arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
   5         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   6         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   7         select ARCH_HAVE_CUSTOM_GPIO_H
   8         select ARCH_HAS_GCOV_PROFILE_ALL
   9         select ARCH_MIGHT_HAVE_PC_PARPORT
  10         select ARCH_SUPPORTS_ATOMIC_RMW
  11         select ARCH_USE_BUILTIN_BSWAP
  12         select ARCH_USE_CMPXCHG_LOCKREF
  13         select ARCH_WANT_IPC_PARSE_VERSION
  14         select BUILDTIME_EXTABLE_SORT if MMU
  15         select CLONE_BACKWARDS
  16         select CPU_PM if (SUSPEND || CPU_IDLE)
  17         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  18         select GENERIC_ALLOCATOR
  19         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  20         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  21         select GENERIC_IDLE_POLL_SETUP
  22         select GENERIC_IRQ_PROBE
  23         select GENERIC_IRQ_SHOW
  24         select GENERIC_PCI_IOMAP
  25         select GENERIC_SCHED_CLOCK
  26         select GENERIC_SMP_IDLE_THREAD
  27         select GENERIC_STRNCPY_FROM_USER
  28         select GENERIC_STRNLEN_USER
  29         select HANDLE_DOMAIN_IRQ
  30         select HARDIRQS_SW_RESEND
  31         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  32         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  33         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
  34         select HAVE_ARCH_KGDB
  35         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  36         select HAVE_ARCH_TRACEHOOK
  37         select HAVE_BPF_JIT
  38         select HAVE_CC_STACKPROTECTOR
  39         select HAVE_CONTEXT_TRACKING
  40         select HAVE_C_RECORDMCOUNT
  41         select HAVE_DEBUG_KMEMLEAK
  42         select HAVE_DMA_API_DEBUG
  43         select HAVE_DMA_ATTRS
  44         select HAVE_DMA_CONTIGUOUS if MMU
  45         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
  46         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  47         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  48         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  49         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  50         select HAVE_GENERIC_DMA_COHERENT
  51         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  52         select HAVE_IDE if PCI || ISA || PCMCIA
  53         select HAVE_IRQ_TIME_ACCOUNTING
  54         select HAVE_KERNEL_GZIP
  55         select HAVE_KERNEL_LZ4
  56         select HAVE_KERNEL_LZMA
  57         select HAVE_KERNEL_LZO
  58         select HAVE_KERNEL_XZ
  59         select HAVE_KPROBES if !XIP_KERNEL
  60         select HAVE_KRETPROBES if (HAVE_KPROBES)
  61         select HAVE_MEMBLOCK
  62         select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
  63         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  64         select HAVE_OPTPROBES if !THUMB2_KERNEL
  65         select HAVE_PERF_EVENTS
  66         select HAVE_PERF_REGS
  67         select HAVE_PERF_USER_STACK_DUMP
  68         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  69         select HAVE_REGS_AND_STACK_ACCESS_API
  70         select HAVE_SYSCALL_TRACEPOINTS
  71         select HAVE_UID16
  72         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  73         select IRQ_FORCED_THREADING
  74         select MODULES_USE_ELF_REL
  75         select NO_BOOTMEM
  76         select OLD_SIGACTION
  77         select OLD_SIGSUSPEND3
  78         select PERF_USE_VMALLOC
  79         select RTC_LIB
  80         select SYS_SUPPORTS_APM_EMULATION
  81         # Above selects are sorted alphabetically; please add new ones
  82         # according to that.  Thanks.
  83         help
  84           The ARM series is a line of low-power-consumption RISC chip designs
  85           licensed by ARM Ltd and targeted at embedded applications and
  86           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  87           manufactured, but legacy ARM-based PC hardware remains popular in
  88           Europe.  There is an ARM Linux project with a web page at
  89           <http://www.arm.linux.org.uk/>.
  90
  91 config ARM_HAS_SG_CHAIN
  92         select ARCH_HAS_SG_CHAIN
  93         bool
  94
  95 config NEED_SG_DMA_LENGTH
  96         bool
  97
  98 config ARM_DMA_USE_IOMMU
  99         bool
 100         select ARM_HAS_SG_CHAIN
 101         select NEED_SG_DMA_LENGTH
 102
 103 if ARM_DMA_USE_IOMMU
 104
 105 config ARM_DMA_IOMMU_ALIGNMENT
 106         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 107         range 4 9
 108         default 8
 109         help
 110           DMA mapping framework by default aligns all buffers to the smallest
 111           PAGE_SIZE order which is greater than or equal to the requested buffer
 112           size. This works well for buffers up to a few hundreds kilobytes, but
 113           for larger buffers it just a waste of address space. Drivers which has
 114           relatively small addressing window (like 64Mib) might run out of
 115           virtual space with just a few allocations.
 116
 117           With this parameter you can specify the maximum PAGE_SIZE order for
 118           DMA IOMMU buffers. Larger buffers will be aligned only to this
 119           specified order. The order is expressed as a power of two multiplied
 120           by the PAGE_SIZE.
 121
 122 endif
 123
 124 config MIGHT_HAVE_PCI
 125         bool
 126
 127 config SYS_SUPPORTS_APM_EMULATION
 128         bool
 129
 130 config HAVE_TCM
 131         bool
 132         select GENERIC_ALLOCATOR
 133
 134 config HAVE_PROC_CPU
 135         bool
 136
 137 config NO_IOPORT_MAP
 138         bool
 139
 140 config EISA
 141         bool
 142         ---help---
 143           The Extended Industry Standard Architecture (EISA) bus was
 144           developed as an open alternative to the IBM MicroChannel bus.
 145
 146           The EISA bus provided some of the features of the IBM MicroChannel
 147           bus while maintaining backward compatibility with cards made for
 148           the older ISA bus.  The EISA bus saw limited use between 1988 and
 149           1995 when it was made obsolete by the PCI bus.
 150
 151           Say Y here if you are building a kernel for an EISA-based machine.
 152
 153           Otherwise, say N.
 154
 155 config SBUS
 156         bool
 157
 158 config STACKTRACE_SUPPORT
 159         bool
 160         default y
 161
 162 config HAVE_LATENCYTOP_SUPPORT
 163         bool
 164         depends on !SMP
 165         default y
 166
 167 config LOCKDEP_SUPPORT
 168         bool
 169         default y
 170
 171 config TRACE_IRQFLAGS_SUPPORT
 172         bool
 173         default y
 174
 175 config RWSEM_XCHGADD_ALGORITHM
 176         bool
 177         default y
 178
 179 config ARCH_HAS_ILOG2_U32
 180         bool
 181
 182 config ARCH_HAS_ILOG2_U64
 183         bool
 184
 185 config ARCH_HAS_BANDGAP
 186         bool
 187
 188 config GENERIC_HWEIGHT
 189         bool
 190         default y
 191
 192 config GENERIC_CALIBRATE_DELAY
 193         bool
 194         default y
 195
 196 config ARCH_MAY_HAVE_PC_FDC
 197         bool
 198
 199 config ZONE_DMA
 200         bool
 201
 202 config NEED_DMA_MAP_STATE
 203        def_bool y
 204
 205 config ARCH_SUPPORTS_UPROBES
 206         def_bool y
 207
 208 config ARCH_HAS_DMA_SET_COHERENT_MASK
 209         bool
 210
 211 config GENERIC_ISA_DMA
 212         bool
 213
 214 config FIQ
 215         bool
 216
 217 config NEED_RET_TO_USER
 218         bool
 219
 220 config ARCH_MTD_XIP
 221         bool
 222
 223 config VECTORS_BASE
 224         hex
 225         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 226         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 227         default 0x00000000
 228         help
 229           The base address of exception vectors.  This must be two pages
 230           in size.
 231
 232 config ARM_PATCH_PHYS_VIRT
 233         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 234         default y
 235         depends on !XIP_KERNEL && MMU
 236         depends on !ARCH_REALVIEW || !SPARSEMEM
 237         help
 238           Patch phys-to-virt and virt-to-phys translation functions at
 239           boot and module load time according to the position of the
 240           kernel in system memory.
 241
 242           This can only be used with non-XIP MMU kernels where the base
 243           of physical memory is at a 16MB boundary.
 244
 245           Only disable this option if you know that you do not require
 246           this feature (eg, building a kernel for a single machine) and
 247           you need to shrink the kernel to the minimal size.
 248
 249 config NEED_MACH_IO_H
 250         bool
 251         help
 252           Select this when mach/io.h is required to provide special
 253           definitions for this platform.  The need for mach/io.h should
 254           be avoided when possible.
 255
 256 config NEED_MACH_MEMORY_H
 257         bool
 258         help
 259           Select this when mach/memory.h is required to provide special
 260           definitions for this platform.  The need for mach/memory.h should
 261           be avoided when possible.
 262
 263 config PHYS_OFFSET
 264         hex "Physical address of main memory" if MMU
 265         depends on !ARM_PATCH_PHYS_VIRT
 266         default DRAM_BASE if !MMU
 267         default 0x00000000 if ARCH_EBSA110 || \
 268                         EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
 269                         ARCH_FOOTBRIDGE || \
 270                         ARCH_INTEGRATOR || \
 271                         ARCH_IOP13XX || \
 272                         ARCH_KS8695 || \
 273                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 274         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 275         default 0x20000000 if ARCH_S5PV210
 276         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 277         default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
 278         default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
 279         default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
 280         default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
 281         help
 282           Please provide the physical address corresponding to the
 283           location of main memory in your system.
 284
 285 config GENERIC_BUG
 286         def_bool y
 287         depends on BUG
 288
 289 source "init/Kconfig"
 290
 291 source "kernel/Kconfig.freezer"
 292
 293 menu "System Type"
 294
 295 config MMU
 296         bool "MMU-based Paged Memory Management Support"
 297         default y
 298         help
 299           Select if you want MMU-based virtualised addressing space
 300           support by paged memory management. If unsure, say 'Y'.
 301
 302 #
 303 # The "ARM system type" choice list is ordered alphabetically by option
 304 # text.  Please add new entries in the option alphabetic order.
 305 #
 306 choice
 307         prompt "ARM system type"
 308         default ARCH_VERSATILE if !MMU
 309         default ARCH_MULTIPLATFORM if MMU
 310
 311 config ARCH_MULTIPLATFORM
 312         bool "Allow multiple platforms to be selected"
 313         depends on MMU
 314         select ARCH_WANT_OPTIONAL_GPIOLIB
 315         select ARM_HAS_SG_CHAIN
 316         select ARM_PATCH_PHYS_VIRT
 317         select AUTO_ZRELADDR
 318         select CLKSRC_OF
 319         select COMMON_CLK
 320         select GENERIC_CLOCKEVENTS
 321         select MIGHT_HAVE_PCI
 322         select MULTI_IRQ_HANDLER
 323         select SPARSE_IRQ
 324         select USE_OF
 325
 326 config ARCH_REALVIEW
 327         bool "ARM Ltd. RealView family"
 328         select ARCH_WANT_OPTIONAL_GPIOLIB
 329         select ARM_AMBA
 330         select ARM_TIMER_SP804
 331         select COMMON_CLK
 332         select COMMON_CLK_VERSATILE
 333         select GENERIC_CLOCKEVENTS
 334         select GPIO_PL061 if GPIOLIB
 335         select ICST
 336         select NEED_MACH_MEMORY_H
 337         select PLAT_VERSATILE
 338         select PLAT_VERSATILE_SCHED_CLOCK
 339         help
 340           This enables support for ARM Ltd RealView boards.
 341
 342 config ARCH_VERSATILE
 343         bool "ARM Ltd. Versatile family"
 344         select ARCH_WANT_OPTIONAL_GPIOLIB
 345         select ARM_AMBA
 346         select ARM_TIMER_SP804
 347         select ARM_VIC
 348         select CLKDEV_LOOKUP
 349         select GENERIC_CLOCKEVENTS
 350         select HAVE_MACH_CLKDEV
 351         select ICST
 352         select PLAT_VERSATILE
 353         select PLAT_VERSATILE_CLOCK
 354         select PLAT_VERSATILE_SCHED_CLOCK
 355         select VERSATILE_FPGA_IRQ
 356         help
 357           This enables support for ARM Ltd Versatile board.
 358
 359 config ARCH_AT91
 360         bool "Atmel AT91"
 361         select ARCH_REQUIRE_GPIOLIB
 362         select CLKDEV_LOOKUP
 363         select IRQ_DOMAIN
 364         select NEED_MACH_IO_H if PCCARD
 365         select PINCTRL
 366         select PINCTRL_AT91
 367         select USE_OF
 368         help
 369           This enables support for systems based on Atmel
 370           AT91RM9200, AT91SAM9 and SAMA5 processors.
 371
 372 config ARCH_CLPS711X
 373         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
 374         select ARCH_REQUIRE_GPIOLIB
 375         select AUTO_ZRELADDR
 376         select CLKSRC_MMIO
 377         select COMMON_CLK
 378         select CPU_ARM720T
 379         select GENERIC_CLOCKEVENTS
 380         select MFD_SYSCON
 381         select SOC_BUS
 382         help
 383           Support for Cirrus Logic 711x/721x/731x based boards.
 384
 385 config ARCH_GEMINI
 386         bool "Cortina Systems Gemini"
 387         select ARCH_REQUIRE_GPIOLIB
 388         select CLKSRC_MMIO
 389         select CPU_FA526
 390         select GENERIC_CLOCKEVENTS
 391         help
 392           Support for the Cortina Systems Gemini family SoCs
 393
 394 config ARCH_EBSA110
 395         bool "EBSA-110"
 396         select ARCH_USES_GETTIMEOFFSET
 397         select CPU_SA110
 398         select ISA
 399         select NEED_MACH_IO_H
 400         select NEED_MACH_MEMORY_H
 401         select NO_IOPORT_MAP
 402         help
 403           This is an evaluation board for the StrongARM processor available
 404           from Digital. It has limited hardware on-board, including an
 405           Ethernet interface, two PCMCIA sockets, two serial ports and a
 406           parallel port.
 407
 408 config ARCH_EFM32
 409         bool "Energy Micro efm32"
 410         depends on !MMU
 411         select ARCH_REQUIRE_GPIOLIB
 412         select ARM_NVIC
 413         select AUTO_ZRELADDR
 414         select CLKSRC_OF
 415         select COMMON_CLK
 416         select CPU_V7M
 417         select GENERIC_CLOCKEVENTS
 418         select NO_DMA
 419         select NO_IOPORT_MAP
 420         select SPARSE_IRQ
 421         select USE_OF
 422         help
 423           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 424           processors.
 425
 426 config ARCH_EP93XX
 427         bool "EP93xx-based"
 428         select ARCH_HAS_HOLES_MEMORYMODEL
 429         select ARCH_REQUIRE_GPIOLIB
 430         select ARCH_USES_GETTIMEOFFSET
 431         select ARM_AMBA
 432         select ARM_VIC
 433         select CLKDEV_LOOKUP
 434         select CPU_ARM920T
 435         help
 436           This enables support for the Cirrus EP93xx series of CPUs.
 437
 438 config ARCH_FOOTBRIDGE
 439         bool "FootBridge"
 440         select CPU_SA110
 441         select FOOTBRIDGE
 442         select GENERIC_CLOCKEVENTS
 443         select HAVE_IDE
 444         select NEED_MACH_IO_H if !MMU
 445         select NEED_MACH_MEMORY_H
 446         help
 447           Support for systems based on the DC21285 companion chip
 448           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 449
 450 config ARCH_NETX
 451         bool "Hilscher NetX based"
 452         select ARM_VIC
 453         select CLKSRC_MMIO
 454         select CPU_ARM926T
 455         select GENERIC_CLOCKEVENTS
 456         help
 457           This enables support for systems based on the Hilscher NetX Soc
 458
 459 config ARCH_IOP13XX
 460         bool "IOP13xx-based"
 461         depends on MMU
 462         select CPU_XSC3
 463         select NEED_MACH_MEMORY_H
 464         select NEED_RET_TO_USER
 465         select PCI
 466         select PLAT_IOP
 467         select VMSPLIT_1G
 468         select SPARSE_IRQ
 469         help
 470           Support for Intel's IOP13XX (XScale) family of processors.
 471
 472 config ARCH_IOP32X
 473         bool "IOP32x-based"
 474         depends on MMU
 475         select ARCH_REQUIRE_GPIOLIB
 476         select CPU_XSCALE
 477         select GPIO_IOP
 478         select NEED_RET_TO_USER
 479         select PCI
 480         select PLAT_IOP
 481         help
 482           Support for Intel's 80219 and IOP32X (XScale) family of
 483           processors.
 484
 485 config ARCH_IOP33X
 486         bool "IOP33x-based"
 487         depends on MMU
 488         select ARCH_REQUIRE_GPIOLIB
 489         select CPU_XSCALE
 490         select GPIO_IOP
 491         select NEED_RET_TO_USER
 492         select PCI
 493         select PLAT_IOP
 494         help
 495           Support for Intel's IOP33X (XScale) family of processors.
 496
 497 config ARCH_IXP4XX
 498         bool "IXP4xx-based"
 499         depends on MMU
 500         select ARCH_HAS_DMA_SET_COHERENT_MASK
 501         select ARCH_REQUIRE_GPIOLIB
 502         select ARCH_SUPPORTS_BIG_ENDIAN
 503         select CLKSRC_MMIO
 504         select CPU_XSCALE
 505         select DMABOUNCE if PCI
 506         select GENERIC_CLOCKEVENTS
 507         select MIGHT_HAVE_PCI
 508         select NEED_MACH_IO_H
 509         select USB_EHCI_BIG_ENDIAN_DESC
 510         select USB_EHCI_BIG_ENDIAN_MMIO
 511         help
 512           Support for Intel's IXP4XX (XScale) family of processors.
 513
 514 config ARCH_DOVE
 515         bool "Marvell Dove"
 516         select ARCH_REQUIRE_GPIOLIB
 517         select CPU_PJ4
 518         select GENERIC_CLOCKEVENTS
 519         select MIGHT_HAVE_PCI
 520         select MVEBU_MBUS
 521         select PINCTRL
 522         select PINCTRL_DOVE
 523         select PLAT_ORION_LEGACY
 524         help
 525           Support for the Marvell Dove SoC 88AP510
 526
 527 config ARCH_MV78XX0
 528         bool "Marvell MV78xx0"
 529         select ARCH_REQUIRE_GPIOLIB
 530         select CPU_FEROCEON
 531         select GENERIC_CLOCKEVENTS
 532         select MVEBU_MBUS
 533         select PCI
 534         select PLAT_ORION_LEGACY
 535         help
 536           Support for the following Marvell MV78xx0 series SoCs:
 537           MV781x0, MV782x0.
 538
 539 config ARCH_ORION5X
 540         bool "Marvell Orion"
 541         depends on MMU
 542         select ARCH_REQUIRE_GPIOLIB
 543         select CPU_FEROCEON
 544         select GENERIC_CLOCKEVENTS
 545         select MVEBU_MBUS
 546         select PCI
 547         select PLAT_ORION_LEGACY
 548         help
 549           Support for the following Marvell Orion 5x series SoCs:
 550           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
 551           Orion-2 (5281), Orion-1-90 (6183).
 552
 553 config ARCH_MMP
 554         bool "Marvell PXA168/910/MMP2"
 555         depends on MMU
 556         select ARCH_REQUIRE_GPIOLIB
 557         select CLKDEV_LOOKUP
 558         select GENERIC_ALLOCATOR
 559         select GENERIC_CLOCKEVENTS
 560         select GPIO_PXA
 561         select IRQ_DOMAIN
 562         select MULTI_IRQ_HANDLER
 563         select PINCTRL
 564         select PLAT_PXA
 565         select SPARSE_IRQ
 566         help
 567           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 568
 569 config ARCH_KS8695
 570         bool "Micrel/Kendin KS8695"
 571         select ARCH_REQUIRE_GPIOLIB
 572         select CLKSRC_MMIO
 573         select CPU_ARM922T
 574         select GENERIC_CLOCKEVENTS
 575         select NEED_MACH_MEMORY_H
 576         help
 577           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 578           System-on-Chip devices.
 579
 580 config ARCH_W90X900
 581         bool "Nuvoton W90X900 CPU"
 582         select ARCH_REQUIRE_GPIOLIB
 583         select CLKDEV_LOOKUP
 584         select CLKSRC_MMIO
 585         select CPU_ARM926T
 586         select GENERIC_CLOCKEVENTS
 587         help
 588           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 589           At present, the w90x900 has been renamed nuc900, regarding
 590           the ARM series product line, you can login the following
 591           link address to know more.
 592
 593           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 594                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 595
 596 config ARCH_LPC32XX
 597         bool "NXP LPC32XX"
 598         select ARCH_REQUIRE_GPIOLIB
 599         select ARM_AMBA
 600         select CLKDEV_LOOKUP
 601         select CLKSRC_MMIO
 602         select CPU_ARM926T
 603         select GENERIC_CLOCKEVENTS
 604         select HAVE_IDE
 605         select USE_OF
 606         help
 607           Support for the NXP LPC32XX family of processors
 608
 609 config ARCH_PXA
 610         bool "PXA2xx/PXA3xx-based"
 611         depends on MMU
 612         select ARCH_MTD_XIP
 613         select ARCH_REQUIRE_GPIOLIB
 614         select ARM_CPU_SUSPEND if PM
 615         select AUTO_ZRELADDR
 616         select CLKDEV_LOOKUP
 617         select CLKSRC_MMIO
 618         select CLKSRC_OF
 619         select GENERIC_CLOCKEVENTS
 620         select GPIO_PXA
 621         select HAVE_IDE
 622         select MULTI_IRQ_HANDLER
 623         select PLAT_PXA
 624         select SPARSE_IRQ
 625         help
 626           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 627
 628 config ARCH_SHMOBILE_LEGACY
 629         bool "Renesas ARM SoCs (non-multiplatform)"
 630         select ARCH_SHMOBILE
 631         select ARM_PATCH_PHYS_VIRT if MMU
 632         select CLKDEV_LOOKUP
 633         select CPU_V7
 634         select GENERIC_CLOCKEVENTS
 635         select HAVE_ARM_SCU if SMP
 636         select HAVE_ARM_TWD if SMP
 637         select HAVE_MACH_CLKDEV
 638         select HAVE_SMP
 639         select MIGHT_HAVE_CACHE_L2X0
 640         select MULTI_IRQ_HANDLER
 641         select NO_IOPORT_MAP
 642         select PINCTRL
 643         select PM_GENERIC_DOMAINS if PM
 644         select SH_CLK_CPG
 645         select SPARSE_IRQ
 646         help
 647           Support for Renesas ARM SoC platforms using a non-multiplatform
 648           kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
 649           and RZ families.
 650
 651 config ARCH_RPC
 652         bool "RiscPC"
 653         select ARCH_ACORN
 654         select ARCH_MAY_HAVE_PC_FDC
 655         select ARCH_SPARSEMEM_ENABLE
 656         select ARCH_USES_GETTIMEOFFSET
 657         select CPU_SA110
 658         select FIQ
 659         select HAVE_IDE
 660         select HAVE_PATA_PLATFORM
 661         select ISA_DMA_API
 662         select NEED_MACH_IO_H
 663         select NEED_MACH_MEMORY_H
 664         select NO_IOPORT_MAP
 665         select VIRT_TO_BUS
 666         help
 667           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 668           CD-ROM interface, serial and parallel port, and the floppy drive.
 669
 670 config ARCH_SA1100
 671         bool "SA1100-based"
 672         select ARCH_MTD_XIP
 673         select ARCH_REQUIRE_GPIOLIB
 674         select ARCH_SPARSEMEM_ENABLE
 675         select CLKDEV_LOOKUP
 676         select CLKSRC_MMIO
 677         select CPU_FREQ
 678         select CPU_SA1100
 679         select GENERIC_CLOCKEVENTS
 680         select HAVE_IDE
 681         select IRQ_DOMAIN
 682         select ISA
 683         select MULTI_IRQ_HANDLER
 684         select NEED_MACH_MEMORY_H
 685         select SPARSE_IRQ
 686         help
 687           Support for StrongARM 11x0 based boards.
 688
 689 config ARCH_S3C24XX
 690         bool "Samsung S3C24XX SoCs"
 691         select ARCH_REQUIRE_GPIOLIB
 692         select ATAGS
 693         select CLKDEV_LOOKUP
 694         select CLKSRC_SAMSUNG_PWM
 695         select GENERIC_CLOCKEVENTS
 696         select GPIO_SAMSUNG
 697         select HAVE_S3C2410_I2C if I2C
 698         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 699         select HAVE_S3C_RTC if RTC_CLASS
 700         select MULTI_IRQ_HANDLER
 701         select NEED_MACH_IO_H
 702         select SAMSUNG_ATAGS
 703         help
 704           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 705           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 706           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 707           Samsung SMDK2410 development board (and derivatives).
 708
 709 config ARCH_S3C64XX
 710         bool "Samsung S3C64XX"
 711         select ARCH_REQUIRE_GPIOLIB
 712         select ARM_AMBA
 713         select ARM_VIC
 714         select ATAGS
 715         select CLKDEV_LOOKUP
 716         select CLKSRC_SAMSUNG_PWM
 717         select COMMON_CLK_SAMSUNG
 718         select CPU_V6K
 719         select GENERIC_CLOCKEVENTS
 720         select GPIO_SAMSUNG
 721         select HAVE_S3C2410_I2C if I2C
 722         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 723         select HAVE_TCM
 724         select NO_IOPORT_MAP
 725         select PLAT_SAMSUNG
 726         select PM_GENERIC_DOMAINS if PM
 727         select S3C_DEV_NAND
 728         select S3C_GPIO_TRACK
 729         select SAMSUNG_ATAGS
 730         select SAMSUNG_WAKEMASK
 731         select SAMSUNG_WDT_RESET
 732         help
 733           Samsung S3C64XX series based systems
 734
 735 config ARCH_DAVINCI
 736         bool "TI DaVinci"
 737         select ARCH_HAS_HOLES_MEMORYMODEL
 738         select ARCH_REQUIRE_GPIOLIB
 739         select CLKDEV_LOOKUP
 740         select GENERIC_ALLOCATOR
 741         select GENERIC_CLOCKEVENTS
 742         select GENERIC_IRQ_CHIP
 743         select HAVE_IDE
 744         select TI_PRIV_EDMA
 745         select USE_OF
 746         select ZONE_DMA
 747         help
 748           Support for TI's DaVinci platform.
 749
 750 config ARCH_OMAP1
 751         bool "TI OMAP1"
 752         depends on MMU
 753         select ARCH_HAS_HOLES_MEMORYMODEL
 754         select ARCH_OMAP
 755         select ARCH_REQUIRE_GPIOLIB
 756         select CLKDEV_LOOKUP
 757         select CLKSRC_MMIO
 758         select GENERIC_CLOCKEVENTS
 759         select GENERIC_IRQ_CHIP
 760         select HAVE_IDE
 761         select IRQ_DOMAIN
 762         select NEED_MACH_IO_H if PCCARD
 763         select NEED_MACH_MEMORY_H
 764         help
 765           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 766
 767 endchoice
 768
 769 menu "Multiple platform selection"
 770         depends on ARCH_MULTIPLATFORM
 771
 772 comment "CPU Core family selection"
 773
 774 config ARCH_MULTI_V4
 775         bool "ARMv4 based platforms (FA526)"
 776         depends on !ARCH_MULTI_V6_V7
 777         select ARCH_MULTI_V4_V5
 778         select CPU_FA526
 779
 780 config ARCH_MULTI_V4T
 781         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 782         depends on !ARCH_MULTI_V6_V7
 783         select ARCH_MULTI_V4_V5
 784         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 785                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 786                 CPU_ARM925T || CPU_ARM940T)
 787
 788 config ARCH_MULTI_V5
 789         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 790         depends on !ARCH_MULTI_V6_V7
 791         select ARCH_MULTI_V4_V5
 792         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 793                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 794                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 795
 796 config ARCH_MULTI_V4_V5
 797         bool
 798
 799 config ARCH_MULTI_V6
 800         bool "ARMv6 based platforms (ARM11)"
 801         select ARCH_MULTI_V6_V7
 802         select CPU_V6K
 803
 804 config ARCH_MULTI_V7
 805         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 806         default y
 807         select ARCH_MULTI_V6_V7
 808         select CPU_V7
 809         select HAVE_SMP
 810
 811 config ARCH_MULTI_V6_V7
 812         bool
 813         select MIGHT_HAVE_CACHE_L2X0
 814
 815 config ARCH_MULTI_CPU_AUTO
 816         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 817         select ARCH_MULTI_V5
 818
 819 endmenu
 820
 821 config ARCH_VIRT
 822         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
 823         select ARM_AMBA
 824         select ARM_GIC
 825         select ARM_PSCI
 826         select HAVE_ARM_ARCH_TIMER
 827
 828 #
 829 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 830 # Kconfigs may be included either alphabetically (according to the
 831 # plat- suffix) or along side the corresponding mach-* source.
 832 #
 833 source "arch/arm/mach-mvebu/Kconfig"
 834
 835 source "arch/arm/mach-asm9260/Kconfig"
 836
 837 source "arch/arm/mach-at91/Kconfig"
 838
 839 source "arch/arm/mach-axxia/Kconfig"
 840
 841 source "arch/arm/mach-bcm/Kconfig"
 842
 843 source "arch/arm/mach-berlin/Kconfig"
 844
 845 source "arch/arm/mach-clps711x/Kconfig"
 846
 847 source "arch/arm/mach-cns3xxx/Kconfig"
 848
 849 source "arch/arm/mach-davinci/Kconfig"
 850
 851 source "arch/arm/mach-digicolor/Kconfig"
 852
 853 source "arch/arm/mach-dove/Kconfig"
 854
 855 source "arch/arm/mach-ep93xx/Kconfig"
 856
 857 source "arch/arm/mach-footbridge/Kconfig"
 858
 859 source "arch/arm/mach-gemini/Kconfig"
 860
 861 source "arch/arm/mach-highbank/Kconfig"
 862
 863 source "arch/arm/mach-hisi/Kconfig"
 864
 865 source "arch/arm/mach-integrator/Kconfig"
 866
 867 source "arch/arm/mach-iop32x/Kconfig"
 868
 869 source "arch/arm/mach-iop33x/Kconfig"
 870
 871 source "arch/arm/mach-iop13xx/Kconfig"
 872
 873 source "arch/arm/mach-ixp4xx/Kconfig"
 874
 875 source "arch/arm/mach-keystone/Kconfig"
 876
 877 source "arch/arm/mach-ks8695/Kconfig"
 878
 879 source "arch/arm/mach-meson/Kconfig"
 880
 881 source "arch/arm/mach-moxart/Kconfig"
 882
 883 source "arch/arm/mach-mv78xx0/Kconfig"
 884
 885 source "arch/arm/mach-imx/Kconfig"
 886
 887 source "arch/arm/mach-mediatek/Kconfig"
 888
 889 source "arch/arm/mach-mxs/Kconfig"
 890
 891 source "arch/arm/mach-netx/Kconfig"
 892
 893 source "arch/arm/mach-nomadik/Kconfig"
 894
 895 source "arch/arm/mach-nspire/Kconfig"
 896
 897 source "arch/arm/plat-omap/Kconfig"
 898
 899 source "arch/arm/mach-omap1/Kconfig"
 900
 901 source "arch/arm/mach-omap2/Kconfig"
 902
 903 source "arch/arm/mach-orion5x/Kconfig"
 904
 905 source "arch/arm/mach-picoxcell/Kconfig"
 906
 907 source "arch/arm/mach-pxa/Kconfig"
 908 source "arch/arm/plat-pxa/Kconfig"
 909
 910 source "arch/arm/mach-mmp/Kconfig"
 911
 912 source "arch/arm/mach-qcom/Kconfig"
 913
 914 source "arch/arm/mach-realview/Kconfig"
 915
 916 source "arch/arm/mach-rockchip/Kconfig"
 917
 918 source "arch/arm/mach-sa1100/Kconfig"
 919
 920 source "arch/arm/mach-socfpga/Kconfig"
 921
 922 source "arch/arm/mach-spear/Kconfig"
 923
 924 source "arch/arm/mach-sti/Kconfig"
 925
 926 source "arch/arm/mach-s3c24xx/Kconfig"
 927
 928 source "arch/arm/mach-s3c64xx/Kconfig"
 929
 930 source "arch/arm/mach-s5pv210/Kconfig"
 931
 932 source "arch/arm/mach-exynos/Kconfig"
 933 source "arch/arm/plat-samsung/Kconfig"
 934
 935 source "arch/arm/mach-shmobile/Kconfig"
 936
 937 source "arch/arm/mach-sunxi/Kconfig"
 938
 939 source "arch/arm/mach-prima2/Kconfig"
 940
 941 source "arch/arm/mach-tegra/Kconfig"
 942
 943 source "arch/arm/mach-u300/Kconfig"
 944
 945 source "arch/arm/mach-ux500/Kconfig"
 946
 947 source "arch/arm/mach-versatile/Kconfig"
 948
 949 source "arch/arm/mach-vexpress/Kconfig"
 950 source "arch/arm/plat-versatile/Kconfig"
 951
 952 source "arch/arm/mach-vt8500/Kconfig"
 953
 954 source "arch/arm/mach-w90x900/Kconfig"
 955
 956 source "arch/arm/mach-zynq/Kconfig"
 957
 958 # Definitions to make life easier
 959 config ARCH_ACORN
 960         bool
 961
 962 config PLAT_IOP
 963         bool
 964         select GENERIC_CLOCKEVENTS
 965
 966 config PLAT_ORION
 967         bool
 968         select CLKSRC_MMIO
 969         select COMMON_CLK
 970         select GENERIC_IRQ_CHIP
 971         select IRQ_DOMAIN
 972
 973 config PLAT_ORION_LEGACY
 974         bool
 975         select PLAT_ORION
 976
 977 config PLAT_PXA
 978         bool
 979
 980 config PLAT_VERSATILE
 981         bool
 982
 983 config ARM_TIMER_SP804
 984         bool
 985         select CLKSRC_MMIO
 986         select CLKSRC_OF if OF
 987
 988 source "arch/arm/firmware/Kconfig"
 989
 990 source arch/arm/mm/Kconfig
 991
 992 config IWMMXT
 993         bool "Enable iWMMXt support"
 994         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
 995         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
 996         help
 997           Enable support for iWMMXt context switching at run time if
 998           running on a CPU that supports it.
 999
1000 config MULTI_IRQ_HANDLER
1001         bool
1002         help
1003           Allow each machine to specify it's own IRQ handler at run time.
1004
1005 if !MMU
1006 source "arch/arm/Kconfig-nommu"
1007 endif
1008
1009 config PJ4B_ERRATA_4742
1010         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1011         depends on CPU_PJ4B && MACH_ARMADA_370
1012         default y
1013         help
1014           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1015           Event (WFE) IDLE states, a specific timing sensitivity exists between
1016           the retiring WFI/WFE instructions and the newly issued subsequent
1017           instructions.  This sensitivity can result in a CPU hang scenario.
1018           Workaround:
1019           The software must insert either a Data Synchronization Barrier (DSB)
1020           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1021           instruction
1022
1023 config ARM_ERRATA_326103
1024         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1025         depends on CPU_V6
1026         help
1027           Executing a SWP instruction to read-only memory does not set bit 11
1028           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1029           treat the access as a read, preventing a COW from occurring and
1030           causing the faulting task to livelock.
1031
1032 config ARM_ERRATA_411920
1033         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1034         depends on CPU_V6 || CPU_V6K
1035         help
1036           Invalidation of the Instruction Cache operation can
1037           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1038           It does not affect the MPCore. This option enables the ARM Ltd.
1039           recommended workaround.
1040
1041 config ARM_ERRATA_430973
1042         bool "ARM errata: Stale prediction on replaced interworking branch"
1043         depends on CPU_V7
1044         help
1045           This option enables the workaround for the 430973 Cortex-A8
1046           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1047           interworking branch is replaced with another code sequence at the
1048           same virtual address, whether due to self-modifying code or virtual
1049           to physical address re-mapping, Cortex-A8 does not recover from the
1050           stale interworking branch prediction. This results in Cortex-A8
1051           executing the new code sequence in the incorrect ARM or Thumb state.
1052           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1053           and also flushes the branch target cache at every context switch.
1054           Note that setting specific bits in the ACTLR register may not be
1055           available in non-secure mode.
1056
1057 config ARM_ERRATA_458693
1058         bool "ARM errata: Processor deadlock when a false hazard is created"
1059         depends on CPU_V7
1060         depends on !ARCH_MULTIPLATFORM
1061         help
1062           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1063           erratum. For very specific sequences of memory operations, it is
1064           possible for a hazard condition intended for a cache line to instead
1065           be incorrectly associated with a different cache line. This false
1066           hazard might then cause a processor deadlock. The workaround enables
1067           the L1 caching of the NEON accesses and disables the PLD instruction
1068           in the ACTLR register. Note that setting specific bits in the ACTLR
1069           register may not be available in non-secure mode.
1070
1071 config ARM_ERRATA_460075
1072         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1073         depends on CPU_V7
1074         depends on !ARCH_MULTIPLATFORM
1075         help
1076           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1077           erratum. Any asynchronous access to the L2 cache may encounter a
1078           situation in which recent store transactions to the L2 cache are lost
1079           and overwritten with stale memory contents from external memory. The
1080           workaround disables the write-allocate mode for the L2 cache via the
1081           ACTLR register. Note that setting specific bits in the ACTLR register
1082           may not be available in non-secure mode.
1083
1084 config ARM_ERRATA_742230
1085         bool "ARM errata: DMB operation may be faulty"
1086         depends on CPU_V7 && SMP
1087         depends on !ARCH_MULTIPLATFORM
1088         help
1089           This option enables the workaround for the 742230 Cortex-A9
1090           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1091           between two write operations may not ensure the correct visibility
1092           ordering of the two writes. This workaround sets a specific bit in
1093           the diagnostic register of the Cortex-A9 which causes the DMB
1094           instruction to behave as a DSB, ensuring the correct behaviour of
1095           the two writes.
1096
1097 config ARM_ERRATA_742231
1098         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1099         depends on CPU_V7 && SMP
1100         depends on !ARCH_MULTIPLATFORM
1101         help
1102           This option enables the workaround for the 742231 Cortex-A9
1103           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1104           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1105           accessing some data located in the same cache line, may get corrupted
1106           data due to bad handling of the address hazard when the line gets
1107           replaced from one of the CPUs at the same time as another CPU is
1108           accessing it. This workaround sets specific bits in the diagnostic
1109           register of the Cortex-A9 which reduces the linefill issuing
1110           capabilities of the processor.
1111
1112 config ARM_ERRATA_643719
1113         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1114         depends on CPU_V7 && SMP
1115         help
1116           This option enables the workaround for the 643719 Cortex-A9 (prior to
1117           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1118           register returns zero when it should return one. The workaround
1119           corrects this value, ensuring cache maintenance operations which use
1120           it behave as intended and avoiding data corruption.
1121
1122 config ARM_ERRATA_720789
1123         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1124         depends on CPU_V7
1125         help
1126           This option enables the workaround for the 720789 Cortex-A9 (prior to
1127           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1128           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1129           As a consequence of this erratum, some TLB entries which should be
1130           invalidated are not, resulting in an incoherency in the system page
1131           tables. The workaround changes the TLB flushing routines to invalidate
1132           entries regardless of the ASID.
1133
1134 config ARM_ERRATA_743622
1135         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1136         depends on CPU_V7
1137         depends on !ARCH_MULTIPLATFORM
1138         help
1139           This option enables the workaround for the 743622 Cortex-A9
1140           (r2p*) erratum. Under very rare conditions, a faulty
1141           optimisation in the Cortex-A9 Store Buffer may lead to data
1142           corruption. This workaround sets a specific bit in the diagnostic
1143           register of the Cortex-A9 which disables the Store Buffer
1144           optimisation, preventing the defect from occurring. This has no
1145           visible impact on the overall performance or power consumption of the
1146           processor.
1147
1148 config ARM_ERRATA_751472
1149         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1150         depends on CPU_V7
1151         depends on !ARCH_MULTIPLATFORM
1152         help
1153           This option enables the workaround for the 751472 Cortex-A9 (prior
1154           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1155           completion of a following broadcasted operation if the second
1156           operation is received by a CPU before the ICIALLUIS has completed,
1157           potentially leading to corrupted entries in the cache or TLB.
1158
1159 config ARM_ERRATA_754322
1160         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1161         depends on CPU_V7
1162         help
1163           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1164           r3p*) erratum. A speculative memory access may cause a page table walk
1165           which starts prior to an ASID switch but completes afterwards. This
1166           can populate the micro-TLB with a stale entry which may be hit with
1167           the new ASID. This workaround places two dsb instructions in the mm
1168           switching code so that no page table walks can cross the ASID switch.
1169
1170 config ARM_ERRATA_754327
1171         bool "ARM errata: no automatic Store Buffer drain"
1172         depends on CPU_V7 && SMP
1173         help
1174           This option enables the workaround for the 754327 Cortex-A9 (prior to
1175           r2p0) erratum. The Store Buffer does not have any automatic draining
1176           mechanism and therefore a livelock may occur if an external agent
1177           continuously polls a memory location waiting to observe an update.
1178           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1179           written polling loops from denying visibility of updates to memory.
1180
1181 config ARM_ERRATA_364296
1182         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1183         depends on CPU_V6
1184         help
1185           This options enables the workaround for the 364296 ARM1136
1186           r0p2 erratum (possible cache data corruption with
1187           hit-under-miss enabled). It sets the undocumented bit 31 in
1188           the auxiliary control register and the FI bit in the control
1189           register, thus disabling hit-under-miss without putting the
1190           processor into full low interrupt latency mode. ARM11MPCore
1191           is not affected.
1192
1193 config ARM_ERRATA_764369
1194         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1195         depends on CPU_V7 && SMP
1196         help
1197           This option enables the workaround for erratum 764369
1198           affecting Cortex-A9 MPCore with two or more processors (all
1199           current revisions). Under certain timing circumstances, a data
1200           cache line maintenance operation by MVA targeting an Inner
1201           Shareable memory region may fail to proceed up to either the
1202           Point of Coherency or to the Point of Unification of the
1203           system. This workaround adds a DSB instruction before the
1204           relevant cache maintenance functions and sets a specific bit
1205           in the diagnostic control register of the SCU.
1206
1207 config ARM_ERRATA_775420
1208        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1209        depends on CPU_V7
1210        help
1211          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1212          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1213          operation aborts with MMU exception, it might cause the processor
1214          to deadlock. This workaround puts DSB before executing ISB if
1215          an abort may occur on cache maintenance.
1216
1217 config ARM_ERRATA_798181
1218         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1219         depends on CPU_V7 && SMP
1220         help
1221           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1222           adequately shooting down all use of the old entries. This
1223           option enables the Linux kernel workaround for this erratum
1224           which sends an IPI to the CPUs that are running the same ASID
1225           as the one being invalidated.
1226
1227 config ARM_ERRATA_773022
1228         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1229         depends on CPU_V7
1230         help
1231           This option enables the workaround for the 773022 Cortex-A15
1232           (up to r0p4) erratum. In certain rare sequences of code, the
1233           loop buffer may deliver incorrect instructions. This
1234           workaround disables the loop buffer to avoid the erratum.
1235
1236 endmenu
1237
1238 source "arch/arm/common/Kconfig"
1239
1240 menu "Bus support"
1241
1242 config ISA
1243         bool
1244         help
1245           Find out whether you have ISA slots on your motherboard.  ISA is the
1246           name of a bus system, i.e. the way the CPU talks to the other stuff
1247           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1248           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1249           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1250
1251 # Select ISA DMA controller support
1252 config ISA_DMA
1253         bool
1254         select ISA_DMA_API
1255
1256 # Select ISA DMA interface
1257 config ISA_DMA_API
1258         bool
1259
1260 config PCI
1261         bool "PCI support" if MIGHT_HAVE_PCI
1262         help
1263           Find out whether you have a PCI motherboard. PCI is the name of a
1264           bus system, i.e. the way the CPU talks to the other stuff inside
1265           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1266           VESA. If you have PCI, say Y, otherwise N.
1267
1268 config PCI_DOMAINS
1269         bool
1270         depends on PCI
1271
1272 config PCI_DOMAINS_GENERIC
1273         def_bool PCI_DOMAINS
1274
1275 config PCI_NANOENGINE
1276         bool "BSE nanoEngine PCI support"
1277         depends on SA1100_NANOENGINE
1278         help
1279           Enable PCI on the BSE nanoEngine board.
1280
1281 config PCI_SYSCALL
1282         def_bool PCI
1283
1284 config PCI_HOST_ITE8152
1285         bool
1286         depends on PCI && MACH_ARMCORE
1287         default y
1288         select DMABOUNCE
1289
1290 source "drivers/pci/Kconfig"
1291 source "drivers/pci/pcie/Kconfig"
1292
1293 source "drivers/pcmcia/Kconfig"
1294
1295 endmenu
1296
1297 menu "Kernel Features"
1298
1299 config HAVE_SMP
1300         bool
1301         help
1302           This option should be selected by machines which have an SMP-
1303           capable CPU.
1304
1305           The only effect of this option is to make the SMP-related
1306           options available to the user for configuration.
1307
1308 config SMP
1309         bool "Symmetric Multi-Processing"
1310         depends on CPU_V6K || CPU_V7
1311         depends on GENERIC_CLOCKEVENTS
1312         depends on HAVE_SMP
1313         depends on MMU || ARM_MPU
1314         help
1315           This enables support for systems with more than one CPU. If you have
1316           a system with only one CPU, say N. If you have a system with more
1317           than one CPU, say Y.
1318
1319           If you say N here, the kernel will run on uni- and multiprocessor
1320           machines, but will use only one CPU of a multiprocessor machine. If
1321           you say Y here, the kernel will run on many, but not all,
1322           uniprocessor machines. On a uniprocessor machine, the kernel
1323           will run faster if you say N here.
1324
1325           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1326           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1327           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1328
1329           If you don't know what to do here, say N.
1330
1331 config SMP_ON_UP
1332         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1333         depends on SMP && !XIP_KERNEL && MMU
1334         default y
1335         help
1336           SMP kernels contain instructions which fail on non-SMP processors.
1337           Enabling this option allows the kernel to modify itself to make
1338           these instructions safe.  Disabling it allows about 1K of space
1339           savings.
1340
1341           If you don't know what to do here, say Y.
1342
1343 config ARM_CPU_TOPOLOGY
1344         bool "Support cpu topology definition"
1345         depends on SMP && CPU_V7
1346         default y
1347         help
1348           Support ARM cpu topology definition. The MPIDR register defines
1349           affinity between processors which is then used to describe the cpu
1350           topology of an ARM System.
1351
1352 config SCHED_MC
1353         bool "Multi-core scheduler support"
1354         depends on ARM_CPU_TOPOLOGY
1355         help
1356           Multi-core scheduler support improves the CPU scheduler's decision
1357           making when dealing with multi-core CPU chips at a cost of slightly
1358           increased overhead in some places. If unsure say N here.
1359
1360 config SCHED_SMT
1361         bool "SMT scheduler support"
1362         depends on ARM_CPU_TOPOLOGY
1363         help
1364           Improves the CPU scheduler's decision making when dealing with
1365           MultiThreading at a cost of slightly increased overhead in some
1366           places. If unsure say N here.
1367
1368 config HAVE_ARM_SCU
1369         bool
1370         help
1371           This option enables support for the ARM system coherency unit
1372
1373 config HAVE_ARM_ARCH_TIMER
1374         bool "Architected timer support"
1375         depends on CPU_V7
1376         select ARM_ARCH_TIMER
1377         select GENERIC_CLOCKEVENTS
1378         help
1379           This option enables support for the ARM architected timer
1380
1381 config HAVE_ARM_TWD
1382         bool
1383         depends on SMP
1384         select CLKSRC_OF if OF
1385         help
1386           This options enables support for the ARM timer and watchdog unit
1387
1388 config MCPM
1389         bool "Multi-Cluster Power Management"
1390         depends on CPU_V7 && SMP
1391         help
1392           This option provides the common power management infrastructure
1393           for (multi-)cluster based systems, such as big.LITTLE based
1394           systems.
1395
1396 config MCPM_QUAD_CLUSTER
1397         bool
1398         depends on MCPM
1399         help
1400           To avoid wasting resources unnecessarily, MCPM only supports up
1401           to 2 clusters by default.
1402           Platforms with 3 or 4 clusters that use MCPM must select this
1403           option to allow the additional clusters to be managed.
1404
1405 config BIG_LITTLE
1406         bool "big.LITTLE support (Experimental)"
1407         depends on CPU_V7 && SMP
1408         select MCPM
1409         help
1410           This option enables support selections for the big.LITTLE
1411           system architecture.
1412
1413 config BL_SWITCHER
1414         bool "big.LITTLE switcher support"
1415         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1416         select ARM_CPU_SUSPEND
1417         select CPU_PM
1418         help
1419           The big.LITTLE "switcher" provides the core functionality to
1420           transparently handle transition between a cluster of A15's
1421           and a cluster of A7's in a big.LITTLE system.
1422
1423 config BL_SWITCHER_DUMMY_IF
1424         tristate "Simple big.LITTLE switcher user interface"
1425         depends on BL_SWITCHER && DEBUG_KERNEL
1426         help
1427           This is a simple and dummy char dev interface to control
1428           the big.LITTLE switcher core code.  It is meant for
1429           debugging purposes only.
1430
1431 choice
1432         prompt "Memory split"
1433         depends on MMU
1434         default VMSPLIT_3G
1435         help
1436           Select the desired split between kernel and user memory.
1437
1438           If you are not absolutely sure what you are doing, leave this
1439           option alone!
1440
1441         config VMSPLIT_3G
1442                 bool "3G/1G user/kernel split"
1443         config VMSPLIT_2G
1444                 bool "2G/2G user/kernel split"
1445         config VMSPLIT_1G
1446                 bool "1G/3G user/kernel split"
1447 endchoice
1448
1449 config PAGE_OFFSET
1450         hex
1451         default PHYS_OFFSET if !MMU
1452         default 0x40000000 if VMSPLIT_1G
1453         default 0x80000000 if VMSPLIT_2G
1454         default 0xC0000000
1455
1456 config NR_CPUS
1457         int "Maximum number of CPUs (2-32)"
1458         range 2 32
1459         depends on SMP
1460         default "4"
1461
1462 config HOTPLUG_CPU
1463         bool "Support for hot-pluggable CPUs"
1464         depends on SMP
1465         help
1466           Say Y here to experiment with turning CPUs off and on.  CPUs
1467           can be controlled through /sys/devices/system/cpu.
1468
1469 config ARM_PSCI
1470         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1471         depends on CPU_V7
1472         help
1473           Say Y here if you want Linux to communicate with system firmware
1474           implementing the PSCI specification for CPU-centric power
1475           management operations described in ARM document number ARM DEN
1476           0022A ("Power State Coordination Interface System Software on
1477           ARM processors").
1478
1479 # The GPIO number here must be sorted by descending number. In case of
1480 # a multiplatform kernel, we just want the highest value required by the
1481 # selected platforms.
1482 config ARCH_NR_GPIO
1483         int
1484         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA || ARCH_ZYNQ
1485         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1486                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1487         default 416 if ARCH_SUNXI
1488         default 392 if ARCH_U8500
1489         default 352 if ARCH_VT8500
1490         default 288 if ARCH_ROCKCHIP
1491         default 264 if MACH_H4700
1492         default 0
1493         help
1494           Maximum number of GPIOs in the system.
1495
1496           If unsure, leave the default value.
1497
1498 source kernel/Kconfig.preempt
1499
1500 config HZ_FIXED
1501         int
1502         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1503                 ARCH_S5PV210 || ARCH_EXYNOS4
1504         default AT91_TIMER_HZ if ARCH_AT91
1505         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1506         default 0
1507
1508 choice
1509         depends on HZ_FIXED = 0
1510         prompt "Timer frequency"
1511
1512 config HZ_100
1513         bool "100 Hz"
1514
1515 config HZ_200
1516         bool "200 Hz"
1517
1518 config HZ_250
1519         bool "250 Hz"
1520
1521 config HZ_300
1522         bool "300 Hz"
1523
1524 config HZ_500
1525         bool "500 Hz"
1526
1527 config HZ_1000
1528         bool "1000 Hz"
1529
1530 endchoice
1531
1532 config HZ
1533         int
1534         default HZ_FIXED if HZ_FIXED != 0
1535         default 100 if HZ_100
1536         default 200 if HZ_200
1537         default 250 if HZ_250
1538         default 300 if HZ_300
1539         default 500 if HZ_500
1540         default 1000
1541
1542 config SCHED_HRTICK
1543         def_bool HIGH_RES_TIMERS
1544
1545 config THUMB2_KERNEL
1546         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1547         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1548         default y if CPU_THUMBONLY
1549         select AEABI
1550         select ARM_ASM_UNIFIED
1551         select ARM_UNWIND
1552         help
1553           By enabling this option, the kernel will be compiled in
1554           Thumb-2 mode. A compiler/assembler that understand the unified
1555           ARM-Thumb syntax is needed.
1556
1557           If unsure, say N.
1558
1559 config THUMB2_AVOID_R_ARM_THM_JUMP11
1560         bool "Work around buggy Thumb-2 short branch relocations in gas"
1561         depends on THUMB2_KERNEL && MODULES
1562         default y
1563         help
1564           Various binutils versions can resolve Thumb-2 branches to
1565           locally-defined, preemptible global symbols as short-range "b.n"
1566           branch instructions.
1567
1568           This is a problem, because there's no guarantee the final
1569           destination of the symbol, or any candidate locations for a
1570           trampoline, are within range of the branch.  For this reason, the
1571           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1572           relocation in modules at all, and it makes little sense to add
1573           support.
1574
1575           The symptom is that the kernel fails with an "unsupported
1576           relocation" error when loading some modules.
1577
1578           Until fixed tools are available, passing
1579           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1580           code which hits this problem, at the cost of a bit of extra runtime
1581           stack usage in some cases.
1582
1583           The problem is described in more detail at:
1584               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1585
1586           Only Thumb-2 kernels are affected.
1587
1588           Unless you are sure your tools don't have this problem, say Y.
1589
1590 config ARM_ASM_UNIFIED
1591         bool
1592
1593 config AEABI
1594         bool "Use the ARM EABI to compile the kernel"
1595         help
1596           This option allows for the kernel to be compiled using the latest
1597           ARM ABI (aka EABI).  This is only useful if you are using a user
1598           space environment that is also compiled with EABI.
1599
1600           Since there are major incompatibilities between the legacy ABI and
1601           EABI, especially with regard to structure member alignment, this
1602           option also changes the kernel syscall calling convention to
1603           disambiguate both ABIs and allow for backward compatibility support
1604           (selected with CONFIG_OABI_COMPAT).
1605
1606           To use this you need GCC version 4.0.0 or later.
1607
1608 config OABI_COMPAT
1609         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1610         depends on AEABI && !THUMB2_KERNEL
1611         help
1612           This option preserves the old syscall interface along with the
1613           new (ARM EABI) one. It also provides a compatibility layer to
1614           intercept syscalls that have structure arguments which layout
1615           in memory differs between the legacy ABI and the new ARM EABI
1616           (only for non "thumb" binaries). This option adds a tiny
1617           overhead to all syscalls and produces a slightly larger kernel.
1618
1619           The seccomp filter system will not be available when this is
1620           selected, since there is no way yet to sensibly distinguish
1621           between calling conventions during filtering.
1622
1623           If you know you'll be using only pure EABI user space then you
1624           can say N here. If this option is not selected and you attempt
1625           to execute a legacy ABI binary then the result will be
1626           UNPREDICTABLE (in fact it can be predicted that it won't work
1627           at all). If in doubt say N.
1628
1629 config ARCH_HAS_HOLES_MEMORYMODEL
1630         bool
1631
1632 config ARCH_SPARSEMEM_ENABLE
1633         bool
1634
1635 config ARCH_SPARSEMEM_DEFAULT
1636         def_bool ARCH_SPARSEMEM_ENABLE
1637
1638 config ARCH_SELECT_MEMORY_MODEL
1639         def_bool ARCH_SPARSEMEM_ENABLE
1640
1641 config HAVE_ARCH_PFN_VALID
1642         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1643
1644 config HAVE_GENERIC_RCU_GUP
1645         def_bool y
1646         depends on ARM_LPAE
1647
1648 config HIGHMEM
1649         bool "High Memory Support"
1650         depends on MMU
1651         help
1652           The address space of ARM processors is only 4 Gigabytes large
1653           and it has to accommodate user address space, kernel address
1654           space as well as some memory mapped IO. That means that, if you
1655           have a large amount of physical memory and/or IO, not all of the
1656           memory can be "permanently mapped" by the kernel. The physical
1657           memory that is not permanently mapped is called "high memory".
1658
1659           Depending on the selected kernel/user memory split, minimum
1660           vmalloc space and actual amount of RAM, you may not need this
1661           option which should result in a slightly faster kernel.
1662
1663           If unsure, say n.
1664
1665 config HIGHPTE
1666         bool "Allocate 2nd-level pagetables from highmem"
1667         depends on HIGHMEM
1668
1669 config HW_PERF_EVENTS
1670         bool "Enable hardware performance counter support for perf events"
1671         depends on PERF_EVENTS
1672         default y
1673         help
1674           Enable hardware performance counter support for perf events. If
1675           disabled, perf events will use software events only.
1676
1677 config SYS_SUPPORTS_HUGETLBFS
1678        def_bool y
1679        depends on ARM_LPAE
1680
1681 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1682        def_bool y
1683        depends on ARM_LPAE
1684
1685 config ARCH_WANT_GENERAL_HUGETLB
1686         def_bool y
1687
1688 source "mm/Kconfig"
1689
1690 config FORCE_MAX_ZONEORDER
1691         int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1692         range 11 64 if ARCH_SHMOBILE_LEGACY
1693         default "12" if SOC_AM33XX
1694         default "9" if SA1111 || ARCH_EFM32
1695         default "11"
1696         help
1697           The kernel memory allocator divides physically contiguous memory
1698           blocks into "zones", where each zone is a power of two number of
1699           pages.  This option selects the largest power of two that the kernel
1700           keeps in the memory allocator.  If you need to allocate very large
1701           blocks of physically contiguous memory, then you may need to
1702           increase this value.
1703
1704           This config option is actually maximum order plus one. For example,
1705           a value of 11 means that the largest free memory block is 2^10 pages.
1706
1707 config ALIGNMENT_TRAP
1708         bool
1709         depends on CPU_CP15_MMU
1710         default y if !ARCH_EBSA110
1711         select HAVE_PROC_CPU if PROC_FS
1712         help
1713           ARM processors cannot fetch/store information which is not
1714           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1715           address divisible by 4. On 32-bit ARM processors, these non-aligned
1716           fetch/store instructions will be emulated in software if you say
1717           here, which has a severe performance impact. This is necessary for
1718           correct operation of some network protocols. With an IP-only
1719           configuration it is safe to say N, otherwise say Y.
1720
1721 config UACCESS_WITH_MEMCPY
1722         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1723         depends on MMU
1724         default y if CPU_FEROCEON
1725         help
1726           Implement faster copy_to_user and clear_user methods for CPU
1727           cores where a 8-word STM instruction give significantly higher
1728           memory write throughput than a sequence of individual 32bit stores.
1729
1730           A possible side effect is a slight increase in scheduling latency
1731           between threads sharing the same address space if they invoke
1732           such copy operations with large buffers.
1733
1734           However, if the CPU data cache is using a write-allocate mode,
1735           this option is unlikely to provide any performance gain.
1736
1737 config SECCOMP
1738         bool
1739         prompt "Enable seccomp to safely compute untrusted bytecode"
1740         ---help---
1741           This kernel feature is useful for number crunching applications
1742           that may need to compute untrusted bytecode during their
1743           execution. By using pipes or other transports made available to
1744           the process as file descriptors supporting the read/write
1745           syscalls, it's possible to isolate those applications in
1746           their own address space using seccomp. Once seccomp is
1747           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1748           and the task is only allowed to execute a few safe syscalls
1749           defined by each seccomp mode.
1750
1751 config SWIOTLB
1752         def_bool y
1753
1754 config IOMMU_HELPER
1755         def_bool SWIOTLB
1756
1757 config XEN_DOM0
1758         def_bool y
1759         depends on XEN
1760
1761 config XEN
1762         bool "Xen guest support on ARM"
1763         depends on ARM && AEABI && OF
1764         depends on CPU_V7 && !CPU_V6
1765         depends on !GENERIC_ATOMIC64
1766         depends on MMU
1767         select ARCH_DMA_ADDR_T_64BIT
1768         select ARM_PSCI
1769         select SWIOTLB_XEN
1770         help
1771           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1772
1773 endmenu
1774
1775 menu "Boot options"
1776
1777 config USE_OF
1778         bool "Flattened Device Tree support"
1779         select IRQ_DOMAIN
1780         select OF
1781         select OF_EARLY_FLATTREE
1782         select OF_RESERVED_MEM
1783         help
1784           Include support for flattened device tree machine descriptions.
1785
1786 config ATAGS
1787         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1788         default y
1789         help
1790           This is the traditional way of passing data to the kernel at boot
1791           time. If you are solely relying on the flattened device tree (or
1792           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1793           to remove ATAGS support from your kernel binary.  If unsure,
1794           leave this to y.
1795
1796 config DEPRECATED_PARAM_STRUCT
1797         bool "Provide old way to pass kernel parameters"
1798         depends on ATAGS
1799         help
1800           This was deprecated in 2001 and announced to live on for 5 years.
1801           Some old boot loaders still use this way.
1802
1803 # Compressed boot loader in ROM.  Yes, we really want to ask about
1804 # TEXT and BSS so we preserve their values in the config files.
1805 config ZBOOT_ROM_TEXT
1806         hex "Compressed ROM boot loader base address"
1807         default "0"
1808         help
1809           The physical address at which the ROM-able zImage is to be
1810           placed in the target.  Platforms which normally make use of
1811           ROM-able zImage formats normally set this to a suitable
1812           value in their defconfig file.
1813
1814           If ZBOOT_ROM is not enabled, this has no effect.
1815
1816 config ZBOOT_ROM_BSS
1817         hex "Compressed ROM boot loader BSS address"
1818         default "0"
1819         help
1820           The base address of an area of read/write memory in the target
1821           for the ROM-able zImage which must be available while the
1822           decompressor is running. It must be large enough to hold the
1823           entire decompressed kernel plus an additional 128 KiB.
1824           Platforms which normally make use of ROM-able zImage formats
1825           normally set this to a suitable value in their defconfig file.
1826
1827           If ZBOOT_ROM is not enabled, this has no effect.
1828
1829 config ZBOOT_ROM
1830         bool "Compressed boot loader in ROM/flash"
1831         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1832         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1833         help
1834           Say Y here if you intend to execute your compressed kernel image
1835           (zImage) directly from ROM or flash.  If unsure, say N.
1836
1837 choice
1838         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1839         depends on ZBOOT_ROM && ARCH_SH7372
1840         default ZBOOT_ROM_NONE
1841         help
1842           Include experimental SD/MMC loading code in the ROM-able zImage.
1843           With this enabled it is possible to write the ROM-able zImage
1844           kernel image to an MMC or SD card and boot the kernel straight
1845           from the reset vector. At reset the processor Mask ROM will load
1846           the first part of the ROM-able zImage which in turn loads the
1847           rest the kernel image to RAM.
1848
1849 config ZBOOT_ROM_NONE
1850         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1851         help
1852           Do not load image from SD or MMC
1853
1854 config ZBOOT_ROM_MMCIF
1855         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1856         help
1857           Load image from MMCIF hardware block.
1858
1859 config ZBOOT_ROM_SH_MOBILE_SDHI
1860         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1861         help
1862           Load image from SDHI hardware block
1863
1864 endchoice
1865
1866 config ARM_APPENDED_DTB
1867         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1868         depends on OF
1869         help
1870           With this option, the boot code will look for a device tree binary
1871           (DTB) appended to zImage
1872           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1873
1874           This is meant as a backward compatibility convenience for those
1875           systems with a bootloader that can't be upgraded to accommodate
1876           the documented boot protocol using a device tree.
1877
1878           Beware that there is very little in terms of protection against
1879           this option being confused by leftover garbage in memory that might
1880           look like a DTB header after a reboot if no actual DTB is appended
1881           to zImage.  Do not leave this option active in a production kernel
1882           if you don't intend to always append a DTB.  Proper passing of the
1883           location into r2 of a bootloader provided DTB is always preferable
1884           to this option.
1885
1886 config ARM_ATAG_DTB_COMPAT
1887         bool "Supplement the appended DTB with traditional ATAG information"
1888         depends on ARM_APPENDED_DTB
1889         help
1890           Some old bootloaders can't be updated to a DTB capable one, yet
1891           they provide ATAGs with memory configuration, the ramdisk address,
1892           the kernel cmdline string, etc.  Such information is dynamically
1893           provided by the bootloader and can't always be stored in a static
1894           DTB.  To allow a device tree enabled kernel to be used with such
1895           bootloaders, this option allows zImage to extract the information
1896           from the ATAG list and store it at run time into the appended DTB.
1897
1898 choice
1899         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1900         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1901
1902 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1903         bool "Use bootloader kernel arguments if available"
1904         help
1905           Uses the command-line options passed by the boot loader instead of
1906           the device tree bootargs property. If the boot loader doesn't provide
1907           any, the device tree bootargs property will be used.
1908
1909 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1910         bool "Extend with bootloader kernel arguments"
1911         help
1912           The command-line arguments provided by the boot loader will be
1913           appended to the the device tree bootargs property.
1914
1915 endchoice
1916
1917 config CMDLINE
1918         string "Default kernel command string"
1919         default ""
1920         help
1921           On some architectures (EBSA110 and CATS), there is currently no way
1922           for the boot loader to pass arguments to the kernel. For these
1923           architectures, you should supply some command-line options at build
1924           time by entering them here. As a minimum, you should specify the
1925           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1926
1927 choice
1928         prompt "Kernel command line type" if CMDLINE != ""
1929         default CMDLINE_FROM_BOOTLOADER
1930         depends on ATAGS
1931
1932 config CMDLINE_FROM_BOOTLOADER
1933         bool "Use bootloader kernel arguments if available"
1934         help
1935           Uses the command-line options passed by the boot loader. If
1936           the boot loader doesn't provide any, the default kernel command
1937           string provided in CMDLINE will be used.
1938
1939 config CMDLINE_EXTEND
1940         bool "Extend bootloader kernel arguments"
1941         help
1942           The command-line arguments provided by the boot loader will be
1943           appended to the default kernel command string.
1944
1945 config CMDLINE_FORCE
1946         bool "Always use the default kernel command string"
1947         help
1948           Always use the default kernel command string, even if the boot
1949           loader passes other arguments to the kernel.
1950           This is useful if you cannot or don't want to change the
1951           command-line options your boot loader passes to the kernel.
1952 endchoice
1953
1954 config XIP_KERNEL
1955         bool "Kernel Execute-In-Place from ROM"
1956         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1957         help
1958           Execute-In-Place allows the kernel to run from non-volatile storage
1959           directly addressable by the CPU, such as NOR flash. This saves RAM
1960           space since the text section of the kernel is not loaded from flash
1961           to RAM.  Read-write sections, such as the data section and stack,
1962           are still copied to RAM.  The XIP kernel is not compressed since
1963           it has to run directly from flash, so it will take more space to
1964           store it.  The flash address used to link the kernel object files,
1965           and for storing it, is configuration dependent. Therefore, if you
1966           say Y here, you must know the proper physical address where to
1967           store the kernel image depending on your own flash memory usage.
1968
1969           Also note that the make target becomes "make xipImage" rather than
1970           "make zImage" or "make Image".  The final kernel binary to put in
1971           ROM memory will be arch/arm/boot/xipImage.
1972
1973           If unsure, say N.
1974
1975 config XIP_PHYS_ADDR
1976         hex "XIP Kernel Physical Location"
1977         depends on XIP_KERNEL
1978         default "0x00080000"
1979         help
1980           This is the physical address in your flash memory the kernel will
1981           be linked for and stored to.  This address is dependent on your
1982           own flash usage.
1983
1984 config KEXEC
1985         bool "Kexec system call (EXPERIMENTAL)"
1986         depends on (!SMP || PM_SLEEP_SMP)
1987         help
1988           kexec is a system call that implements the ability to shutdown your
1989           current kernel, and to start another kernel.  It is like a reboot
1990           but it is independent of the system firmware.   And like a reboot
1991           you can start any kernel with it, not just Linux.
1992
1993           It is an ongoing process to be certain the hardware in a machine
1994           is properly shutdown, so do not be surprised if this code does not
1995           initially work for you.
1996
1997 config ATAGS_PROC
1998         bool "Export atags in procfs"
1999         depends on ATAGS && KEXEC
2000         default y
2001         help
2002           Should the atags used to boot the kernel be exported in an "atags"
2003           file in procfs. Useful with kexec.
2004
2005 config CRASH_DUMP
2006         bool "Build kdump crash kernel (EXPERIMENTAL)"
2007         help
2008           Generate crash dump after being started by kexec. This should
2009           be normally only set in special crash dump kernels which are
2010           loaded in the main kernel with kexec-tools into a specially
2011           reserved region and then later executed after a crash by
2012           kdump/kexec. The crash dump kernel must be compiled to a
2013           memory address not used by the main kernel
2014
2015           For more details see Documentation/kdump/kdump.txt
2016
2017 config AUTO_ZRELADDR
2018         bool "Auto calculation of the decompressed kernel image address"
2019         help
2020           ZRELADDR is the physical address where the decompressed kernel
2021           image will be placed. If AUTO_ZRELADDR is selected, the address
2022           will be determined at run-time by masking the current IP with
2023           0xf8000000. This assumes the zImage being placed in the first 128MB
2024           from start of memory.
2025
2026 endmenu
2027
2028 menu "CPU Power Management"
2029
2030 source "drivers/cpufreq/Kconfig"
2031
2032 source "drivers/cpuidle/Kconfig"
2033
2034 endmenu
2035
2036 menu "Floating point emulation"
2037
2038 comment "At least one emulation must be selected"
2039
2040 config FPE_NWFPE
2041         bool "NWFPE math emulation"
2042         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2043         ---help---
2044           Say Y to include the NWFPE floating point emulator in the kernel.
2045           This is necessary to run most binaries. Linux does not currently
2046           support floating point hardware so you need to say Y here even if
2047           your machine has an FPA or floating point co-processor podule.
2048
2049           You may say N here if you are going to load the Acorn FPEmulator
2050           early in the bootup.
2051
2052 config FPE_NWFPE_XP
2053         bool "Support extended precision"
2054         depends on FPE_NWFPE
2055         help
2056           Say Y to include 80-bit support in the kernel floating-point
2057           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2058           Note that gcc does not generate 80-bit operations by default,
2059           so in most cases this option only enlarges the size of the
2060           floating point emulator without any good reason.
2061
2062           You almost surely want to say N here.
2063
2064 config FPE_FASTFPE
2065         bool "FastFPE math emulation (EXPERIMENTAL)"
2066         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2067         ---help---
2068           Say Y here to include the FAST floating point emulator in the kernel.
2069           This is an experimental much faster emulator which now also has full
2070           precision for the mantissa.  It does not support any exceptions.
2071           It is very simple, and approximately 3-6 times faster than NWFPE.
2072
2073           It should be sufficient for most programs.  It may be not suitable
2074           for scientific calculations, but you have to check this for yourself.
2075           If you do not feel you need a faster FP emulation you should better
2076           choose NWFPE.
2077
2078 config VFP
2079         bool "VFP-format floating point maths"
2080         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2081         help
2082           Say Y to include VFP support code in the kernel. This is needed
2083           if your hardware includes a VFP unit.
2084
2085           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2086           release notes and additional status information.
2087
2088           Say N if your target does not have VFP hardware.
2089
2090 config VFPv3
2091         bool
2092         depends on VFP
2093         default y if CPU_V7
2094
2095 config NEON
2096         bool "Advanced SIMD (NEON) Extension support"
2097         depends on VFPv3 && CPU_V7
2098         help
2099           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2100           Extension.
2101
2102 config KERNEL_MODE_NEON
2103         bool "Support for NEON in kernel mode"
2104         depends on NEON && AEABI
2105         help
2106           Say Y to include support for NEON in kernel mode.
2107
2108 endmenu
2109
2110 menu "Userspace binary formats"
2111
2112 source "fs/Kconfig.binfmt"
2113
2114 config ARTHUR
2115         tristate "RISC OS personality"
2116         depends on !AEABI
2117         help
2118           Say Y here to include the kernel code necessary if you want to run
2119           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2120           experimental; if this sounds frightening, say N and sleep in peace.
2121           You can also say M here to compile this support as a module (which
2122           will be called arthur).
2123
2124 endmenu
2125
2126 menu "Power management options"
2127
2128 source "kernel/power/Kconfig"
2129
2130 config ARCH_SUSPEND_POSSIBLE
2131         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2132                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2133         def_bool y
2134
2135 config ARM_CPU_SUSPEND
2136         def_bool PM_SLEEP
2137
2138 config ARCH_HIBERNATION_POSSIBLE
2139         bool
2140         depends on MMU
2141         default y if ARCH_SUSPEND_POSSIBLE
2142
2143 endmenu
2144
2145 source "net/Kconfig"
2146
2147 source "drivers/Kconfig"
2148
2149 source "fs/Kconfig"
2150
2151 source "arch/arm/Kconfig.debug"
2152
2153 source "security/Kconfig"
2154
2155 source "crypto/Kconfig"
2156
2157 source "lib/Kconfig"
2158
2159 source "arch/arm/kvm/Kconfig"