arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   5         select ARCH_HAS_DEVMEM_IS_ALLOWED
   6         select ARCH_HAS_ELF_RANDOMIZE
   7         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   8         select ARCH_HAVE_CUSTOM_GPIO_H
   9         select ARCH_HAS_GCOV_PROFILE_ALL
  10         select ARCH_MIGHT_HAVE_PC_PARPORT
  11         select ARCH_SUPPORTS_ATOMIC_RMW
  12         select ARCH_USE_BUILTIN_BSWAP
  13         select ARCH_USE_CMPXCHG_LOCKREF
  14         select ARCH_WANT_IPC_PARSE_VERSION
  15         select BUILDTIME_EXTABLE_SORT if MMU
  16         select CLONE_BACKWARDS
  17         select CPU_PM if (SUSPEND || CPU_IDLE)
  18         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  19         select EDAC_SUPPORT
  20         select EDAC_ATOMIC_SCRUB
  21         select GENERIC_ALLOCATOR
  22         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  23         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  24         select GENERIC_EARLY_IOREMAP
  25         select GENERIC_IDLE_POLL_SETUP
  26         select GENERIC_IRQ_PROBE
  27         select GENERIC_IRQ_SHOW
  28         select GENERIC_IRQ_SHOW_LEVEL
  29         select GENERIC_PCI_IOMAP
  30         select GENERIC_SCHED_CLOCK
  31         select GENERIC_SMP_IDLE_THREAD
  32         select GENERIC_STRNCPY_FROM_USER
  33         select GENERIC_STRNLEN_USER
  34         select HANDLE_DOMAIN_IRQ
  35         select HARDIRQS_SW_RESEND
  36         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  37         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  38         select HAVE_ARCH_HARDENED_USERCOPY
  39         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
  40         select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
  41         select HAVE_ARCH_MMAP_RND_BITS if MMU
  42         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  43         select HAVE_ARCH_TRACEHOOK
  44         select HAVE_ARM_SMCCC if CPU_V7
  45         select HAVE_CBPF_JIT
  46         select HAVE_CC_STACKPROTECTOR
  47         select HAVE_CONTEXT_TRACKING
  48         select HAVE_C_RECORDMCOUNT
  49         select HAVE_DEBUG_KMEMLEAK
  50         select HAVE_DMA_API_DEBUG
  51         select HAVE_DMA_CONTIGUOUS if MMU
  52         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
  53         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  54         select HAVE_EXIT_THREAD
  55         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  56         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  57         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  58         select HAVE_GCC_PLUGINS
  59         select HAVE_GENERIC_DMA_COHERENT
  60         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  61         select HAVE_IDE if PCI || ISA || PCMCIA
  62         select HAVE_IRQ_TIME_ACCOUNTING
  63         select HAVE_KERNEL_GZIP
  64         select HAVE_KERNEL_LZ4
  65         select HAVE_KERNEL_LZMA
  66         select HAVE_KERNEL_LZO
  67         select HAVE_KERNEL_XZ
  68         select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
  69         select HAVE_KRETPROBES if (HAVE_KPROBES)
  70         select HAVE_MEMBLOCK
  71         select HAVE_MOD_ARCH_SPECIFIC
  72         select HAVE_NMI
  73         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  74         select HAVE_OPTPROBES if !THUMB2_KERNEL
  75         select HAVE_PERF_EVENTS
  76         select HAVE_PERF_REGS
  77         select HAVE_PERF_USER_STACK_DUMP
  78         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  79         select HAVE_REGS_AND_STACK_ACCESS_API
  80         select HAVE_SYSCALL_TRACEPOINTS
  81         select HAVE_UID16
  82         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  83         select IRQ_FORCED_THREADING
  84         select MODULES_USE_ELF_REL
  85         select NO_BOOTMEM
  86         select OF_EARLY_FLATTREE if OF
  87         select OF_RESERVED_MEM if OF
  88         select OLD_SIGACTION
  89         select OLD_SIGSUSPEND3
  90         select PERF_USE_VMALLOC
  91         select RTC_LIB
  92         select SYS_SUPPORTS_APM_EMULATION
  93         # Above selects are sorted alphabetically; please add new ones
  94         # according to that.  Thanks.
  95         help
  96           The ARM series is a line of low-power-consumption RISC chip designs
  97           licensed by ARM Ltd and targeted at embedded applications and
  98           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  99           manufactured, but legacy ARM-based PC hardware remains popular in
 100           Europe.  There is an ARM Linux project with a web page at
 101           <http://www.arm.linux.org.uk/>.
 102
 103 config ARM_HAS_SG_CHAIN
 104         select ARCH_HAS_SG_CHAIN
 105         bool
 106
 107 config NEED_SG_DMA_LENGTH
 108         bool
 109
 110 config ARM_DMA_USE_IOMMU
 111         bool
 112         select ARM_HAS_SG_CHAIN
 113         select NEED_SG_DMA_LENGTH
 114
 115 if ARM_DMA_USE_IOMMU
 116
 117 config ARM_DMA_IOMMU_ALIGNMENT
 118         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 119         range 4 9
 120         default 8
 121         help
 122           DMA mapping framework by default aligns all buffers to the smallest
 123           PAGE_SIZE order which is greater than or equal to the requested buffer
 124           size. This works well for buffers up to a few hundreds kilobytes, but
 125           for larger buffers it just a waste of address space. Drivers which has
 126           relatively small addressing window (like 64Mib) might run out of
 127           virtual space with just a few allocations.
 128
 129           With this parameter you can specify the maximum PAGE_SIZE order for
 130           DMA IOMMU buffers. Larger buffers will be aligned only to this
 131           specified order. The order is expressed as a power of two multiplied
 132           by the PAGE_SIZE.
 133
 134 endif
 135
 136 config MIGHT_HAVE_PCI
 137         bool
 138
 139 config SYS_SUPPORTS_APM_EMULATION
 140         bool
 141
 142 config HAVE_TCM
 143         bool
 144         select GENERIC_ALLOCATOR
 145
 146 config HAVE_PROC_CPU
 147         bool
 148
 149 config NO_IOPORT_MAP
 150         bool
 151
 152 config EISA
 153         bool
 154         ---help---
 155           The Extended Industry Standard Architecture (EISA) bus was
 156           developed as an open alternative to the IBM MicroChannel bus.
 157
 158           The EISA bus provided some of the features of the IBM MicroChannel
 159           bus while maintaining backward compatibility with cards made for
 160           the older ISA bus.  The EISA bus saw limited use between 1988 and
 161           1995 when it was made obsolete by the PCI bus.
 162
 163           Say Y here if you are building a kernel for an EISA-based machine.
 164
 165           Otherwise, say N.
 166
 167 config SBUS
 168         bool
 169
 170 config STACKTRACE_SUPPORT
 171         bool
 172         default y
 173
 174 config LOCKDEP_SUPPORT
 175         bool
 176         default y
 177
 178 config TRACE_IRQFLAGS_SUPPORT
 179         bool
 180         default !CPU_V7M
 181
 182 config RWSEM_XCHGADD_ALGORITHM
 183         bool
 184         default y
 185
 186 config ARCH_HAS_ILOG2_U32
 187         bool
 188
 189 config ARCH_HAS_ILOG2_U64
 190         bool
 191
 192 config ARCH_HAS_BANDGAP
 193         bool
 194
 195 config FIX_EARLYCON_MEM
 196         def_bool y if MMU
 197
 198 config GENERIC_HWEIGHT
 199         bool
 200         default y
 201
 202 config GENERIC_CALIBRATE_DELAY
 203         bool
 204         default y
 205
 206 config ARCH_MAY_HAVE_PC_FDC
 207         bool
 208
 209 config ZONE_DMA
 210         bool
 211
 212 config NEED_DMA_MAP_STATE
 213        def_bool y
 214
 215 config ARCH_SUPPORTS_UPROBES
 216         def_bool y
 217
 218 config ARCH_HAS_DMA_SET_COHERENT_MASK
 219         bool
 220
 221 config GENERIC_ISA_DMA
 222         bool
 223
 224 config FIQ
 225         bool
 226
 227 config NEED_RET_TO_USER
 228         bool
 229
 230 config ARCH_MTD_XIP
 231         bool
 232
 233 config VECTORS_BASE
 234         hex
 235         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 236         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 237         default 0x00000000
 238         help
 239           The base address of exception vectors.  This must be two pages
 240           in size.
 241
 242 config ARM_PATCH_PHYS_VIRT
 243         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 244         default y
 245         depends on !XIP_KERNEL && MMU
 246         help
 247           Patch phys-to-virt and virt-to-phys translation functions at
 248           boot and module load time according to the position of the
 249           kernel in system memory.
 250
 251           This can only be used with non-XIP MMU kernels where the base
 252           of physical memory is at a 16MB boundary.
 253
 254           Only disable this option if you know that you do not require
 255           this feature (eg, building a kernel for a single machine) and
 256           you need to shrink the kernel to the minimal size.
 257
 258 config NEED_MACH_IO_H
 259         bool
 260         help
 261           Select this when mach/io.h is required to provide special
 262           definitions for this platform.  The need for mach/io.h should
 263           be avoided when possible.
 264
 265 config NEED_MACH_MEMORY_H
 266         bool
 267         help
 268           Select this when mach/memory.h is required to provide special
 269           definitions for this platform.  The need for mach/memory.h should
 270           be avoided when possible.
 271
 272 config PHYS_OFFSET
 273         hex "Physical address of main memory" if MMU
 274         depends on !ARM_PATCH_PHYS_VIRT
 275         default DRAM_BASE if !MMU
 276         default 0x00000000 if ARCH_EBSA110 || \
 277                         ARCH_FOOTBRIDGE || \
 278                         ARCH_INTEGRATOR || \
 279                         ARCH_IOP13XX || \
 280                         ARCH_KS8695 || \
 281                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 282         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 283         default 0x20000000 if ARCH_S5PV210
 284         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 285         default 0xc0000000 if ARCH_SA1100
 286         help
 287           Please provide the physical address corresponding to the
 288           location of main memory in your system.
 289
 290 config GENERIC_BUG
 291         def_bool y
 292         depends on BUG
 293
 294 config PGTABLE_LEVELS
 295         int
 296         default 3 if ARM_LPAE
 297         default 2
 298
 299 source "init/Kconfig"
 300
 301 source "kernel/Kconfig.freezer"
 302
 303 menu "System Type"
 304
 305 config MMU
 306         bool "MMU-based Paged Memory Management Support"
 307         default y
 308         help
 309           Select if you want MMU-based virtualised addressing space
 310           support by paged memory management. If unsure, say 'Y'.
 311
 312 config ARCH_MMAP_RND_BITS_MIN
 313         default 8
 314
 315 config ARCH_MMAP_RND_BITS_MAX
 316         default 14 if PAGE_OFFSET=0x40000000
 317         default 15 if PAGE_OFFSET=0x80000000
 318         default 16
 319
 320 #
 321 # The "ARM system type" choice list is ordered alphabetically by option
 322 # text.  Please add new entries in the option alphabetic order.
 323 #
 324 choice
 325         prompt "ARM system type"
 326         default ARM_SINGLE_ARMV7M if !MMU
 327         default ARCH_MULTIPLATFORM if MMU
 328
 329 config ARCH_MULTIPLATFORM
 330         bool "Allow multiple platforms to be selected"
 331         depends on MMU
 332         select ARM_HAS_SG_CHAIN
 333         select ARM_PATCH_PHYS_VIRT
 334         select AUTO_ZRELADDR
 335         select CLKSRC_OF
 336         select COMMON_CLK
 337         select GENERIC_CLOCKEVENTS
 338         select MIGHT_HAVE_PCI
 339         select MULTI_IRQ_HANDLER
 340         select SPARSE_IRQ
 341         select USE_OF
 342
 343 config ARM_SINGLE_ARMV7M
 344         bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
 345         depends on !MMU
 346         select ARM_NVIC
 347         select AUTO_ZRELADDR
 348         select CLKSRC_OF
 349         select COMMON_CLK
 350         select CPU_V7M
 351         select GENERIC_CLOCKEVENTS
 352         select NO_IOPORT_MAP
 353         select SPARSE_IRQ
 354         select USE_OF
 355
 356 config ARCH_GEMINI
 357         bool "Cortina Systems Gemini"
 358         select CLKSRC_MMIO
 359         select CPU_FA526
 360         select GENERIC_CLOCKEVENTS
 361         select GPIOLIB
 362         help
 363           Support for the Cortina Systems Gemini family SoCs
 364
 365 config ARCH_EBSA110
 366         bool "EBSA-110"
 367         select ARCH_USES_GETTIMEOFFSET
 368         select CPU_SA110
 369         select ISA
 370         select NEED_MACH_IO_H
 371         select NEED_MACH_MEMORY_H
 372         select NO_IOPORT_MAP
 373         help
 374           This is an evaluation board for the StrongARM processor available
 375           from Digital. It has limited hardware on-board, including an
 376           Ethernet interface, two PCMCIA sockets, two serial ports and a
 377           parallel port.
 378
 379 config ARCH_EP93XX
 380         bool "EP93xx-based"
 381         select ARCH_HAS_HOLES_MEMORYMODEL
 382         select ARM_AMBA
 383         select ARM_PATCH_PHYS_VIRT
 384         select ARM_VIC
 385         select AUTO_ZRELADDR
 386         select CLKDEV_LOOKUP
 387         select CLKSRC_MMIO
 388         select CPU_ARM920T
 389         select GENERIC_CLOCKEVENTS
 390         select GPIOLIB
 391         help
 392           This enables support for the Cirrus EP93xx series of CPUs.
 393
 394 config ARCH_FOOTBRIDGE
 395         bool "FootBridge"
 396         select CPU_SA110
 397         select FOOTBRIDGE
 398         select GENERIC_CLOCKEVENTS
 399         select HAVE_IDE
 400         select NEED_MACH_IO_H if !MMU
 401         select NEED_MACH_MEMORY_H
 402         help
 403           Support for systems based on the DC21285 companion chip
 404           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 405
 406 config ARCH_NETX
 407         bool "Hilscher NetX based"
 408         select ARM_VIC
 409         select CLKSRC_MMIO
 410         select CPU_ARM926T
 411         select GENERIC_CLOCKEVENTS
 412         help
 413           This enables support for systems based on the Hilscher NetX Soc
 414
 415 config ARCH_IOP13XX
 416         bool "IOP13xx-based"
 417         depends on MMU
 418         select CPU_XSC3
 419         select NEED_MACH_MEMORY_H
 420         select NEED_RET_TO_USER
 421         select PCI
 422         select PLAT_IOP
 423         select VMSPLIT_1G
 424         select SPARSE_IRQ
 425         help
 426           Support for Intel's IOP13XX (XScale) family of processors.
 427
 428 config ARCH_IOP32X
 429         bool "IOP32x-based"
 430         depends on MMU
 431         select CPU_XSCALE
 432         select GPIO_IOP
 433         select GPIOLIB
 434         select NEED_RET_TO_USER
 435         select PCI
 436         select PLAT_IOP
 437         help
 438           Support for Intel's 80219 and IOP32X (XScale) family of
 439           processors.
 440
 441 config ARCH_IOP33X
 442         bool "IOP33x-based"
 443         depends on MMU
 444         select CPU_XSCALE
 445         select GPIO_IOP
 446         select GPIOLIB
 447         select NEED_RET_TO_USER
 448         select PCI
 449         select PLAT_IOP
 450         help
 451           Support for Intel's IOP33X (XScale) family of processors.
 452
 453 config ARCH_IXP4XX
 454         bool "IXP4xx-based"
 455         depends on MMU
 456         select ARCH_HAS_DMA_SET_COHERENT_MASK
 457         select ARCH_SUPPORTS_BIG_ENDIAN
 458         select CLKSRC_MMIO
 459         select CPU_XSCALE
 460         select DMABOUNCE if PCI
 461         select GENERIC_CLOCKEVENTS
 462         select GPIOLIB
 463         select MIGHT_HAVE_PCI
 464         select NEED_MACH_IO_H
 465         select USB_EHCI_BIG_ENDIAN_DESC
 466         select USB_EHCI_BIG_ENDIAN_MMIO
 467         help
 468           Support for Intel's IXP4XX (XScale) family of processors.
 469
 470 config ARCH_DOVE
 471         bool "Marvell Dove"
 472         select CPU_PJ4
 473         select GENERIC_CLOCKEVENTS
 474         select GPIOLIB
 475         select MIGHT_HAVE_PCI
 476         select MULTI_IRQ_HANDLER
 477         select MVEBU_MBUS
 478         select PINCTRL
 479         select PINCTRL_DOVE
 480         select PLAT_ORION_LEGACY
 481         select SPARSE_IRQ
 482         select PM_GENERIC_DOMAINS if PM
 483         help
 484           Support for the Marvell Dove SoC 88AP510
 485
 486 config ARCH_KS8695
 487         bool "Micrel/Kendin KS8695"
 488         select CLKSRC_MMIO
 489         select CPU_ARM922T
 490         select GENERIC_CLOCKEVENTS
 491         select GPIOLIB
 492         select NEED_MACH_MEMORY_H
 493         help
 494           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 495           System-on-Chip devices.
 496
 497 config ARCH_W90X900
 498         bool "Nuvoton W90X900 CPU"
 499         select CLKDEV_LOOKUP
 500         select CLKSRC_MMIO
 501         select CPU_ARM926T
 502         select GENERIC_CLOCKEVENTS
 503         select GPIOLIB
 504         help
 505           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 506           At present, the w90x900 has been renamed nuc900, regarding
 507           the ARM series product line, you can login the following
 508           link address to know more.
 509
 510           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 511                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 512
 513 config ARCH_LPC32XX
 514         bool "NXP LPC32XX"
 515         select ARM_AMBA
 516         select CLKDEV_LOOKUP
 517         select CLKSRC_LPC32XX
 518         select COMMON_CLK
 519         select CPU_ARM926T
 520         select GENERIC_CLOCKEVENTS
 521         select GPIOLIB
 522         select MULTI_IRQ_HANDLER
 523         select SPARSE_IRQ
 524         select USE_OF
 525         help
 526           Support for the NXP LPC32XX family of processors
 527
 528 config ARCH_PXA
 529         bool "PXA2xx/PXA3xx-based"
 530         depends on MMU
 531         select ARCH_MTD_XIP
 532         select ARM_CPU_SUSPEND if PM
 533         select AUTO_ZRELADDR
 534         select COMMON_CLK
 535         select CLKDEV_LOOKUP
 536         select CLKSRC_PXA
 537         select CLKSRC_MMIO
 538         select CLKSRC_OF
 539         select CPU_XSCALE if !CPU_XSC3
 540         select GENERIC_CLOCKEVENTS
 541         select GPIO_PXA
 542         select GPIOLIB
 543         select HAVE_IDE
 544         select IRQ_DOMAIN
 545         select MULTI_IRQ_HANDLER
 546         select PLAT_PXA
 547         select SPARSE_IRQ
 548         help
 549           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 550
 551 config ARCH_RPC
 552         bool "RiscPC"
 553         depends on MMU
 554         select ARCH_ACORN
 555         select ARCH_MAY_HAVE_PC_FDC
 556         select ARCH_SPARSEMEM_ENABLE
 557         select ARCH_USES_GETTIMEOFFSET
 558         select CPU_SA110
 559         select FIQ
 560         select HAVE_IDE
 561         select HAVE_PATA_PLATFORM
 562         select ISA_DMA_API
 563         select NEED_MACH_IO_H
 564         select NEED_MACH_MEMORY_H
 565         select NO_IOPORT_MAP
 566         help
 567           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 568           CD-ROM interface, serial and parallel port, and the floppy drive.
 569
 570 config ARCH_SA1100
 571         bool "SA1100-based"
 572         select ARCH_MTD_XIP
 573         select ARCH_SPARSEMEM_ENABLE
 574         select CLKDEV_LOOKUP
 575         select CLKSRC_MMIO
 576         select CLKSRC_PXA
 577         select CLKSRC_OF if OF
 578         select CPU_FREQ
 579         select CPU_SA1100
 580         select GENERIC_CLOCKEVENTS
 581         select GPIOLIB
 582         select HAVE_IDE
 583         select IRQ_DOMAIN
 584         select ISA
 585         select MULTI_IRQ_HANDLER
 586         select NEED_MACH_MEMORY_H
 587         select SPARSE_IRQ
 588         help
 589           Support for StrongARM 11x0 based boards.
 590
 591 config ARCH_S3C24XX
 592         bool "Samsung S3C24XX SoCs"
 593         select ATAGS
 594         select CLKDEV_LOOKUP
 595         select CLKSRC_SAMSUNG_PWM
 596         select GENERIC_CLOCKEVENTS
 597         select GPIO_SAMSUNG
 598         select GPIOLIB
 599         select HAVE_S3C2410_I2C if I2C
 600         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 601         select HAVE_S3C_RTC if RTC_CLASS
 602         select MULTI_IRQ_HANDLER
 603         select NEED_MACH_IO_H
 604         select SAMSUNG_ATAGS
 605         help
 606           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 607           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 608           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 609           Samsung SMDK2410 development board (and derivatives).
 610
 611 config ARCH_DAVINCI
 612         bool "TI DaVinci"
 613         select ARCH_HAS_HOLES_MEMORYMODEL
 614         select CLKDEV_LOOKUP
 615         select CPU_ARM926T
 616         select GENERIC_ALLOCATOR
 617         select GENERIC_CLOCKEVENTS
 618         select GENERIC_IRQ_CHIP
 619         select GPIOLIB
 620         select HAVE_IDE
 621         select USE_OF
 622         select ZONE_DMA
 623         help
 624           Support for TI's DaVinci platform.
 625
 626 config ARCH_OMAP1
 627         bool "TI OMAP1"
 628         depends on MMU
 629         select ARCH_HAS_HOLES_MEMORYMODEL
 630         select ARCH_OMAP
 631         select CLKDEV_LOOKUP
 632         select CLKSRC_MMIO
 633         select GENERIC_CLOCKEVENTS
 634         select GENERIC_IRQ_CHIP
 635         select GPIOLIB
 636         select HAVE_IDE
 637         select IRQ_DOMAIN
 638         select MULTI_IRQ_HANDLER
 639         select NEED_MACH_IO_H if PCCARD
 640         select NEED_MACH_MEMORY_H
 641         select SPARSE_IRQ
 642         help
 643           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 644
 645 endchoice
 646
 647 menu "Multiple platform selection"
 648         depends on ARCH_MULTIPLATFORM
 649
 650 comment "CPU Core family selection"
 651
 652 config ARCH_MULTI_V4
 653         bool "ARMv4 based platforms (FA526)"
 654         depends on !ARCH_MULTI_V6_V7
 655         select ARCH_MULTI_V4_V5
 656         select CPU_FA526
 657
 658 config ARCH_MULTI_V4T
 659         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 660         depends on !ARCH_MULTI_V6_V7
 661         select ARCH_MULTI_V4_V5
 662         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 663                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 664                 CPU_ARM925T || CPU_ARM940T)
 665
 666 config ARCH_MULTI_V5
 667         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 668         depends on !ARCH_MULTI_V6_V7
 669         select ARCH_MULTI_V4_V5
 670         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 671                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 672                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 673
 674 config ARCH_MULTI_V4_V5
 675         bool
 676
 677 config ARCH_MULTI_V6
 678         bool "ARMv6 based platforms (ARM11)"
 679         select ARCH_MULTI_V6_V7
 680         select CPU_V6K
 681
 682 config ARCH_MULTI_V7
 683         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 684         default y
 685         select ARCH_MULTI_V6_V7
 686         select CPU_V7
 687         select HAVE_SMP
 688
 689 config ARCH_MULTI_V6_V7
 690         bool
 691         select MIGHT_HAVE_CACHE_L2X0
 692
 693 config ARCH_MULTI_CPU_AUTO
 694         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 695         select ARCH_MULTI_V5
 696
 697 endmenu
 698
 699 config ARCH_VIRT
 700         bool "Dummy Virtual Machine"
 701         depends on ARCH_MULTI_V7
 702         select ARM_AMBA
 703         select ARM_GIC
 704         select ARM_GIC_V2M if PCI
 705         select ARM_GIC_V3
 706         select ARM_PSCI
 707         select HAVE_ARM_ARCH_TIMER
 708
 709 #
 710 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 711 # Kconfigs may be included either alphabetically (according to the
 712 # plat- suffix) or along side the corresponding mach-* source.
 713 #
 714 source "arch/arm/mach-mvebu/Kconfig"
 715
 716 source "arch/arm/mach-alpine/Kconfig"
 717
 718 source "arch/arm/mach-artpec/Kconfig"
 719
 720 source "arch/arm/mach-asm9260/Kconfig"
 721
 722 source "arch/arm/mach-at91/Kconfig"
 723
 724 source "arch/arm/mach-axxia/Kconfig"
 725
 726 source "arch/arm/mach-bcm/Kconfig"
 727
 728 source "arch/arm/mach-berlin/Kconfig"
 729
 730 source "arch/arm/mach-clps711x/Kconfig"
 731
 732 source "arch/arm/mach-cns3xxx/Kconfig"
 733
 734 source "arch/arm/mach-davinci/Kconfig"
 735
 736 source "arch/arm/mach-digicolor/Kconfig"
 737
 738 source "arch/arm/mach-dove/Kconfig"
 739
 740 source "arch/arm/mach-ep93xx/Kconfig"
 741
 742 source "arch/arm/mach-footbridge/Kconfig"
 743
 744 source "arch/arm/mach-gemini/Kconfig"
 745
 746 source "arch/arm/mach-highbank/Kconfig"
 747
 748 source "arch/arm/mach-hisi/Kconfig"
 749
 750 source "arch/arm/mach-integrator/Kconfig"
 751
 752 source "arch/arm/mach-iop32x/Kconfig"
 753
 754 source "arch/arm/mach-iop33x/Kconfig"
 755
 756 source "arch/arm/mach-iop13xx/Kconfig"
 757
 758 source "arch/arm/mach-ixp4xx/Kconfig"
 759
 760 source "arch/arm/mach-keystone/Kconfig"
 761
 762 source "arch/arm/mach-ks8695/Kconfig"
 763
 764 source "arch/arm/mach-meson/Kconfig"
 765
 766 source "arch/arm/mach-moxart/Kconfig"
 767
 768 source "arch/arm/mach-aspeed/Kconfig"
 769
 770 source "arch/arm/mach-mv78xx0/Kconfig"
 771
 772 source "arch/arm/mach-imx/Kconfig"
 773
 774 source "arch/arm/mach-mediatek/Kconfig"
 775
 776 source "arch/arm/mach-mxs/Kconfig"
 777
 778 source "arch/arm/mach-netx/Kconfig"
 779
 780 source "arch/arm/mach-nomadik/Kconfig"
 781
 782 source "arch/arm/mach-nspire/Kconfig"
 783
 784 source "arch/arm/plat-omap/Kconfig"
 785
 786 source "arch/arm/mach-omap1/Kconfig"
 787
 788 source "arch/arm/mach-omap2/Kconfig"
 789
 790 source "arch/arm/mach-orion5x/Kconfig"
 791
 792 source "arch/arm/mach-picoxcell/Kconfig"
 793
 794 source "arch/arm/mach-pxa/Kconfig"
 795 source "arch/arm/plat-pxa/Kconfig"
 796
 797 source "arch/arm/mach-mmp/Kconfig"
 798
 799 source "arch/arm/mach-oxnas/Kconfig"
 800
 801 source "arch/arm/mach-qcom/Kconfig"
 802
 803 source "arch/arm/mach-realview/Kconfig"
 804
 805 source "arch/arm/mach-rockchip/Kconfig"
 806
 807 source "arch/arm/mach-sa1100/Kconfig"
 808
 809 source "arch/arm/mach-socfpga/Kconfig"
 810
 811 source "arch/arm/mach-spear/Kconfig"
 812
 813 source "arch/arm/mach-sti/Kconfig"
 814
 815 source "arch/arm/mach-s3c24xx/Kconfig"
 816
 817 source "arch/arm/mach-s3c64xx/Kconfig"
 818
 819 source "arch/arm/mach-s5pv210/Kconfig"
 820
 821 source "arch/arm/mach-exynos/Kconfig"
 822 source "arch/arm/plat-samsung/Kconfig"
 823
 824 source "arch/arm/mach-shmobile/Kconfig"
 825
 826 source "arch/arm/mach-sunxi/Kconfig"
 827
 828 source "arch/arm/mach-prima2/Kconfig"
 829
 830 source "arch/arm/mach-tango/Kconfig"
 831
 832 source "arch/arm/mach-tegra/Kconfig"
 833
 834 source "arch/arm/mach-u300/Kconfig"
 835
 836 source "arch/arm/mach-uniphier/Kconfig"
 837
 838 source "arch/arm/mach-ux500/Kconfig"
 839
 840 source "arch/arm/mach-versatile/Kconfig"
 841
 842 source "arch/arm/mach-vexpress/Kconfig"
 843 source "arch/arm/plat-versatile/Kconfig"
 844
 845 source "arch/arm/mach-vt8500/Kconfig"
 846
 847 source "arch/arm/mach-w90x900/Kconfig"
 848
 849 source "arch/arm/mach-zx/Kconfig"
 850
 851 source "arch/arm/mach-zynq/Kconfig"
 852
 853 # ARMv7-M architecture
 854 config ARCH_EFM32
 855         bool "Energy Micro efm32"
 856         depends on ARM_SINGLE_ARMV7M
 857         select GPIOLIB
 858         help
 859           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 860           processors.
 861
 862 config ARCH_LPC18XX
 863         bool "NXP LPC18xx/LPC43xx"
 864         depends on ARM_SINGLE_ARMV7M
 865         select ARCH_HAS_RESET_CONTROLLER
 866         select ARM_AMBA
 867         select CLKSRC_LPC32XX
 868         select PINCTRL
 869         help
 870           Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
 871           high performance microcontrollers.
 872
 873 config ARCH_STM32
 874         bool "STMicrolectronics STM32"
 875         depends on ARM_SINGLE_ARMV7M
 876         select ARCH_HAS_RESET_CONTROLLER
 877         select ARMV7M_SYSTICK
 878         select CLKSRC_STM32
 879         select PINCTRL
 880         select RESET_CONTROLLER
 881         help
 882           Support for STMicroelectronics STM32 processors.
 883
 884 config MACH_STM32F429
 885         bool "STMicrolectronics STM32F429"
 886         depends on ARCH_STM32
 887         default y
 888
 889 config ARCH_MPS2
 890         bool "ARM MPS2 platform"
 891         depends on ARM_SINGLE_ARMV7M
 892         select ARM_AMBA
 893         select CLKSRC_MPS2
 894         help
 895           Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
 896           with a range of available cores like Cortex-M3/M4/M7.
 897
 898           Please, note that depends which Application Note is used memory map
 899           for the platform may vary, so adjustment of RAM base might be needed.
 900
 901 # Definitions to make life easier
 902 config ARCH_ACORN
 903         bool
 904
 905 config PLAT_IOP
 906         bool
 907         select GENERIC_CLOCKEVENTS
 908
 909 config PLAT_ORION
 910         bool
 911         select CLKSRC_MMIO
 912         select COMMON_CLK
 913         select GENERIC_IRQ_CHIP
 914         select IRQ_DOMAIN
 915
 916 config PLAT_ORION_LEGACY
 917         bool
 918         select PLAT_ORION
 919
 920 config PLAT_PXA
 921         bool
 922
 923 config PLAT_VERSATILE
 924         bool
 925
 926 source "arch/arm/firmware/Kconfig"
 927
 928 source arch/arm/mm/Kconfig
 929
 930 config IWMMXT
 931         bool "Enable iWMMXt support"
 932         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
 933         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
 934         help
 935           Enable support for iWMMXt context switching at run time if
 936           running on a CPU that supports it.
 937
 938 config MULTI_IRQ_HANDLER
 939         bool
 940         help
 941           Allow each machine to specify it's own IRQ handler at run time.
 942
 943 if !MMU
 944 source "arch/arm/Kconfig-nommu"
 945 endif
 946
 947 config PJ4B_ERRATA_4742
 948         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
 949         depends on CPU_PJ4B && MACH_ARMADA_370
 950         default y
 951         help
 952           When coming out of either a Wait for Interrupt (WFI) or a Wait for
 953           Event (WFE) IDLE states, a specific timing sensitivity exists between
 954           the retiring WFI/WFE instructions and the newly issued subsequent
 955           instructions.  This sensitivity can result in a CPU hang scenario.
 956           Workaround:
 957           The software must insert either a Data Synchronization Barrier (DSB)
 958           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
 959           instruction
 960
 961 config ARM_ERRATA_326103
 962         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
 963         depends on CPU_V6
 964         help
 965           Executing a SWP instruction to read-only memory does not set bit 11
 966           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
 967           treat the access as a read, preventing a COW from occurring and
 968           causing the faulting task to livelock.
 969
 970 config ARM_ERRATA_411920
 971         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
 972         depends on CPU_V6 || CPU_V6K
 973         help
 974           Invalidation of the Instruction Cache operation can
 975           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
 976           It does not affect the MPCore. This option enables the ARM Ltd.
 977           recommended workaround.
 978
 979 config ARM_ERRATA_430973
 980         bool "ARM errata: Stale prediction on replaced interworking branch"
 981         depends on CPU_V7
 982         help
 983           This option enables the workaround for the 430973 Cortex-A8
 984           r1p* erratum. If a code sequence containing an ARM/Thumb
 985           interworking branch is replaced with another code sequence at the
 986           same virtual address, whether due to self-modifying code or virtual
 987           to physical address re-mapping, Cortex-A8 does not recover from the
 988           stale interworking branch prediction. This results in Cortex-A8
 989           executing the new code sequence in the incorrect ARM or Thumb state.
 990           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
 991           and also flushes the branch target cache at every context switch.
 992           Note that setting specific bits in the ACTLR register may not be
 993           available in non-secure mode.
 994
 995 config ARM_ERRATA_458693
 996         bool "ARM errata: Processor deadlock when a false hazard is created"
 997         depends on CPU_V7
 998         depends on !ARCH_MULTIPLATFORM
 999         help
1000           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1001           erratum. For very specific sequences of memory operations, it is
1002           possible for a hazard condition intended for a cache line to instead
1003           be incorrectly associated with a different cache line. This false
1004           hazard might then cause a processor deadlock. The workaround enables
1005           the L1 caching of the NEON accesses and disables the PLD instruction
1006           in the ACTLR register. Note that setting specific bits in the ACTLR
1007           register may not be available in non-secure mode.
1008
1009 config ARM_ERRATA_460075
1010         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1011         depends on CPU_V7
1012         depends on !ARCH_MULTIPLATFORM
1013         help
1014           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1015           erratum. Any asynchronous access to the L2 cache may encounter a
1016           situation in which recent store transactions to the L2 cache are lost
1017           and overwritten with stale memory contents from external memory. The
1018           workaround disables the write-allocate mode for the L2 cache via the
1019           ACTLR register. Note that setting specific bits in the ACTLR register
1020           may not be available in non-secure mode.
1021
1022 config ARM_ERRATA_742230
1023         bool "ARM errata: DMB operation may be faulty"
1024         depends on CPU_V7 && SMP
1025         depends on !ARCH_MULTIPLATFORM
1026         help
1027           This option enables the workaround for the 742230 Cortex-A9
1028           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1029           between two write operations may not ensure the correct visibility
1030           ordering of the two writes. This workaround sets a specific bit in
1031           the diagnostic register of the Cortex-A9 which causes the DMB
1032           instruction to behave as a DSB, ensuring the correct behaviour of
1033           the two writes.
1034
1035 config ARM_ERRATA_742231
1036         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1037         depends on CPU_V7 && SMP
1038         depends on !ARCH_MULTIPLATFORM
1039         help
1040           This option enables the workaround for the 742231 Cortex-A9
1041           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1042           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1043           accessing some data located in the same cache line, may get corrupted
1044           data due to bad handling of the address hazard when the line gets
1045           replaced from one of the CPUs at the same time as another CPU is
1046           accessing it. This workaround sets specific bits in the diagnostic
1047           register of the Cortex-A9 which reduces the linefill issuing
1048           capabilities of the processor.
1049
1050 config ARM_ERRATA_643719
1051         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1052         depends on CPU_V7 && SMP
1053         default y
1054         help
1055           This option enables the workaround for the 643719 Cortex-A9 (prior to
1056           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1057           register returns zero when it should return one. The workaround
1058           corrects this value, ensuring cache maintenance operations which use
1059           it behave as intended and avoiding data corruption.
1060
1061 config ARM_ERRATA_720789
1062         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1063         depends on CPU_V7
1064         help
1065           This option enables the workaround for the 720789 Cortex-A9 (prior to
1066           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1067           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1068           As a consequence of this erratum, some TLB entries which should be
1069           invalidated are not, resulting in an incoherency in the system page
1070           tables. The workaround changes the TLB flushing routines to invalidate
1071           entries regardless of the ASID.
1072
1073 config ARM_ERRATA_743622
1074         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1075         depends on CPU_V7
1076         depends on !ARCH_MULTIPLATFORM
1077         help
1078           This option enables the workaround for the 743622 Cortex-A9
1079           (r2p*) erratum. Under very rare conditions, a faulty
1080           optimisation in the Cortex-A9 Store Buffer may lead to data
1081           corruption. This workaround sets a specific bit in the diagnostic
1082           register of the Cortex-A9 which disables the Store Buffer
1083           optimisation, preventing the defect from occurring. This has no
1084           visible impact on the overall performance or power consumption of the
1085           processor.
1086
1087 config ARM_ERRATA_751472
1088         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1089         depends on CPU_V7
1090         depends on !ARCH_MULTIPLATFORM
1091         help
1092           This option enables the workaround for the 751472 Cortex-A9 (prior
1093           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1094           completion of a following broadcasted operation if the second
1095           operation is received by a CPU before the ICIALLUIS has completed,
1096           potentially leading to corrupted entries in the cache or TLB.
1097
1098 config ARM_ERRATA_754322
1099         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1100         depends on CPU_V7
1101         help
1102           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1103           r3p*) erratum. A speculative memory access may cause a page table walk
1104           which starts prior to an ASID switch but completes afterwards. This
1105           can populate the micro-TLB with a stale entry which may be hit with
1106           the new ASID. This workaround places two dsb instructions in the mm
1107           switching code so that no page table walks can cross the ASID switch.
1108
1109 config ARM_ERRATA_754327
1110         bool "ARM errata: no automatic Store Buffer drain"
1111         depends on CPU_V7 && SMP
1112         help
1113           This option enables the workaround for the 754327 Cortex-A9 (prior to
1114           r2p0) erratum. The Store Buffer does not have any automatic draining
1115           mechanism and therefore a livelock may occur if an external agent
1116           continuously polls a memory location waiting to observe an update.
1117           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1118           written polling loops from denying visibility of updates to memory.
1119
1120 config ARM_ERRATA_364296
1121         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1122         depends on CPU_V6
1123         help
1124           This options enables the workaround for the 364296 ARM1136
1125           r0p2 erratum (possible cache data corruption with
1126           hit-under-miss enabled). It sets the undocumented bit 31 in
1127           the auxiliary control register and the FI bit in the control
1128           register, thus disabling hit-under-miss without putting the
1129           processor into full low interrupt latency mode. ARM11MPCore
1130           is not affected.
1131
1132 config ARM_ERRATA_764369
1133         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1134         depends on CPU_V7 && SMP
1135         help
1136           This option enables the workaround for erratum 764369
1137           affecting Cortex-A9 MPCore with two or more processors (all
1138           current revisions). Under certain timing circumstances, a data
1139           cache line maintenance operation by MVA targeting an Inner
1140           Shareable memory region may fail to proceed up to either the
1141           Point of Coherency or to the Point of Unification of the
1142           system. This workaround adds a DSB instruction before the
1143           relevant cache maintenance functions and sets a specific bit
1144           in the diagnostic control register of the SCU.
1145
1146 config ARM_ERRATA_775420
1147        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1148        depends on CPU_V7
1149        help
1150          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1151          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1152          operation aborts with MMU exception, it might cause the processor
1153          to deadlock. This workaround puts DSB before executing ISB if
1154          an abort may occur on cache maintenance.
1155
1156 config ARM_ERRATA_798181
1157         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1158         depends on CPU_V7 && SMP
1159         help
1160           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1161           adequately shooting down all use of the old entries. This
1162           option enables the Linux kernel workaround for this erratum
1163           which sends an IPI to the CPUs that are running the same ASID
1164           as the one being invalidated.
1165
1166 config ARM_ERRATA_773022
1167         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1168         depends on CPU_V7
1169         help
1170           This option enables the workaround for the 773022 Cortex-A15
1171           (up to r0p4) erratum. In certain rare sequences of code, the
1172           loop buffer may deliver incorrect instructions. This
1173           workaround disables the loop buffer to avoid the erratum.
1174
1175 config ARM_ERRATA_818325_852422
1176         bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1177         depends on CPU_V7
1178         help
1179           This option enables the workaround for:
1180           - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1181             instruction might deadlock.  Fixed in r0p1.
1182           - Cortex-A12 852422: Execution of a sequence of instructions might
1183             lead to either a data corruption or a CPU deadlock.  Not fixed in
1184             any Cortex-A12 cores yet.
1185           This workaround for all both errata involves setting bit[12] of the
1186           Feature Register. This bit disables an optimisation applied to a
1187           sequence of 2 instructions that use opposing condition codes.
1188
1189 config ARM_ERRATA_821420
1190         bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1191         depends on CPU_V7
1192         help
1193           This option enables the workaround for the 821420 Cortex-A12
1194           (all revs) erratum. In very rare timing conditions, a sequence
1195           of VMOV to Core registers instructions, for which the second
1196           one is in the shadow of a branch or abort, can lead to a
1197           deadlock when the VMOV instructions are issued out-of-order.
1198
1199 config ARM_ERRATA_825619
1200         bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1201         depends on CPU_V7
1202         help
1203           This option enables the workaround for the 825619 Cortex-A12
1204           (all revs) erratum. Within rare timing constraints, executing a
1205           DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1206           and Device/Strongly-Ordered loads and stores might cause deadlock
1207
1208 config ARM_ERRATA_852421
1209         bool "ARM errata: A17: DMB ST might fail to create order between stores"
1210         depends on CPU_V7
1211         help
1212           This option enables the workaround for the 852421 Cortex-A17
1213           (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1214           execution of a DMB ST instruction might fail to properly order
1215           stores from GroupA and stores from GroupB.
1216
1217 config ARM_ERRATA_852423
1218         bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1219         depends on CPU_V7
1220         help
1221           This option enables the workaround for:
1222           - Cortex-A17 852423: Execution of a sequence of instructions might
1223             lead to either a data corruption or a CPU deadlock.  Not fixed in
1224             any Cortex-A17 cores yet.
1225           This is identical to Cortex-A12 erratum 852422.  It is a separate
1226           config option from the A12 erratum due to the way errata are checked
1227           for and handled.
1228
1229 endmenu
1230
1231 source "arch/arm/common/Kconfig"
1232
1233 menu "Bus support"
1234
1235 config ISA
1236         bool
1237         help
1238           Find out whether you have ISA slots on your motherboard.  ISA is the
1239           name of a bus system, i.e. the way the CPU talks to the other stuff
1240           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1241           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1242           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1243
1244 # Select ISA DMA controller support
1245 config ISA_DMA
1246         bool
1247         select ISA_DMA_API
1248
1249 # Select ISA DMA interface
1250 config ISA_DMA_API
1251         bool
1252
1253 config PCI
1254         bool "PCI support" if MIGHT_HAVE_PCI
1255         help
1256           Find out whether you have a PCI motherboard. PCI is the name of a
1257           bus system, i.e. the way the CPU talks to the other stuff inside
1258           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1259           VESA. If you have PCI, say Y, otherwise N.
1260
1261 config PCI_DOMAINS
1262         bool
1263         depends on PCI
1264
1265 config PCI_DOMAINS_GENERIC
1266         def_bool PCI_DOMAINS
1267
1268 config PCI_NANOENGINE
1269         bool "BSE nanoEngine PCI support"
1270         depends on SA1100_NANOENGINE
1271         help
1272           Enable PCI on the BSE nanoEngine board.
1273
1274 config PCI_SYSCALL
1275         def_bool PCI
1276
1277 config PCI_HOST_ITE8152
1278         bool
1279         depends on PCI && MACH_ARMCORE
1280         default y
1281         select DMABOUNCE
1282
1283 source "drivers/pci/Kconfig"
1284
1285 source "drivers/pcmcia/Kconfig"
1286
1287 endmenu
1288
1289 menu "Kernel Features"
1290
1291 config HAVE_SMP
1292         bool
1293         help
1294           This option should be selected by machines which have an SMP-
1295           capable CPU.
1296
1297           The only effect of this option is to make the SMP-related
1298           options available to the user for configuration.
1299
1300 config SMP
1301         bool "Symmetric Multi-Processing"
1302         depends on CPU_V6K || CPU_V7
1303         depends on GENERIC_CLOCKEVENTS
1304         depends on HAVE_SMP
1305         depends on MMU || ARM_MPU
1306         select IRQ_WORK
1307         help
1308           This enables support for systems with more than one CPU. If you have
1309           a system with only one CPU, say N. If you have a system with more
1310           than one CPU, say Y.
1311
1312           If you say N here, the kernel will run on uni- and multiprocessor
1313           machines, but will use only one CPU of a multiprocessor machine. If
1314           you say Y here, the kernel will run on many, but not all,
1315           uniprocessor machines. On a uniprocessor machine, the kernel
1316           will run faster if you say N here.
1317
1318           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1319           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1320           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1321
1322           If you don't know what to do here, say N.
1323
1324 config SMP_ON_UP
1325         bool "Allow booting SMP kernel on uniprocessor systems"
1326         depends on SMP && !XIP_KERNEL && MMU
1327         default y
1328         help
1329           SMP kernels contain instructions which fail on non-SMP processors.
1330           Enabling this option allows the kernel to modify itself to make
1331           these instructions safe.  Disabling it allows about 1K of space
1332           savings.
1333
1334           If you don't know what to do here, say Y.
1335
1336 config ARM_CPU_TOPOLOGY
1337         bool "Support cpu topology definition"
1338         depends on SMP && CPU_V7
1339         default y
1340         help
1341           Support ARM cpu topology definition. The MPIDR register defines
1342           affinity between processors which is then used to describe the cpu
1343           topology of an ARM System.
1344
1345 config SCHED_MC
1346         bool "Multi-core scheduler support"
1347         depends on ARM_CPU_TOPOLOGY
1348         help
1349           Multi-core scheduler support improves the CPU scheduler's decision
1350           making when dealing with multi-core CPU chips at a cost of slightly
1351           increased overhead in some places. If unsure say N here.
1352
1353 config SCHED_SMT
1354         bool "SMT scheduler support"
1355         depends on ARM_CPU_TOPOLOGY
1356         help
1357           Improves the CPU scheduler's decision making when dealing with
1358           MultiThreading at a cost of slightly increased overhead in some
1359           places. If unsure say N here.
1360
1361 config HAVE_ARM_SCU
1362         bool
1363         help
1364           This option enables support for the ARM system coherency unit
1365
1366 config HAVE_ARM_ARCH_TIMER
1367         bool "Architected timer support"
1368         depends on CPU_V7
1369         select ARM_ARCH_TIMER
1370         select GENERIC_CLOCKEVENTS
1371         help
1372           This option enables support for the ARM architected timer
1373
1374 config HAVE_ARM_TWD
1375         bool
1376         select CLKSRC_OF if OF
1377         help
1378           This options enables support for the ARM timer and watchdog unit
1379
1380 config MCPM
1381         bool "Multi-Cluster Power Management"
1382         depends on CPU_V7 && SMP
1383         help
1384           This option provides the common power management infrastructure
1385           for (multi-)cluster based systems, such as big.LITTLE based
1386           systems.
1387
1388 config MCPM_QUAD_CLUSTER
1389         bool
1390         depends on MCPM
1391         help
1392           To avoid wasting resources unnecessarily, MCPM only supports up
1393           to 2 clusters by default.
1394           Platforms with 3 or 4 clusters that use MCPM must select this
1395           option to allow the additional clusters to be managed.
1396
1397 config BIG_LITTLE
1398         bool "big.LITTLE support (Experimental)"
1399         depends on CPU_V7 && SMP
1400         select MCPM
1401         help
1402           This option enables support selections for the big.LITTLE
1403           system architecture.
1404
1405 config BL_SWITCHER
1406         bool "big.LITTLE switcher support"
1407         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1408         select CPU_PM
1409         help
1410           The big.LITTLE "switcher" provides the core functionality to
1411           transparently handle transition between a cluster of A15's
1412           and a cluster of A7's in a big.LITTLE system.
1413
1414 config BL_SWITCHER_DUMMY_IF
1415         tristate "Simple big.LITTLE switcher user interface"
1416         depends on BL_SWITCHER && DEBUG_KERNEL
1417         help
1418           This is a simple and dummy char dev interface to control
1419           the big.LITTLE switcher core code.  It is meant for
1420           debugging purposes only.
1421
1422 choice
1423         prompt "Memory split"
1424         depends on MMU
1425         default VMSPLIT_3G
1426         help
1427           Select the desired split between kernel and user memory.
1428
1429           If you are not absolutely sure what you are doing, leave this
1430           option alone!
1431
1432         config VMSPLIT_3G
1433                 bool "3G/1G user/kernel split"
1434         config VMSPLIT_3G_OPT
1435                 bool "3G/1G user/kernel split (for full 1G low memory)"
1436         config VMSPLIT_2G
1437                 bool "2G/2G user/kernel split"
1438         config VMSPLIT_1G
1439                 bool "1G/3G user/kernel split"
1440 endchoice
1441
1442 config PAGE_OFFSET
1443         hex
1444         default PHYS_OFFSET if !MMU
1445         default 0x40000000 if VMSPLIT_1G
1446         default 0x80000000 if VMSPLIT_2G
1447         default 0xB0000000 if VMSPLIT_3G_OPT
1448         default 0xC0000000
1449
1450 config NR_CPUS
1451         int "Maximum number of CPUs (2-32)"
1452         range 2 32
1453         depends on SMP
1454         default "4"
1455
1456 config HOTPLUG_CPU
1457         bool "Support for hot-pluggable CPUs"
1458         depends on SMP
1459         help
1460           Say Y here to experiment with turning CPUs off and on.  CPUs
1461           can be controlled through /sys/devices/system/cpu.
1462
1463 config ARM_PSCI
1464         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1465         depends on HAVE_ARM_SMCCC
1466         select ARM_PSCI_FW
1467         help
1468           Say Y here if you want Linux to communicate with system firmware
1469           implementing the PSCI specification for CPU-centric power
1470           management operations described in ARM document number ARM DEN
1471           0022A ("Power State Coordination Interface System Software on
1472           ARM processors").
1473
1474 # The GPIO number here must be sorted by descending number. In case of
1475 # a multiplatform kernel, we just want the highest value required by the
1476 # selected platforms.
1477 config ARCH_NR_GPIO
1478         int
1479         default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1480                 ARCH_ZYNQ
1481         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1482                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1483         default 416 if ARCH_SUNXI
1484         default 392 if ARCH_U8500
1485         default 352 if ARCH_VT8500
1486         default 288 if ARCH_ROCKCHIP
1487         default 264 if MACH_H4700
1488         default 0
1489         help
1490           Maximum number of GPIOs in the system.
1491
1492           If unsure, leave the default value.
1493
1494 source kernel/Kconfig.preempt
1495
1496 config HZ_FIXED
1497         int
1498         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1499                 ARCH_S5PV210 || ARCH_EXYNOS4
1500         default 128 if SOC_AT91RM9200
1501         default 0
1502
1503 choice
1504         depends on HZ_FIXED = 0
1505         prompt "Timer frequency"
1506
1507 config HZ_100
1508         bool "100 Hz"
1509
1510 config HZ_200
1511         bool "200 Hz"
1512
1513 config HZ_250
1514         bool "250 Hz"
1515
1516 config HZ_300
1517         bool "300 Hz"
1518
1519 config HZ_500
1520         bool "500 Hz"
1521
1522 config HZ_1000
1523         bool "1000 Hz"
1524
1525 endchoice
1526
1527 config HZ
1528         int
1529         default HZ_FIXED if HZ_FIXED != 0
1530         default 100 if HZ_100
1531         default 200 if HZ_200
1532         default 250 if HZ_250
1533         default 300 if HZ_300
1534         default 500 if HZ_500
1535         default 1000
1536
1537 config SCHED_HRTICK
1538         def_bool HIGH_RES_TIMERS
1539
1540 config THUMB2_KERNEL
1541         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1542         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1543         default y if CPU_THUMBONLY
1544         select AEABI
1545         select ARM_ASM_UNIFIED
1546         select ARM_UNWIND
1547         help
1548           By enabling this option, the kernel will be compiled in
1549           Thumb-2 mode. A compiler/assembler that understand the unified
1550           ARM-Thumb syntax is needed.
1551
1552           If unsure, say N.
1553
1554 config THUMB2_AVOID_R_ARM_THM_JUMP11
1555         bool "Work around buggy Thumb-2 short branch relocations in gas"
1556         depends on THUMB2_KERNEL && MODULES
1557         default y
1558         help
1559           Various binutils versions can resolve Thumb-2 branches to
1560           locally-defined, preemptible global symbols as short-range "b.n"
1561           branch instructions.
1562
1563           This is a problem, because there's no guarantee the final
1564           destination of the symbol, or any candidate locations for a
1565           trampoline, are within range of the branch.  For this reason, the
1566           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1567           relocation in modules at all, and it makes little sense to add
1568           support.
1569
1570           The symptom is that the kernel fails with an "unsupported
1571           relocation" error when loading some modules.
1572
1573           Until fixed tools are available, passing
1574           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1575           code which hits this problem, at the cost of a bit of extra runtime
1576           stack usage in some cases.
1577
1578           The problem is described in more detail at:
1579               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1580
1581           Only Thumb-2 kernels are affected.
1582
1583           Unless you are sure your tools don't have this problem, say Y.
1584
1585 config ARM_ASM_UNIFIED
1586         bool
1587
1588 config ARM_PATCH_IDIV
1589         bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1590         depends on CPU_32v7 && !XIP_KERNEL
1591         default y
1592         help
1593           The ARM compiler inserts calls to __aeabi_idiv() and
1594           __aeabi_uidiv() when it needs to perform division on signed
1595           and unsigned integers. Some v7 CPUs have support for the sdiv
1596           and udiv instructions that can be used to implement those
1597           functions.
1598
1599           Enabling this option allows the kernel to modify itself to
1600           replace the first two instructions of these library functions
1601           with the sdiv or udiv plus "bx lr" instructions when the CPU
1602           it is running on supports them. Typically this will be faster
1603           and less power intensive than running the original library
1604           code to do integer division.
1605
1606 config AEABI
1607         bool "Use the ARM EABI to compile the kernel"
1608         help
1609           This option allows for the kernel to be compiled using the latest
1610           ARM ABI (aka EABI).  This is only useful if you are using a user
1611           space environment that is also compiled with EABI.
1612
1613           Since there are major incompatibilities between the legacy ABI and
1614           EABI, especially with regard to structure member alignment, this
1615           option also changes the kernel syscall calling convention to
1616           disambiguate both ABIs and allow for backward compatibility support
1617           (selected with CONFIG_OABI_COMPAT).
1618
1619           To use this you need GCC version 4.0.0 or later.
1620
1621 config OABI_COMPAT
1622         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1623         depends on AEABI && !THUMB2_KERNEL
1624         help
1625           This option preserves the old syscall interface along with the
1626           new (ARM EABI) one. It also provides a compatibility layer to
1627           intercept syscalls that have structure arguments which layout
1628           in memory differs between the legacy ABI and the new ARM EABI
1629           (only for non "thumb" binaries). This option adds a tiny
1630           overhead to all syscalls and produces a slightly larger kernel.
1631
1632           The seccomp filter system will not be available when this is
1633           selected, since there is no way yet to sensibly distinguish
1634           between calling conventions during filtering.
1635
1636           If you know you'll be using only pure EABI user space then you
1637           can say N here. If this option is not selected and you attempt
1638           to execute a legacy ABI binary then the result will be
1639           UNPREDICTABLE (in fact it can be predicted that it won't work
1640           at all). If in doubt say N.
1641
1642 config ARCH_HAS_HOLES_MEMORYMODEL
1643         bool
1644
1645 config ARCH_SPARSEMEM_ENABLE
1646         bool
1647
1648 config ARCH_SPARSEMEM_DEFAULT
1649         def_bool ARCH_SPARSEMEM_ENABLE
1650
1651 config ARCH_SELECT_MEMORY_MODEL
1652         def_bool ARCH_SPARSEMEM_ENABLE
1653
1654 config HAVE_ARCH_PFN_VALID
1655         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1656
1657 config HAVE_GENERIC_RCU_GUP
1658         def_bool y
1659         depends on ARM_LPAE
1660
1661 config HIGHMEM
1662         bool "High Memory Support"
1663         depends on MMU
1664         help
1665           The address space of ARM processors is only 4 Gigabytes large
1666           and it has to accommodate user address space, kernel address
1667           space as well as some memory mapped IO. That means that, if you
1668           have a large amount of physical memory and/or IO, not all of the
1669           memory can be "permanently mapped" by the kernel. The physical
1670           memory that is not permanently mapped is called "high memory".
1671
1672           Depending on the selected kernel/user memory split, minimum
1673           vmalloc space and actual amount of RAM, you may not need this
1674           option which should result in a slightly faster kernel.
1675
1676           If unsure, say n.
1677
1678 config HIGHPTE
1679         bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1680         depends on HIGHMEM
1681         default y
1682         help
1683           The VM uses one page of physical memory for each page table.
1684           For systems with a lot of processes, this can use a lot of
1685           precious low memory, eventually leading to low memory being
1686           consumed by page tables.  Setting this option will allow
1687           user-space 2nd level page tables to reside in high memory.
1688
1689 config CPU_SW_DOMAIN_PAN
1690         bool "Enable use of CPU domains to implement privileged no-access"
1691         depends on MMU && !ARM_LPAE
1692         default y
1693         help
1694           Increase kernel security by ensuring that normal kernel accesses
1695           are unable to access userspace addresses.  This can help prevent
1696           use-after-free bugs becoming an exploitable privilege escalation
1697           by ensuring that magic values (such as LIST_POISON) will always
1698           fault when dereferenced.
1699
1700           CPUs with low-vector mappings use a best-efforts implementation.
1701           Their lower 1MB needs to remain accessible for the vectors, but
1702           the remainder of userspace will become appropriately inaccessible.
1703
1704 config HW_PERF_EVENTS
1705         def_bool y
1706         depends on ARM_PMU
1707
1708 config SYS_SUPPORTS_HUGETLBFS
1709        def_bool y
1710        depends on ARM_LPAE
1711
1712 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1713        def_bool y
1714        depends on ARM_LPAE
1715
1716 config ARCH_WANT_GENERAL_HUGETLB
1717         def_bool y
1718
1719 config ARM_MODULE_PLTS
1720         bool "Use PLTs to allow module memory to spill over into vmalloc area"
1721         depends on MODULES
1722         help
1723           Allocate PLTs when loading modules so that jumps and calls whose
1724           targets are too far away for their relative offsets to be encoded
1725           in the instructions themselves can be bounced via veneers in the
1726           module's PLT. This allows modules to be allocated in the generic
1727           vmalloc area after the dedicated module memory area has been
1728           exhausted. The modules will use slightly more memory, but after
1729           rounding up to page size, the actual memory footprint is usually
1730           the same.
1731
1732           Say y if you are getting out of memory errors while loading modules
1733
1734 source "mm/Kconfig"
1735
1736 config FORCE_MAX_ZONEORDER
1737         int "Maximum zone order"
1738         default "12" if SOC_AM33XX
1739         default "9" if SA1111 || ARCH_EFM32
1740         default "11"
1741         help
1742           The kernel memory allocator divides physically contiguous memory
1743           blocks into "zones", where each zone is a power of two number of
1744           pages.  This option selects the largest power of two that the kernel
1745           keeps in the memory allocator.  If you need to allocate very large
1746           blocks of physically contiguous memory, then you may need to
1747           increase this value.
1748
1749           This config option is actually maximum order plus one. For example,
1750           a value of 11 means that the largest free memory block is 2^10 pages.
1751
1752 config ALIGNMENT_TRAP
1753         bool
1754         depends on CPU_CP15_MMU
1755         default y if !ARCH_EBSA110
1756         select HAVE_PROC_CPU if PROC_FS
1757         help
1758           ARM processors cannot fetch/store information which is not
1759           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1760           address divisible by 4. On 32-bit ARM processors, these non-aligned
1761           fetch/store instructions will be emulated in software if you say
1762           here, which has a severe performance impact. This is necessary for
1763           correct operation of some network protocols. With an IP-only
1764           configuration it is safe to say N, otherwise say Y.
1765
1766 config UACCESS_WITH_MEMCPY
1767         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1768         depends on MMU
1769         default y if CPU_FEROCEON
1770         help
1771           Implement faster copy_to_user and clear_user methods for CPU
1772           cores where a 8-word STM instruction give significantly higher
1773           memory write throughput than a sequence of individual 32bit stores.
1774
1775           A possible side effect is a slight increase in scheduling latency
1776           between threads sharing the same address space if they invoke
1777           such copy operations with large buffers.
1778
1779           However, if the CPU data cache is using a write-allocate mode,
1780           this option is unlikely to provide any performance gain.
1781
1782 config SECCOMP
1783         bool
1784         prompt "Enable seccomp to safely compute untrusted bytecode"
1785         ---help---
1786           This kernel feature is useful for number crunching applications
1787           that may need to compute untrusted bytecode during their
1788           execution. By using pipes or other transports made available to
1789           the process as file descriptors supporting the read/write
1790           syscalls, it's possible to isolate those applications in
1791           their own address space using seccomp. Once seccomp is
1792           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1793           and the task is only allowed to execute a few safe syscalls
1794           defined by each seccomp mode.
1795
1796 config SWIOTLB
1797         def_bool y
1798
1799 config IOMMU_HELPER
1800         def_bool SWIOTLB
1801
1802 config PARAVIRT
1803         bool "Enable paravirtualization code"
1804         help
1805           This changes the kernel so it can modify itself when it is run
1806           under a hypervisor, potentially improving performance significantly
1807           over full virtualization.
1808
1809 config PARAVIRT_TIME_ACCOUNTING
1810         bool "Paravirtual steal time accounting"
1811         select PARAVIRT
1812         default n
1813         help
1814           Select this option to enable fine granularity task steal time
1815           accounting. Time spent executing other tasks in parallel with
1816           the current vCPU is discounted from the vCPU power. To account for
1817           that, there can be a small performance impact.
1818
1819           If in doubt, say N here.
1820
1821 config XEN_DOM0
1822         def_bool y
1823         depends on XEN
1824
1825 config XEN
1826         bool "Xen guest support on ARM"
1827         depends on ARM && AEABI && OF
1828         depends on CPU_V7 && !CPU_V6
1829         depends on !GENERIC_ATOMIC64
1830         depends on MMU
1831         select ARCH_DMA_ADDR_T_64BIT
1832         select ARM_PSCI
1833         select SWIOTLB_XEN
1834         select PARAVIRT
1835         help
1836           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1837
1838 endmenu
1839
1840 menu "Boot options"
1841
1842 config USE_OF
1843         bool "Flattened Device Tree support"
1844         select IRQ_DOMAIN
1845         select OF
1846         help
1847           Include support for flattened device tree machine descriptions.
1848
1849 config ATAGS
1850         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1851         default y
1852         help
1853           This is the traditional way of passing data to the kernel at boot
1854           time. If you are solely relying on the flattened device tree (or
1855           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1856           to remove ATAGS support from your kernel binary.  If unsure,
1857           leave this to y.
1858
1859 config DEPRECATED_PARAM_STRUCT
1860         bool "Provide old way to pass kernel parameters"
1861         depends on ATAGS
1862         help
1863           This was deprecated in 2001 and announced to live on for 5 years.
1864           Some old boot loaders still use this way.
1865
1866 # Compressed boot loader in ROM.  Yes, we really want to ask about
1867 # TEXT and BSS so we preserve their values in the config files.
1868 config ZBOOT_ROM_TEXT
1869         hex "Compressed ROM boot loader base address"
1870         default "0"
1871         help
1872           The physical address at which the ROM-able zImage is to be
1873           placed in the target.  Platforms which normally make use of
1874           ROM-able zImage formats normally set this to a suitable
1875           value in their defconfig file.
1876
1877           If ZBOOT_ROM is not enabled, this has no effect.
1878
1879 config ZBOOT_ROM_BSS
1880         hex "Compressed ROM boot loader BSS address"
1881         default "0"
1882         help
1883           The base address of an area of read/write memory in the target
1884           for the ROM-able zImage which must be available while the
1885           decompressor is running. It must be large enough to hold the
1886           entire decompressed kernel plus an additional 128 KiB.
1887           Platforms which normally make use of ROM-able zImage formats
1888           normally set this to a suitable value in their defconfig file.
1889
1890           If ZBOOT_ROM is not enabled, this has no effect.
1891
1892 config ZBOOT_ROM
1893         bool "Compressed boot loader in ROM/flash"
1894         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1895         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1896         help
1897           Say Y here if you intend to execute your compressed kernel image
1898           (zImage) directly from ROM or flash.  If unsure, say N.
1899
1900 config ARM_APPENDED_DTB
1901         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1902         depends on OF
1903         help
1904           With this option, the boot code will look for a device tree binary
1905           (DTB) appended to zImage
1906           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1907
1908           This is meant as a backward compatibility convenience for those
1909           systems with a bootloader that can't be upgraded to accommodate
1910           the documented boot protocol using a device tree.
1911
1912           Beware that there is very little in terms of protection against
1913           this option being confused by leftover garbage in memory that might
1914           look like a DTB header after a reboot if no actual DTB is appended
1915           to zImage.  Do not leave this option active in a production kernel
1916           if you don't intend to always append a DTB.  Proper passing of the
1917           location into r2 of a bootloader provided DTB is always preferable
1918           to this option.
1919
1920 config ARM_ATAG_DTB_COMPAT
1921         bool "Supplement the appended DTB with traditional ATAG information"
1922         depends on ARM_APPENDED_DTB
1923         help
1924           Some old bootloaders can't be updated to a DTB capable one, yet
1925           they provide ATAGs with memory configuration, the ramdisk address,
1926           the kernel cmdline string, etc.  Such information is dynamically
1927           provided by the bootloader and can't always be stored in a static
1928           DTB.  To allow a device tree enabled kernel to be used with such
1929           bootloaders, this option allows zImage to extract the information
1930           from the ATAG list and store it at run time into the appended DTB.
1931
1932 choice
1933         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1934         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1935
1936 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1937         bool "Use bootloader kernel arguments if available"
1938         help
1939           Uses the command-line options passed by the boot loader instead of
1940           the device tree bootargs property. If the boot loader doesn't provide
1941           any, the device tree bootargs property will be used.
1942
1943 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1944         bool "Extend with bootloader kernel arguments"
1945         help
1946           The command-line arguments provided by the boot loader will be
1947           appended to the the device tree bootargs property.
1948
1949 endchoice
1950
1951 config CMDLINE
1952         string "Default kernel command string"
1953         default ""
1954         help
1955           On some architectures (EBSA110 and CATS), there is currently no way
1956           for the boot loader to pass arguments to the kernel. For these
1957           architectures, you should supply some command-line options at build
1958           time by entering them here. As a minimum, you should specify the
1959           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1960
1961 choice
1962         prompt "Kernel command line type" if CMDLINE != ""
1963         default CMDLINE_FROM_BOOTLOADER
1964         depends on ATAGS
1965
1966 config CMDLINE_FROM_BOOTLOADER
1967         bool "Use bootloader kernel arguments if available"
1968         help
1969           Uses the command-line options passed by the boot loader. If
1970           the boot loader doesn't provide any, the default kernel command
1971           string provided in CMDLINE will be used.
1972
1973 config CMDLINE_EXTEND
1974         bool "Extend bootloader kernel arguments"
1975         help
1976           The command-line arguments provided by the boot loader will be
1977           appended to the default kernel command string.
1978
1979 config CMDLINE_FORCE
1980         bool "Always use the default kernel command string"
1981         help
1982           Always use the default kernel command string, even if the boot
1983           loader passes other arguments to the kernel.
1984           This is useful if you cannot or don't want to change the
1985           command-line options your boot loader passes to the kernel.
1986 endchoice
1987
1988 config XIP_KERNEL
1989         bool "Kernel Execute-In-Place from ROM"
1990         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1991         help
1992           Execute-In-Place allows the kernel to run from non-volatile storage
1993           directly addressable by the CPU, such as NOR flash. This saves RAM
1994           space since the text section of the kernel is not loaded from flash
1995           to RAM.  Read-write sections, such as the data section and stack,
1996           are still copied to RAM.  The XIP kernel is not compressed since
1997           it has to run directly from flash, so it will take more space to
1998           store it.  The flash address used to link the kernel object files,
1999           and for storing it, is configuration dependent. Therefore, if you
2000           say Y here, you must know the proper physical address where to
2001           store the kernel image depending on your own flash memory usage.
2002
2003           Also note that the make target becomes "make xipImage" rather than
2004           "make zImage" or "make Image".  The final kernel binary to put in
2005           ROM memory will be arch/arm/boot/xipImage.
2006
2007           If unsure, say N.
2008
2009 config XIP_PHYS_ADDR
2010         hex "XIP Kernel Physical Location"
2011         depends on XIP_KERNEL
2012         default "0x00080000"
2013         help
2014           This is the physical address in your flash memory the kernel will
2015           be linked for and stored to.  This address is dependent on your
2016           own flash usage.
2017
2018 config KEXEC
2019         bool "Kexec system call (EXPERIMENTAL)"
2020         depends on (!SMP || PM_SLEEP_SMP)
2021         depends on !CPU_V7M
2022         select KEXEC_CORE
2023         help
2024           kexec is a system call that implements the ability to shutdown your
2025           current kernel, and to start another kernel.  It is like a reboot
2026           but it is independent of the system firmware.   And like a reboot
2027           you can start any kernel with it, not just Linux.
2028
2029           It is an ongoing process to be certain the hardware in a machine
2030           is properly shutdown, so do not be surprised if this code does not
2031           initially work for you.
2032
2033 config ATAGS_PROC
2034         bool "Export atags in procfs"
2035         depends on ATAGS && KEXEC
2036         default y
2037         help
2038           Should the atags used to boot the kernel be exported in an "atags"
2039           file in procfs. Useful with kexec.
2040
2041 config CRASH_DUMP
2042         bool "Build kdump crash kernel (EXPERIMENTAL)"
2043         help
2044           Generate crash dump after being started by kexec. This should
2045           be normally only set in special crash dump kernels which are
2046           loaded in the main kernel with kexec-tools into a specially
2047           reserved region and then later executed after a crash by
2048           kdump/kexec. The crash dump kernel must be compiled to a
2049           memory address not used by the main kernel
2050
2051           For more details see Documentation/kdump/kdump.txt
2052
2053 config AUTO_ZRELADDR
2054         bool "Auto calculation of the decompressed kernel image address"
2055         help
2056           ZRELADDR is the physical address where the decompressed kernel
2057           image will be placed. If AUTO_ZRELADDR is selected, the address
2058           will be determined at run-time by masking the current IP with
2059           0xf8000000. This assumes the zImage being placed in the first 128MB
2060           from start of memory.
2061
2062 config EFI_STUB
2063         bool
2064
2065 config EFI
2066         bool "UEFI runtime support"
2067         depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2068         select UCS2_STRING
2069         select EFI_PARAMS_FROM_FDT
2070         select EFI_STUB
2071         select EFI_ARMSTUB
2072         select EFI_RUNTIME_WRAPPERS
2073         ---help---
2074           This option provides support for runtime services provided
2075           by UEFI firmware (such as non-volatile variables, realtime
2076           clock, and platform reset). A UEFI stub is also provided to
2077           allow the kernel to be booted as an EFI application. This
2078           is only useful for kernels that may run on systems that have
2079           UEFI firmware.
2080
2081 endmenu
2082
2083 menu "CPU Power Management"
2084
2085 source "drivers/cpufreq/Kconfig"
2086
2087 source "drivers/cpuidle/Kconfig"
2088
2089 endmenu
2090
2091 menu "Floating point emulation"
2092
2093 comment "At least one emulation must be selected"
2094
2095 config FPE_NWFPE
2096         bool "NWFPE math emulation"
2097         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2098         ---help---
2099           Say Y to include the NWFPE floating point emulator in the kernel.
2100           This is necessary to run most binaries. Linux does not currently
2101           support floating point hardware so you need to say Y here even if
2102           your machine has an FPA or floating point co-processor podule.
2103
2104           You may say N here if you are going to load the Acorn FPEmulator
2105           early in the bootup.
2106
2107 config FPE_NWFPE_XP
2108         bool "Support extended precision"
2109         depends on FPE_NWFPE
2110         help
2111           Say Y to include 80-bit support in the kernel floating-point
2112           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2113           Note that gcc does not generate 80-bit operations by default,
2114           so in most cases this option only enlarges the size of the
2115           floating point emulator without any good reason.
2116
2117           You almost surely want to say N here.
2118
2119 config FPE_FASTFPE
2120         bool "FastFPE math emulation (EXPERIMENTAL)"
2121         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2122         ---help---
2123           Say Y here to include the FAST floating point emulator in the kernel.
2124           This is an experimental much faster emulator which now also has full
2125           precision for the mantissa.  It does not support any exceptions.
2126           It is very simple, and approximately 3-6 times faster than NWFPE.
2127
2128           It should be sufficient for most programs.  It may be not suitable
2129           for scientific calculations, but you have to check this for yourself.
2130           If you do not feel you need a faster FP emulation you should better
2131           choose NWFPE.
2132
2133 config VFP
2134         bool "VFP-format floating point maths"
2135         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2136         help
2137           Say Y to include VFP support code in the kernel. This is needed
2138           if your hardware includes a VFP unit.
2139
2140           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2141           release notes and additional status information.
2142
2143           Say N if your target does not have VFP hardware.
2144
2145 config VFPv3
2146         bool
2147         depends on VFP
2148         default y if CPU_V7
2149
2150 config NEON
2151         bool "Advanced SIMD (NEON) Extension support"
2152         depends on VFPv3 && CPU_V7
2153         help
2154           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2155           Extension.
2156
2157 config KERNEL_MODE_NEON
2158         bool "Support for NEON in kernel mode"
2159         depends on NEON && AEABI
2160         help
2161           Say Y to include support for NEON in kernel mode.
2162
2163 endmenu
2164
2165 menu "Userspace binary formats"
2166
2167 source "fs/Kconfig.binfmt"
2168
2169 endmenu
2170
2171 menu "Power management options"
2172
2173 source "kernel/power/Kconfig"
2174
2175 config ARCH_SUSPEND_POSSIBLE
2176         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2177                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2178         def_bool y
2179
2180 config ARM_CPU_SUSPEND
2181         def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2182         depends on ARCH_SUSPEND_POSSIBLE
2183
2184 config ARCH_HIBERNATION_POSSIBLE
2185         bool
2186         depends on MMU
2187         default y if ARCH_SUSPEND_POSSIBLE
2188
2189 endmenu
2190
2191 source "net/Kconfig"
2192
2193 source "drivers/Kconfig"
2194
2195 source "drivers/firmware/Kconfig"
2196
2197 source "fs/Kconfig"
2198
2199 source "arch/arm/Kconfig.debug"
2200
2201 source "security/Kconfig"
2202
2203 source "crypto/Kconfig"
2204 if CRYPTO
2205 source "arch/arm/crypto/Kconfig"
2206 endif
2207
2208 source "lib/Kconfig"
2209
2210 source "arch/arm/kvm/Kconfig"