arch/arm/Kconfig

   1 config ARM
   2         bool
   3         default y
   4         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
   5         select ARCH_HAS_DEVMEM_IS_ALLOWED
   6         select ARCH_HAS_ELF_RANDOMIZE
   7         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
   8         select ARCH_HAVE_CUSTOM_GPIO_H
   9         select ARCH_HAS_GCOV_PROFILE_ALL
  10         select ARCH_MIGHT_HAVE_PC_PARPORT
  11         select ARCH_SUPPORTS_ATOMIC_RMW
  12         select ARCH_USE_BUILTIN_BSWAP
  13         select ARCH_USE_CMPXCHG_LOCKREF
  14         select ARCH_WANT_IPC_PARSE_VERSION
  15         select BUILDTIME_EXTABLE_SORT if MMU
  16         select CLONE_BACKWARDS
  17         select CPU_PM if (SUSPEND || CPU_IDLE)
  18         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
  19         select EDAC_SUPPORT
  20         select EDAC_ATOMIC_SCRUB
  21         select GENERIC_ALLOCATOR
  22         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
  23         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
  24         select GENERIC_EARLY_IOREMAP
  25         select GENERIC_IDLE_POLL_SETUP
  26         select GENERIC_IRQ_PROBE
  27         select GENERIC_IRQ_SHOW
  28         select GENERIC_IRQ_SHOW_LEVEL
  29         select GENERIC_PCI_IOMAP
  30         select GENERIC_SCHED_CLOCK
  31         select GENERIC_SMP_IDLE_THREAD
  32         select GENERIC_STRNCPY_FROM_USER
  33         select GENERIC_STRNLEN_USER
  34         select HANDLE_DOMAIN_IRQ
  35         select HARDIRQS_SW_RESEND
  36         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
  37         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
  38         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
  39         select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
  40         select HAVE_ARCH_MMAP_RND_BITS if MMU
  41         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
  42         select HAVE_ARCH_TRACEHOOK
  43         select HAVE_ARM_SMCCC if CPU_V7
  44         select HAVE_CBPF_JIT
  45         select HAVE_CC_STACKPROTECTOR
  46         select HAVE_CONTEXT_TRACKING
  47         select HAVE_C_RECORDMCOUNT
  48         select HAVE_DEBUG_KMEMLEAK
  49         select HAVE_DMA_API_DEBUG
  50         select HAVE_DMA_CONTIGUOUS if MMU
  51         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
  52         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
  53         select HAVE_EXIT_THREAD
  54         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
  55         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
  56         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
  57         select HAVE_GCC_PLUGINS
  58         select HAVE_GENERIC_DMA_COHERENT
  59         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
  60         select HAVE_IDE if PCI || ISA || PCMCIA
  61         select HAVE_IRQ_TIME_ACCOUNTING
  62         select HAVE_KERNEL_GZIP
  63         select HAVE_KERNEL_LZ4
  64         select HAVE_KERNEL_LZMA
  65         select HAVE_KERNEL_LZO
  66         select HAVE_KERNEL_XZ
  67         select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
  68         select HAVE_KRETPROBES if (HAVE_KPROBES)
  69         select HAVE_MEMBLOCK
  70         select HAVE_MOD_ARCH_SPECIFIC
  71         select HAVE_NMI
  72         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
  73         select HAVE_OPTPROBES if !THUMB2_KERNEL
  74         select HAVE_PERF_EVENTS
  75         select HAVE_PERF_REGS
  76         select HAVE_PERF_USER_STACK_DUMP
  77         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
  78         select HAVE_REGS_AND_STACK_ACCESS_API
  79         select HAVE_SYSCALL_TRACEPOINTS
  80         select HAVE_UID16
  81         select HAVE_VIRT_CPU_ACCOUNTING_GEN
  82         select IRQ_FORCED_THREADING
  83         select MODULES_USE_ELF_REL
  84         select NO_BOOTMEM
  85         select OF_EARLY_FLATTREE if OF
  86         select OF_RESERVED_MEM if OF
  87         select OLD_SIGACTION
  88         select OLD_SIGSUSPEND3
  89         select PERF_USE_VMALLOC
  90         select RTC_LIB
  91         select SYS_SUPPORTS_APM_EMULATION
  92         # Above selects are sorted alphabetically; please add new ones
  93         # according to that.  Thanks.
  94         help
  95           The ARM series is a line of low-power-consumption RISC chip designs
  96           licensed by ARM Ltd and targeted at embedded applications and
  97           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
  98           manufactured, but legacy ARM-based PC hardware remains popular in
  99           Europe.  There is an ARM Linux project with a web page at
 100           <http://www.arm.linux.org.uk/>.
 101
 102 config ARM_HAS_SG_CHAIN
 103         select ARCH_HAS_SG_CHAIN
 104         bool
 105
 106 config NEED_SG_DMA_LENGTH
 107         bool
 108
 109 config ARM_DMA_USE_IOMMU
 110         bool
 111         select ARM_HAS_SG_CHAIN
 112         select NEED_SG_DMA_LENGTH
 113
 114 if ARM_DMA_USE_IOMMU
 115
 116 config ARM_DMA_IOMMU_ALIGNMENT
 117         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
 118         range 4 9
 119         default 8
 120         help
 121           DMA mapping framework by default aligns all buffers to the smallest
 122           PAGE_SIZE order which is greater than or equal to the requested buffer
 123           size. This works well for buffers up to a few hundreds kilobytes, but
 124           for larger buffers it just a waste of address space. Drivers which has
 125           relatively small addressing window (like 64Mib) might run out of
 126           virtual space with just a few allocations.
 127
 128           With this parameter you can specify the maximum PAGE_SIZE order for
 129           DMA IOMMU buffers. Larger buffers will be aligned only to this
 130           specified order. The order is expressed as a power of two multiplied
 131           by the PAGE_SIZE.
 132
 133 endif
 134
 135 config MIGHT_HAVE_PCI
 136         bool
 137
 138 config SYS_SUPPORTS_APM_EMULATION
 139         bool
 140
 141 config HAVE_TCM
 142         bool
 143         select GENERIC_ALLOCATOR
 144
 145 config HAVE_PROC_CPU
 146         bool
 147
 148 config NO_IOPORT_MAP
 149         bool
 150
 151 config EISA
 152         bool
 153         ---help---
 154           The Extended Industry Standard Architecture (EISA) bus was
 155           developed as an open alternative to the IBM MicroChannel bus.
 156
 157           The EISA bus provided some of the features of the IBM MicroChannel
 158           bus while maintaining backward compatibility with cards made for
 159           the older ISA bus.  The EISA bus saw limited use between 1988 and
 160           1995 when it was made obsolete by the PCI bus.
 161
 162           Say Y here if you are building a kernel for an EISA-based machine.
 163
 164           Otherwise, say N.
 165
 166 config SBUS
 167         bool
 168
 169 config STACKTRACE_SUPPORT
 170         bool
 171         default y
 172
 173 config LOCKDEP_SUPPORT
 174         bool
 175         default y
 176
 177 config TRACE_IRQFLAGS_SUPPORT
 178         bool
 179         default !CPU_V7M
 180
 181 config RWSEM_XCHGADD_ALGORITHM
 182         bool
 183         default y
 184
 185 config ARCH_HAS_ILOG2_U32
 186         bool
 187
 188 config ARCH_HAS_ILOG2_U64
 189         bool
 190
 191 config ARCH_HAS_BANDGAP
 192         bool
 193
 194 config FIX_EARLYCON_MEM
 195         def_bool y if MMU
 196
 197 config GENERIC_HWEIGHT
 198         bool
 199         default y
 200
 201 config GENERIC_CALIBRATE_DELAY
 202         bool
 203         default y
 204
 205 config ARCH_MAY_HAVE_PC_FDC
 206         bool
 207
 208 config ZONE_DMA
 209         bool
 210
 211 config NEED_DMA_MAP_STATE
 212        def_bool y
 213
 214 config ARCH_SUPPORTS_UPROBES
 215         def_bool y
 216
 217 config ARCH_HAS_DMA_SET_COHERENT_MASK
 218         bool
 219
 220 config GENERIC_ISA_DMA
 221         bool
 222
 223 config FIQ
 224         bool
 225
 226 config NEED_RET_TO_USER
 227         bool
 228
 229 config ARCH_MTD_XIP
 230         bool
 231
 232 config VECTORS_BASE
 233         hex
 234         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
 235         default DRAM_BASE if REMAP_VECTORS_TO_RAM
 236         default 0x00000000
 237         help
 238           The base address of exception vectors.  This must be two pages
 239           in size.
 240
 241 config ARM_PATCH_PHYS_VIRT
 242         bool "Patch physical to virtual translations at runtime" if EMBEDDED
 243         default y
 244         depends on !XIP_KERNEL && MMU
 245         help
 246           Patch phys-to-virt and virt-to-phys translation functions at
 247           boot and module load time according to the position of the
 248           kernel in system memory.
 249
 250           This can only be used with non-XIP MMU kernels where the base
 251           of physical memory is at a 16MB boundary.
 252
 253           Only disable this option if you know that you do not require
 254           this feature (eg, building a kernel for a single machine) and
 255           you need to shrink the kernel to the minimal size.
 256
 257 config NEED_MACH_IO_H
 258         bool
 259         help
 260           Select this when mach/io.h is required to provide special
 261           definitions for this platform.  The need for mach/io.h should
 262           be avoided when possible.
 263
 264 config NEED_MACH_MEMORY_H
 265         bool
 266         help
 267           Select this when mach/memory.h is required to provide special
 268           definitions for this platform.  The need for mach/memory.h should
 269           be avoided when possible.
 270
 271 config PHYS_OFFSET
 272         hex "Physical address of main memory" if MMU
 273         depends on !ARM_PATCH_PHYS_VIRT
 274         default DRAM_BASE if !MMU
 275         default 0x00000000 if ARCH_EBSA110 || \
 276                         ARCH_FOOTBRIDGE || \
 277                         ARCH_INTEGRATOR || \
 278                         ARCH_IOP13XX || \
 279                         ARCH_KS8695 || \
 280                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
 281         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
 282         default 0x20000000 if ARCH_S5PV210
 283         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
 284         default 0xc0000000 if ARCH_SA1100
 285         help
 286           Please provide the physical address corresponding to the
 287           location of main memory in your system.
 288
 289 config GENERIC_BUG
 290         def_bool y
 291         depends on BUG
 292
 293 config PGTABLE_LEVELS
 294         int
 295         default 3 if ARM_LPAE
 296         default 2
 297
 298 source "init/Kconfig"
 299
 300 source "kernel/Kconfig.freezer"
 301
 302 menu "System Type"
 303
 304 config MMU
 305         bool "MMU-based Paged Memory Management Support"
 306         default y
 307         help
 308           Select if you want MMU-based virtualised addressing space
 309           support by paged memory management. If unsure, say 'Y'.
 310
 311 config ARCH_MMAP_RND_BITS_MIN
 312         default 8
 313
 314 config ARCH_MMAP_RND_BITS_MAX
 315         default 14 if PAGE_OFFSET=0x40000000
 316         default 15 if PAGE_OFFSET=0x80000000
 317         default 16
 318
 319 #
 320 # The "ARM system type" choice list is ordered alphabetically by option
 321 # text.  Please add new entries in the option alphabetic order.
 322 #
 323 choice
 324         prompt "ARM system type"
 325         default ARM_SINGLE_ARMV7M if !MMU
 326         default ARCH_MULTIPLATFORM if MMU
 327
 328 config ARCH_MULTIPLATFORM
 329         bool "Allow multiple platforms to be selected"
 330         depends on MMU
 331         select ARM_HAS_SG_CHAIN
 332         select ARM_PATCH_PHYS_VIRT
 333         select AUTO_ZRELADDR
 334         select CLKSRC_OF
 335         select COMMON_CLK
 336         select GENERIC_CLOCKEVENTS
 337         select MIGHT_HAVE_PCI
 338         select MULTI_IRQ_HANDLER
 339         select SPARSE_IRQ
 340         select USE_OF
 341
 342 config ARM_SINGLE_ARMV7M
 343         bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
 344         depends on !MMU
 345         select ARM_NVIC
 346         select AUTO_ZRELADDR
 347         select CLKSRC_OF
 348         select COMMON_CLK
 349         select CPU_V7M
 350         select GENERIC_CLOCKEVENTS
 351         select NO_IOPORT_MAP
 352         select SPARSE_IRQ
 353         select USE_OF
 354
 355 config ARCH_GEMINI
 356         bool "Cortina Systems Gemini"
 357         select CLKSRC_MMIO
 358         select CPU_FA526
 359         select GENERIC_CLOCKEVENTS
 360         select GPIOLIB
 361         help
 362           Support for the Cortina Systems Gemini family SoCs
 363
 364 config ARCH_EBSA110
 365         bool "EBSA-110"
 366         select ARCH_USES_GETTIMEOFFSET
 367         select CPU_SA110
 368         select ISA
 369         select NEED_MACH_IO_H
 370         select NEED_MACH_MEMORY_H
 371         select NO_IOPORT_MAP
 372         help
 373           This is an evaluation board for the StrongARM processor available
 374           from Digital. It has limited hardware on-board, including an
 375           Ethernet interface, two PCMCIA sockets, two serial ports and a
 376           parallel port.
 377
 378 config ARCH_EP93XX
 379         bool "EP93xx-based"
 380         select ARCH_HAS_HOLES_MEMORYMODEL
 381         select ARM_AMBA
 382         select ARM_PATCH_PHYS_VIRT
 383         select ARM_VIC
 384         select AUTO_ZRELADDR
 385         select CLKDEV_LOOKUP
 386         select CLKSRC_MMIO
 387         select CPU_ARM920T
 388         select GENERIC_CLOCKEVENTS
 389         select GPIOLIB
 390         help
 391           This enables support for the Cirrus EP93xx series of CPUs.
 392
 393 config ARCH_FOOTBRIDGE
 394         bool "FootBridge"
 395         select CPU_SA110
 396         select FOOTBRIDGE
 397         select GENERIC_CLOCKEVENTS
 398         select HAVE_IDE
 399         select NEED_MACH_IO_H if !MMU
 400         select NEED_MACH_MEMORY_H
 401         help
 402           Support for systems based on the DC21285 companion chip
 403           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
 404
 405 config ARCH_NETX
 406         bool "Hilscher NetX based"
 407         select ARM_VIC
 408         select CLKSRC_MMIO
 409         select CPU_ARM926T
 410         select GENERIC_CLOCKEVENTS
 411         help
 412           This enables support for systems based on the Hilscher NetX Soc
 413
 414 config ARCH_IOP13XX
 415         bool "IOP13xx-based"
 416         depends on MMU
 417         select CPU_XSC3
 418         select NEED_MACH_MEMORY_H
 419         select NEED_RET_TO_USER
 420         select PCI
 421         select PLAT_IOP
 422         select VMSPLIT_1G
 423         select SPARSE_IRQ
 424         help
 425           Support for Intel's IOP13XX (XScale) family of processors.
 426
 427 config ARCH_IOP32X
 428         bool "IOP32x-based"
 429         depends on MMU
 430         select CPU_XSCALE
 431         select GPIO_IOP
 432         select GPIOLIB
 433         select NEED_RET_TO_USER
 434         select PCI
 435         select PLAT_IOP
 436         help
 437           Support for Intel's 80219 and IOP32X (XScale) family of
 438           processors.
 439
 440 config ARCH_IOP33X
 441         bool "IOP33x-based"
 442         depends on MMU
 443         select CPU_XSCALE
 444         select GPIO_IOP
 445         select GPIOLIB
 446         select NEED_RET_TO_USER
 447         select PCI
 448         select PLAT_IOP
 449         help
 450           Support for Intel's IOP33X (XScale) family of processors.
 451
 452 config ARCH_IXP4XX
 453         bool "IXP4xx-based"
 454         depends on MMU
 455         select ARCH_HAS_DMA_SET_COHERENT_MASK
 456         select ARCH_SUPPORTS_BIG_ENDIAN
 457         select CLKSRC_MMIO
 458         select CPU_XSCALE
 459         select DMABOUNCE if PCI
 460         select GENERIC_CLOCKEVENTS
 461         select GPIOLIB
 462         select MIGHT_HAVE_PCI
 463         select NEED_MACH_IO_H
 464         select USB_EHCI_BIG_ENDIAN_DESC
 465         select USB_EHCI_BIG_ENDIAN_MMIO
 466         help
 467           Support for Intel's IXP4XX (XScale) family of processors.
 468
 469 config ARCH_DOVE
 470         bool "Marvell Dove"
 471         select CPU_PJ4
 472         select GENERIC_CLOCKEVENTS
 473         select GPIOLIB
 474         select MIGHT_HAVE_PCI
 475         select MULTI_IRQ_HANDLER
 476         select MVEBU_MBUS
 477         select PINCTRL
 478         select PINCTRL_DOVE
 479         select PLAT_ORION_LEGACY
 480         select SPARSE_IRQ
 481         select PM_GENERIC_DOMAINS if PM
 482         help
 483           Support for the Marvell Dove SoC 88AP510
 484
 485 config ARCH_KS8695
 486         bool "Micrel/Kendin KS8695"
 487         select CLKSRC_MMIO
 488         select CPU_ARM922T
 489         select GENERIC_CLOCKEVENTS
 490         select GPIOLIB
 491         select NEED_MACH_MEMORY_H
 492         help
 493           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 494           System-on-Chip devices.
 495
 496 config ARCH_W90X900
 497         bool "Nuvoton W90X900 CPU"
 498         select CLKDEV_LOOKUP
 499         select CLKSRC_MMIO
 500         select CPU_ARM926T
 501         select GENERIC_CLOCKEVENTS
 502         select GPIOLIB
 503         help
 504           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
 505           At present, the w90x900 has been renamed nuc900, regarding
 506           the ARM series product line, you can login the following
 507           link address to know more.
 508
 509           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
 510                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 511
 512 config ARCH_LPC32XX
 513         bool "NXP LPC32XX"
 514         select ARM_AMBA
 515         select CLKDEV_LOOKUP
 516         select CLKSRC_LPC32XX
 517         select COMMON_CLK
 518         select CPU_ARM926T
 519         select GENERIC_CLOCKEVENTS
 520         select GPIOLIB
 521         select MULTI_IRQ_HANDLER
 522         select SPARSE_IRQ
 523         select USE_OF
 524         help
 525           Support for the NXP LPC32XX family of processors
 526
 527 config ARCH_PXA
 528         bool "PXA2xx/PXA3xx-based"
 529         depends on MMU
 530         select ARCH_MTD_XIP
 531         select ARM_CPU_SUSPEND if PM
 532         select AUTO_ZRELADDR
 533         select COMMON_CLK
 534         select CLKDEV_LOOKUP
 535         select CLKSRC_PXA
 536         select CLKSRC_MMIO
 537         select CLKSRC_OF
 538         select CPU_XSCALE if !CPU_XSC3
 539         select GENERIC_CLOCKEVENTS
 540         select GPIO_PXA
 541         select GPIOLIB
 542         select HAVE_IDE
 543         select IRQ_DOMAIN
 544         select MULTI_IRQ_HANDLER
 545         select PLAT_PXA
 546         select SPARSE_IRQ
 547         help
 548           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 549
 550 config ARCH_RPC
 551         bool "RiscPC"
 552         depends on MMU
 553         select ARCH_ACORN
 554         select ARCH_MAY_HAVE_PC_FDC
 555         select ARCH_SPARSEMEM_ENABLE
 556         select ARCH_USES_GETTIMEOFFSET
 557         select CPU_SA110
 558         select FIQ
 559         select HAVE_IDE
 560         select HAVE_PATA_PLATFORM
 561         select ISA_DMA_API
 562         select NEED_MACH_IO_H
 563         select NEED_MACH_MEMORY_H
 564         select NO_IOPORT_MAP
 565         help
 566           On the Acorn Risc-PC, Linux can support the internal IDE disk and
 567           CD-ROM interface, serial and parallel port, and the floppy drive.
 568
 569 config ARCH_SA1100
 570         bool "SA1100-based"
 571         select ARCH_MTD_XIP
 572         select ARCH_SPARSEMEM_ENABLE
 573         select CLKDEV_LOOKUP
 574         select CLKSRC_MMIO
 575         select CLKSRC_PXA
 576         select CLKSRC_OF if OF
 577         select CPU_FREQ
 578         select CPU_SA1100
 579         select GENERIC_CLOCKEVENTS
 580         select GPIOLIB
 581         select HAVE_IDE
 582         select IRQ_DOMAIN
 583         select ISA
 584         select MULTI_IRQ_HANDLER
 585         select NEED_MACH_MEMORY_H
 586         select SPARSE_IRQ
 587         help
 588           Support for StrongARM 11x0 based boards.
 589
 590 config ARCH_S3C24XX
 591         bool "Samsung S3C24XX SoCs"
 592         select ATAGS
 593         select CLKDEV_LOOKUP
 594         select CLKSRC_SAMSUNG_PWM
 595         select GENERIC_CLOCKEVENTS
 596         select GPIO_SAMSUNG
 597         select GPIOLIB
 598         select HAVE_S3C2410_I2C if I2C
 599         select HAVE_S3C2410_WATCHDOG if WATCHDOG
 600         select HAVE_S3C_RTC if RTC_CLASS
 601         select MULTI_IRQ_HANDLER
 602         select NEED_MACH_IO_H
 603         select SAMSUNG_ATAGS
 604         help
 605           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
 606           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
 607           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
 608           Samsung SMDK2410 development board (and derivatives).
 609
 610 config ARCH_DAVINCI
 611         bool "TI DaVinci"
 612         select ARCH_HAS_HOLES_MEMORYMODEL
 613         select CLKDEV_LOOKUP
 614         select CPU_ARM926T
 615         select GENERIC_ALLOCATOR
 616         select GENERIC_CLOCKEVENTS
 617         select GENERIC_IRQ_CHIP
 618         select GPIOLIB
 619         select HAVE_IDE
 620         select USE_OF
 621         select ZONE_DMA
 622         help
 623           Support for TI's DaVinci platform.
 624
 625 config ARCH_OMAP1
 626         bool "TI OMAP1"
 627         depends on MMU
 628         select ARCH_HAS_HOLES_MEMORYMODEL
 629         select ARCH_OMAP
 630         select CLKDEV_LOOKUP
 631         select CLKSRC_MMIO
 632         select GENERIC_CLOCKEVENTS
 633         select GENERIC_IRQ_CHIP
 634         select GPIOLIB
 635         select HAVE_IDE
 636         select IRQ_DOMAIN
 637         select MULTI_IRQ_HANDLER
 638         select NEED_MACH_IO_H if PCCARD
 639         select NEED_MACH_MEMORY_H
 640         select SPARSE_IRQ
 641         help
 642           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
 643
 644 endchoice
 645
 646 menu "Multiple platform selection"
 647         depends on ARCH_MULTIPLATFORM
 648
 649 comment "CPU Core family selection"
 650
 651 config ARCH_MULTI_V4
 652         bool "ARMv4 based platforms (FA526)"
 653         depends on !ARCH_MULTI_V6_V7
 654         select ARCH_MULTI_V4_V5
 655         select CPU_FA526
 656
 657 config ARCH_MULTI_V4T
 658         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
 659         depends on !ARCH_MULTI_V6_V7
 660         select ARCH_MULTI_V4_V5
 661         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
 662                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
 663                 CPU_ARM925T || CPU_ARM940T)
 664
 665 config ARCH_MULTI_V5
 666         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
 667         depends on !ARCH_MULTI_V6_V7
 668         select ARCH_MULTI_V4_V5
 669         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
 670                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 671                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
 672
 673 config ARCH_MULTI_V4_V5
 674         bool
 675
 676 config ARCH_MULTI_V6
 677         bool "ARMv6 based platforms (ARM11)"
 678         select ARCH_MULTI_V6_V7
 679         select CPU_V6K
 680
 681 config ARCH_MULTI_V7
 682         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 683         default y
 684         select ARCH_MULTI_V6_V7
 685         select CPU_V7
 686         select HAVE_SMP
 687
 688 config ARCH_MULTI_V6_V7
 689         bool
 690         select MIGHT_HAVE_CACHE_L2X0
 691
 692 config ARCH_MULTI_CPU_AUTO
 693         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
 694         select ARCH_MULTI_V5
 695
 696 endmenu
 697
 698 config ARCH_VIRT
 699         bool "Dummy Virtual Machine"
 700         depends on ARCH_MULTI_V7
 701         select ARM_AMBA
 702         select ARM_GIC
 703         select ARM_GIC_V2M if PCI
 704         select ARM_GIC_V3
 705         select ARM_PSCI
 706         select HAVE_ARM_ARCH_TIMER
 707
 708 #
 709 # This is sorted alphabetically by mach-* pathname.  However, plat-*
 710 # Kconfigs may be included either alphabetically (according to the
 711 # plat- suffix) or along side the corresponding mach-* source.
 712 #
 713 source "arch/arm/mach-mvebu/Kconfig"
 714
 715 source "arch/arm/mach-alpine/Kconfig"
 716
 717 source "arch/arm/mach-artpec/Kconfig"
 718
 719 source "arch/arm/mach-asm9260/Kconfig"
 720
 721 source "arch/arm/mach-at91/Kconfig"
 722
 723 source "arch/arm/mach-axxia/Kconfig"
 724
 725 source "arch/arm/mach-bcm/Kconfig"
 726
 727 source "arch/arm/mach-berlin/Kconfig"
 728
 729 source "arch/arm/mach-clps711x/Kconfig"
 730
 731 source "arch/arm/mach-cns3xxx/Kconfig"
 732
 733 source "arch/arm/mach-davinci/Kconfig"
 734
 735 source "arch/arm/mach-digicolor/Kconfig"
 736
 737 source "arch/arm/mach-dove/Kconfig"
 738
 739 source "arch/arm/mach-ep93xx/Kconfig"
 740
 741 source "arch/arm/mach-footbridge/Kconfig"
 742
 743 source "arch/arm/mach-gemini/Kconfig"
 744
 745 source "arch/arm/mach-highbank/Kconfig"
 746
 747 source "arch/arm/mach-hisi/Kconfig"
 748
 749 source "arch/arm/mach-integrator/Kconfig"
 750
 751 source "arch/arm/mach-iop32x/Kconfig"
 752
 753 source "arch/arm/mach-iop33x/Kconfig"
 754
 755 source "arch/arm/mach-iop13xx/Kconfig"
 756
 757 source "arch/arm/mach-ixp4xx/Kconfig"
 758
 759 source "arch/arm/mach-keystone/Kconfig"
 760
 761 source "arch/arm/mach-ks8695/Kconfig"
 762
 763 source "arch/arm/mach-meson/Kconfig"
 764
 765 source "arch/arm/mach-moxart/Kconfig"
 766
 767 source "arch/arm/mach-aspeed/Kconfig"
 768
 769 source "arch/arm/mach-mv78xx0/Kconfig"
 770
 771 source "arch/arm/mach-imx/Kconfig"
 772
 773 source "arch/arm/mach-mediatek/Kconfig"
 774
 775 source "arch/arm/mach-mxs/Kconfig"
 776
 777 source "arch/arm/mach-netx/Kconfig"
 778
 779 source "arch/arm/mach-nomadik/Kconfig"
 780
 781 source "arch/arm/mach-nspire/Kconfig"
 782
 783 source "arch/arm/plat-omap/Kconfig"
 784
 785 source "arch/arm/mach-omap1/Kconfig"
 786
 787 source "arch/arm/mach-omap2/Kconfig"
 788
 789 source "arch/arm/mach-orion5x/Kconfig"
 790
 791 source "arch/arm/mach-picoxcell/Kconfig"
 792
 793 source "arch/arm/mach-pxa/Kconfig"
 794 source "arch/arm/plat-pxa/Kconfig"
 795
 796 source "arch/arm/mach-mmp/Kconfig"
 797
 798 source "arch/arm/mach-oxnas/Kconfig"
 799
 800 source "arch/arm/mach-qcom/Kconfig"
 801
 802 source "arch/arm/mach-realview/Kconfig"
 803
 804 source "arch/arm/mach-rockchip/Kconfig"
 805
 806 source "arch/arm/mach-sa1100/Kconfig"
 807
 808 source "arch/arm/mach-socfpga/Kconfig"
 809
 810 source "arch/arm/mach-spear/Kconfig"
 811
 812 source "arch/arm/mach-sti/Kconfig"
 813
 814 source "arch/arm/mach-s3c24xx/Kconfig"
 815
 816 source "arch/arm/mach-s3c64xx/Kconfig"
 817
 818 source "arch/arm/mach-s5pv210/Kconfig"
 819
 820 source "arch/arm/mach-exynos/Kconfig"
 821 source "arch/arm/plat-samsung/Kconfig"
 822
 823 source "arch/arm/mach-shmobile/Kconfig"
 824
 825 source "arch/arm/mach-sunxi/Kconfig"
 826
 827 source "arch/arm/mach-prima2/Kconfig"
 828
 829 source "arch/arm/mach-tango/Kconfig"
 830
 831 source "arch/arm/mach-tegra/Kconfig"
 832
 833 source "arch/arm/mach-u300/Kconfig"
 834
 835 source "arch/arm/mach-uniphier/Kconfig"
 836
 837 source "arch/arm/mach-ux500/Kconfig"
 838
 839 source "arch/arm/mach-versatile/Kconfig"
 840
 841 source "arch/arm/mach-vexpress/Kconfig"
 842 source "arch/arm/plat-versatile/Kconfig"
 843
 844 source "arch/arm/mach-vt8500/Kconfig"
 845
 846 source "arch/arm/mach-w90x900/Kconfig"
 847
 848 source "arch/arm/mach-zx/Kconfig"
 849
 850 source "arch/arm/mach-zynq/Kconfig"
 851
 852 # ARMv7-M architecture
 853 config ARCH_EFM32
 854         bool "Energy Micro efm32"
 855         depends on ARM_SINGLE_ARMV7M
 856         select GPIOLIB
 857         help
 858           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
 859           processors.
 860
 861 config ARCH_LPC18XX
 862         bool "NXP LPC18xx/LPC43xx"
 863         depends on ARM_SINGLE_ARMV7M
 864         select ARCH_HAS_RESET_CONTROLLER
 865         select ARM_AMBA
 866         select CLKSRC_LPC32XX
 867         select PINCTRL
 868         help
 869           Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
 870           high performance microcontrollers.
 871
 872 config ARCH_STM32
 873         bool "STMicrolectronics STM32"
 874         depends on ARM_SINGLE_ARMV7M
 875         select ARCH_HAS_RESET_CONTROLLER
 876         select ARMV7M_SYSTICK
 877         select CLKSRC_STM32
 878         select PINCTRL
 879         select RESET_CONTROLLER
 880         help
 881           Support for STMicroelectronics STM32 processors.
 882
 883 config MACH_STM32F429
 884         bool "STMicrolectronics STM32F429"
 885         depends on ARCH_STM32
 886         default y
 887
 888 config ARCH_MPS2
 889         bool "ARM MPS2 platform"
 890         depends on ARM_SINGLE_ARMV7M
 891         select ARM_AMBA
 892         select CLKSRC_MPS2
 893         help
 894           Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
 895           with a range of available cores like Cortex-M3/M4/M7.
 896
 897           Please, note that depends which Application Note is used memory map
 898           for the platform may vary, so adjustment of RAM base might be needed.
 899
 900 # Definitions to make life easier
 901 config ARCH_ACORN
 902         bool
 903
 904 config PLAT_IOP
 905         bool
 906         select GENERIC_CLOCKEVENTS
 907
 908 config PLAT_ORION
 909         bool
 910         select CLKSRC_MMIO
 911         select COMMON_CLK
 912         select GENERIC_IRQ_CHIP
 913         select IRQ_DOMAIN
 914
 915 config PLAT_ORION_LEGACY
 916         bool
 917         select PLAT_ORION
 918
 919 config PLAT_PXA
 920         bool
 921
 922 config PLAT_VERSATILE
 923         bool
 924
 925 source "arch/arm/firmware/Kconfig"
 926
 927 source arch/arm/mm/Kconfig
 928
 929 config IWMMXT
 930         bool "Enable iWMMXt support"
 931         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
 932         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
 933         help
 934           Enable support for iWMMXt context switching at run time if
 935           running on a CPU that supports it.
 936
 937 config MULTI_IRQ_HANDLER
 938         bool
 939         help
 940           Allow each machine to specify it's own IRQ handler at run time.
 941
 942 if !MMU
 943 source "arch/arm/Kconfig-nommu"
 944 endif
 945
 946 config PJ4B_ERRATA_4742
 947         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
 948         depends on CPU_PJ4B && MACH_ARMADA_370
 949         default y
 950         help
 951           When coming out of either a Wait for Interrupt (WFI) or a Wait for
 952           Event (WFE) IDLE states, a specific timing sensitivity exists between
 953           the retiring WFI/WFE instructions and the newly issued subsequent
 954           instructions.  This sensitivity can result in a CPU hang scenario.
 955           Workaround:
 956           The software must insert either a Data Synchronization Barrier (DSB)
 957           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
 958           instruction
 959
 960 config ARM_ERRATA_326103
 961         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
 962         depends on CPU_V6
 963         help
 964           Executing a SWP instruction to read-only memory does not set bit 11
 965           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
 966           treat the access as a read, preventing a COW from occurring and
 967           causing the faulting task to livelock.
 968
 969 config ARM_ERRATA_411920
 970         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
 971         depends on CPU_V6 || CPU_V6K
 972         help
 973           Invalidation of the Instruction Cache operation can
 974           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
 975           It does not affect the MPCore. This option enables the ARM Ltd.
 976           recommended workaround.
 977
 978 config ARM_ERRATA_430973
 979         bool "ARM errata: Stale prediction on replaced interworking branch"
 980         depends on CPU_V7
 981         help
 982           This option enables the workaround for the 430973 Cortex-A8
 983           r1p* erratum. If a code sequence containing an ARM/Thumb
 984           interworking branch is replaced with another code sequence at the
 985           same virtual address, whether due to self-modifying code or virtual
 986           to physical address re-mapping, Cortex-A8 does not recover from the
 987           stale interworking branch prediction. This results in Cortex-A8
 988           executing the new code sequence in the incorrect ARM or Thumb state.
 989           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
 990           and also flushes the branch target cache at every context switch.
 991           Note that setting specific bits in the ACTLR register may not be
 992           available in non-secure mode.
 993
 994 config ARM_ERRATA_458693
 995         bool "ARM errata: Processor deadlock when a false hazard is created"
 996         depends on CPU_V7
 997         depends on !ARCH_MULTIPLATFORM
 998         help
 999           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1000           erratum. For very specific sequences of memory operations, it is
1001           possible for a hazard condition intended for a cache line to instead
1002           be incorrectly associated with a different cache line. This false
1003           hazard might then cause a processor deadlock. The workaround enables
1004           the L1 caching of the NEON accesses and disables the PLD instruction
1005           in the ACTLR register. Note that setting specific bits in the ACTLR
1006           register may not be available in non-secure mode.
1007
1008 config ARM_ERRATA_460075
1009         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1010         depends on CPU_V7
1011         depends on !ARCH_MULTIPLATFORM
1012         help
1013           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1014           erratum. Any asynchronous access to the L2 cache may encounter a
1015           situation in which recent store transactions to the L2 cache are lost
1016           and overwritten with stale memory contents from external memory. The
1017           workaround disables the write-allocate mode for the L2 cache via the
1018           ACTLR register. Note that setting specific bits in the ACTLR register
1019           may not be available in non-secure mode.
1020
1021 config ARM_ERRATA_742230
1022         bool "ARM errata: DMB operation may be faulty"
1023         depends on CPU_V7 && SMP
1024         depends on !ARCH_MULTIPLATFORM
1025         help
1026           This option enables the workaround for the 742230 Cortex-A9
1027           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1028           between two write operations may not ensure the correct visibility
1029           ordering of the two writes. This workaround sets a specific bit in
1030           the diagnostic register of the Cortex-A9 which causes the DMB
1031           instruction to behave as a DSB, ensuring the correct behaviour of
1032           the two writes.
1033
1034 config ARM_ERRATA_742231
1035         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1036         depends on CPU_V7 && SMP
1037         depends on !ARCH_MULTIPLATFORM
1038         help
1039           This option enables the workaround for the 742231 Cortex-A9
1040           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1041           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1042           accessing some data located in the same cache line, may get corrupted
1043           data due to bad handling of the address hazard when the line gets
1044           replaced from one of the CPUs at the same time as another CPU is
1045           accessing it. This workaround sets specific bits in the diagnostic
1046           register of the Cortex-A9 which reduces the linefill issuing
1047           capabilities of the processor.
1048
1049 config ARM_ERRATA_643719
1050         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1051         depends on CPU_V7 && SMP
1052         default y
1053         help
1054           This option enables the workaround for the 643719 Cortex-A9 (prior to
1055           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1056           register returns zero when it should return one. The workaround
1057           corrects this value, ensuring cache maintenance operations which use
1058           it behave as intended and avoiding data corruption.
1059
1060 config ARM_ERRATA_720789
1061         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1062         depends on CPU_V7
1063         help
1064           This option enables the workaround for the 720789 Cortex-A9 (prior to
1065           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1066           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1067           As a consequence of this erratum, some TLB entries which should be
1068           invalidated are not, resulting in an incoherency in the system page
1069           tables. The workaround changes the TLB flushing routines to invalidate
1070           entries regardless of the ASID.
1071
1072 config ARM_ERRATA_743622
1073         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1074         depends on CPU_V7
1075         depends on !ARCH_MULTIPLATFORM
1076         help
1077           This option enables the workaround for the 743622 Cortex-A9
1078           (r2p*) erratum. Under very rare conditions, a faulty
1079           optimisation in the Cortex-A9 Store Buffer may lead to data
1080           corruption. This workaround sets a specific bit in the diagnostic
1081           register of the Cortex-A9 which disables the Store Buffer
1082           optimisation, preventing the defect from occurring. This has no
1083           visible impact on the overall performance or power consumption of the
1084           processor.
1085
1086 config ARM_ERRATA_751472
1087         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1088         depends on CPU_V7
1089         depends on !ARCH_MULTIPLATFORM
1090         help
1091           This option enables the workaround for the 751472 Cortex-A9 (prior
1092           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1093           completion of a following broadcasted operation if the second
1094           operation is received by a CPU before the ICIALLUIS has completed,
1095           potentially leading to corrupted entries in the cache or TLB.
1096
1097 config ARM_ERRATA_754322
1098         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1099         depends on CPU_V7
1100         help
1101           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1102           r3p*) erratum. A speculative memory access may cause a page table walk
1103           which starts prior to an ASID switch but completes afterwards. This
1104           can populate the micro-TLB with a stale entry which may be hit with
1105           the new ASID. This workaround places two dsb instructions in the mm
1106           switching code so that no page table walks can cross the ASID switch.
1107
1108 config ARM_ERRATA_754327
1109         bool "ARM errata: no automatic Store Buffer drain"
1110         depends on CPU_V7 && SMP
1111         help
1112           This option enables the workaround for the 754327 Cortex-A9 (prior to
1113           r2p0) erratum. The Store Buffer does not have any automatic draining
1114           mechanism and therefore a livelock may occur if an external agent
1115           continuously polls a memory location waiting to observe an update.
1116           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1117           written polling loops from denying visibility of updates to memory.
1118
1119 config ARM_ERRATA_364296
1120         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1121         depends on CPU_V6
1122         help
1123           This options enables the workaround for the 364296 ARM1136
1124           r0p2 erratum (possible cache data corruption with
1125           hit-under-miss enabled). It sets the undocumented bit 31 in
1126           the auxiliary control register and the FI bit in the control
1127           register, thus disabling hit-under-miss without putting the
1128           processor into full low interrupt latency mode. ARM11MPCore
1129           is not affected.
1130
1131 config ARM_ERRATA_764369
1132         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1133         depends on CPU_V7 && SMP
1134         help
1135           This option enables the workaround for erratum 764369
1136           affecting Cortex-A9 MPCore with two or more processors (all
1137           current revisions). Under certain timing circumstances, a data
1138           cache line maintenance operation by MVA targeting an Inner
1139           Shareable memory region may fail to proceed up to either the
1140           Point of Coherency or to the Point of Unification of the
1141           system. This workaround adds a DSB instruction before the
1142           relevant cache maintenance functions and sets a specific bit
1143           in the diagnostic control register of the SCU.
1144
1145 config ARM_ERRATA_775420
1146        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1147        depends on CPU_V7
1148        help
1149          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1150          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1151          operation aborts with MMU exception, it might cause the processor
1152          to deadlock. This workaround puts DSB before executing ISB if
1153          an abort may occur on cache maintenance.
1154
1155 config ARM_ERRATA_798181
1156         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1157         depends on CPU_V7 && SMP
1158         help
1159           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1160           adequately shooting down all use of the old entries. This
1161           option enables the Linux kernel workaround for this erratum
1162           which sends an IPI to the CPUs that are running the same ASID
1163           as the one being invalidated.
1164
1165 config ARM_ERRATA_773022
1166         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1167         depends on CPU_V7
1168         help
1169           This option enables the workaround for the 773022 Cortex-A15
1170           (up to r0p4) erratum. In certain rare sequences of code, the
1171           loop buffer may deliver incorrect instructions. This
1172           workaround disables the loop buffer to avoid the erratum.
1173
1174 config ARM_ERRATA_818325_852422
1175         bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1176         depends on CPU_V7
1177         help
1178           This option enables the workaround for:
1179           - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1180             instruction might deadlock.  Fixed in r0p1.
1181           - Cortex-A12 852422: Execution of a sequence of instructions might
1182             lead to either a data corruption or a CPU deadlock.  Not fixed in
1183             any Cortex-A12 cores yet.
1184           This workaround for all both errata involves setting bit[12] of the
1185           Feature Register. This bit disables an optimisation applied to a
1186           sequence of 2 instructions that use opposing condition codes.
1187
1188 config ARM_ERRATA_821420
1189         bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1190         depends on CPU_V7
1191         help
1192           This option enables the workaround for the 821420 Cortex-A12
1193           (all revs) erratum. In very rare timing conditions, a sequence
1194           of VMOV to Core registers instructions, for which the second
1195           one is in the shadow of a branch or abort, can lead to a
1196           deadlock when the VMOV instructions are issued out-of-order.
1197
1198 config ARM_ERRATA_825619
1199         bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1200         depends on CPU_V7
1201         help
1202           This option enables the workaround for the 825619 Cortex-A12
1203           (all revs) erratum. Within rare timing constraints, executing a
1204           DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1205           and Device/Strongly-Ordered loads and stores might cause deadlock
1206
1207 config ARM_ERRATA_852421
1208         bool "ARM errata: A17: DMB ST might fail to create order between stores"
1209         depends on CPU_V7
1210         help
1211           This option enables the workaround for the 852421 Cortex-A17
1212           (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1213           execution of a DMB ST instruction might fail to properly order
1214           stores from GroupA and stores from GroupB.
1215
1216 config ARM_ERRATA_852423
1217         bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1218         depends on CPU_V7
1219         help
1220           This option enables the workaround for:
1221           - Cortex-A17 852423: Execution of a sequence of instructions might
1222             lead to either a data corruption or a CPU deadlock.  Not fixed in
1223             any Cortex-A17 cores yet.
1224           This is identical to Cortex-A12 erratum 852422.  It is a separate
1225           config option from the A12 erratum due to the way errata are checked
1226           for and handled.
1227
1228 endmenu
1229
1230 source "arch/arm/common/Kconfig"
1231
1232 menu "Bus support"
1233
1234 config ISA
1235         bool
1236         help
1237           Find out whether you have ISA slots on your motherboard.  ISA is the
1238           name of a bus system, i.e. the way the CPU talks to the other stuff
1239           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1240           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1241           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1242
1243 # Select ISA DMA controller support
1244 config ISA_DMA
1245         bool
1246         select ISA_DMA_API
1247
1248 # Select ISA DMA interface
1249 config ISA_DMA_API
1250         bool
1251
1252 config PCI
1253         bool "PCI support" if MIGHT_HAVE_PCI
1254         help
1255           Find out whether you have a PCI motherboard. PCI is the name of a
1256           bus system, i.e. the way the CPU talks to the other stuff inside
1257           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1258           VESA. If you have PCI, say Y, otherwise N.
1259
1260 config PCI_DOMAINS
1261         bool
1262         depends on PCI
1263
1264 config PCI_DOMAINS_GENERIC
1265         def_bool PCI_DOMAINS
1266
1267 config PCI_NANOENGINE
1268         bool "BSE nanoEngine PCI support"
1269         depends on SA1100_NANOENGINE
1270         help
1271           Enable PCI on the BSE nanoEngine board.
1272
1273 config PCI_SYSCALL
1274         def_bool PCI
1275
1276 config PCI_HOST_ITE8152
1277         bool
1278         depends on PCI && MACH_ARMCORE
1279         default y
1280         select DMABOUNCE
1281
1282 source "drivers/pci/Kconfig"
1283
1284 source "drivers/pcmcia/Kconfig"
1285
1286 endmenu
1287
1288 menu "Kernel Features"
1289
1290 config HAVE_SMP
1291         bool
1292         help
1293           This option should be selected by machines which have an SMP-
1294           capable CPU.
1295
1296           The only effect of this option is to make the SMP-related
1297           options available to the user for configuration.
1298
1299 config SMP
1300         bool "Symmetric Multi-Processing"
1301         depends on CPU_V6K || CPU_V7
1302         depends on GENERIC_CLOCKEVENTS
1303         depends on HAVE_SMP
1304         depends on MMU || ARM_MPU
1305         select IRQ_WORK
1306         help
1307           This enables support for systems with more than one CPU. If you have
1308           a system with only one CPU, say N. If you have a system with more
1309           than one CPU, say Y.
1310
1311           If you say N here, the kernel will run on uni- and multiprocessor
1312           machines, but will use only one CPU of a multiprocessor machine. If
1313           you say Y here, the kernel will run on many, but not all,
1314           uniprocessor machines. On a uniprocessor machine, the kernel
1315           will run faster if you say N here.
1316
1317           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1318           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1319           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1320
1321           If you don't know what to do here, say N.
1322
1323 config SMP_ON_UP
1324         bool "Allow booting SMP kernel on uniprocessor systems"
1325         depends on SMP && !XIP_KERNEL && MMU
1326         default y
1327         help
1328           SMP kernels contain instructions which fail on non-SMP processors.
1329           Enabling this option allows the kernel to modify itself to make
1330           these instructions safe.  Disabling it allows about 1K of space
1331           savings.
1332
1333           If you don't know what to do here, say Y.
1334
1335 config ARM_CPU_TOPOLOGY
1336         bool "Support cpu topology definition"
1337         depends on SMP && CPU_V7
1338         default y
1339         help
1340           Support ARM cpu topology definition. The MPIDR register defines
1341           affinity between processors which is then used to describe the cpu
1342           topology of an ARM System.
1343
1344 config SCHED_MC
1345         bool "Multi-core scheduler support"
1346         depends on ARM_CPU_TOPOLOGY
1347         help
1348           Multi-core scheduler support improves the CPU scheduler's decision
1349           making when dealing with multi-core CPU chips at a cost of slightly
1350           increased overhead in some places. If unsure say N here.
1351
1352 config SCHED_SMT
1353         bool "SMT scheduler support"
1354         depends on ARM_CPU_TOPOLOGY
1355         help
1356           Improves the CPU scheduler's decision making when dealing with
1357           MultiThreading at a cost of slightly increased overhead in some
1358           places. If unsure say N here.
1359
1360 config HAVE_ARM_SCU
1361         bool
1362         help
1363           This option enables support for the ARM system coherency unit
1364
1365 config HAVE_ARM_ARCH_TIMER
1366         bool "Architected timer support"
1367         depends on CPU_V7
1368         select ARM_ARCH_TIMER
1369         select GENERIC_CLOCKEVENTS
1370         help
1371           This option enables support for the ARM architected timer
1372
1373 config HAVE_ARM_TWD
1374         bool
1375         select CLKSRC_OF if OF
1376         help
1377           This options enables support for the ARM timer and watchdog unit
1378
1379 config MCPM
1380         bool "Multi-Cluster Power Management"
1381         depends on CPU_V7 && SMP
1382         help
1383           This option provides the common power management infrastructure
1384           for (multi-)cluster based systems, such as big.LITTLE based
1385           systems.
1386
1387 config MCPM_QUAD_CLUSTER
1388         bool
1389         depends on MCPM
1390         help
1391           To avoid wasting resources unnecessarily, MCPM only supports up
1392           to 2 clusters by default.
1393           Platforms with 3 or 4 clusters that use MCPM must select this
1394           option to allow the additional clusters to be managed.
1395
1396 config BIG_LITTLE
1397         bool "big.LITTLE support (Experimental)"
1398         depends on CPU_V7 && SMP
1399         select MCPM
1400         help
1401           This option enables support selections for the big.LITTLE
1402           system architecture.
1403
1404 config BL_SWITCHER
1405         bool "big.LITTLE switcher support"
1406         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1407         select CPU_PM
1408         help
1409           The big.LITTLE "switcher" provides the core functionality to
1410           transparently handle transition between a cluster of A15's
1411           and a cluster of A7's in a big.LITTLE system.
1412
1413 config BL_SWITCHER_DUMMY_IF
1414         tristate "Simple big.LITTLE switcher user interface"
1415         depends on BL_SWITCHER && DEBUG_KERNEL
1416         help
1417           This is a simple and dummy char dev interface to control
1418           the big.LITTLE switcher core code.  It is meant for
1419           debugging purposes only.
1420
1421 choice
1422         prompt "Memory split"
1423         depends on MMU
1424         default VMSPLIT_3G
1425         help
1426           Select the desired split between kernel and user memory.
1427
1428           If you are not absolutely sure what you are doing, leave this
1429           option alone!
1430
1431         config VMSPLIT_3G
1432                 bool "3G/1G user/kernel split"
1433         config VMSPLIT_3G_OPT
1434                 bool "3G/1G user/kernel split (for full 1G low memory)"
1435         config VMSPLIT_2G
1436                 bool "2G/2G user/kernel split"
1437         config VMSPLIT_1G
1438                 bool "1G/3G user/kernel split"
1439 endchoice
1440
1441 config PAGE_OFFSET
1442         hex
1443         default PHYS_OFFSET if !MMU
1444         default 0x40000000 if VMSPLIT_1G
1445         default 0x80000000 if VMSPLIT_2G
1446         default 0xB0000000 if VMSPLIT_3G_OPT
1447         default 0xC0000000
1448
1449 config NR_CPUS
1450         int "Maximum number of CPUs (2-32)"
1451         range 2 32
1452         depends on SMP
1453         default "4"
1454
1455 config HOTPLUG_CPU
1456         bool "Support for hot-pluggable CPUs"
1457         depends on SMP
1458         help
1459           Say Y here to experiment with turning CPUs off and on.  CPUs
1460           can be controlled through /sys/devices/system/cpu.
1461
1462 config ARM_PSCI
1463         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1464         depends on HAVE_ARM_SMCCC
1465         select ARM_PSCI_FW
1466         help
1467           Say Y here if you want Linux to communicate with system firmware
1468           implementing the PSCI specification for CPU-centric power
1469           management operations described in ARM document number ARM DEN
1470           0022A ("Power State Coordination Interface System Software on
1471           ARM processors").
1472
1473 # The GPIO number here must be sorted by descending number. In case of
1474 # a multiplatform kernel, we just want the highest value required by the
1475 # selected platforms.
1476 config ARCH_NR_GPIO
1477         int
1478         default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1479                 ARCH_ZYNQ
1480         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1481                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1482         default 416 if ARCH_SUNXI
1483         default 392 if ARCH_U8500
1484         default 352 if ARCH_VT8500
1485         default 288 if ARCH_ROCKCHIP
1486         default 264 if MACH_H4700
1487         default 0
1488         help
1489           Maximum number of GPIOs in the system.
1490
1491           If unsure, leave the default value.
1492
1493 source kernel/Kconfig.preempt
1494
1495 config HZ_FIXED
1496         int
1497         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1498                 ARCH_S5PV210 || ARCH_EXYNOS4
1499         default 128 if SOC_AT91RM9200
1500         default 0
1501
1502 choice
1503         depends on HZ_FIXED = 0
1504         prompt "Timer frequency"
1505
1506 config HZ_100
1507         bool "100 Hz"
1508
1509 config HZ_200
1510         bool "200 Hz"
1511
1512 config HZ_250
1513         bool "250 Hz"
1514
1515 config HZ_300
1516         bool "300 Hz"
1517
1518 config HZ_500
1519         bool "500 Hz"
1520
1521 config HZ_1000
1522         bool "1000 Hz"
1523
1524 endchoice
1525
1526 config HZ
1527         int
1528         default HZ_FIXED if HZ_FIXED != 0
1529         default 100 if HZ_100
1530         default 200 if HZ_200
1531         default 250 if HZ_250
1532         default 300 if HZ_300
1533         default 500 if HZ_500
1534         default 1000
1535
1536 config SCHED_HRTICK
1537         def_bool HIGH_RES_TIMERS
1538
1539 config THUMB2_KERNEL
1540         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1541         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1542         default y if CPU_THUMBONLY
1543         select AEABI
1544         select ARM_ASM_UNIFIED
1545         select ARM_UNWIND
1546         help
1547           By enabling this option, the kernel will be compiled in
1548           Thumb-2 mode. A compiler/assembler that understand the unified
1549           ARM-Thumb syntax is needed.
1550
1551           If unsure, say N.
1552
1553 config THUMB2_AVOID_R_ARM_THM_JUMP11
1554         bool "Work around buggy Thumb-2 short branch relocations in gas"
1555         depends on THUMB2_KERNEL && MODULES
1556         default y
1557         help
1558           Various binutils versions can resolve Thumb-2 branches to
1559           locally-defined, preemptible global symbols as short-range "b.n"
1560           branch instructions.
1561
1562           This is a problem, because there's no guarantee the final
1563           destination of the symbol, or any candidate locations for a
1564           trampoline, are within range of the branch.  For this reason, the
1565           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1566           relocation in modules at all, and it makes little sense to add
1567           support.
1568
1569           The symptom is that the kernel fails with an "unsupported
1570           relocation" error when loading some modules.
1571
1572           Until fixed tools are available, passing
1573           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1574           code which hits this problem, at the cost of a bit of extra runtime
1575           stack usage in some cases.
1576
1577           The problem is described in more detail at:
1578               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1579
1580           Only Thumb-2 kernels are affected.
1581
1582           Unless you are sure your tools don't have this problem, say Y.
1583
1584 config ARM_ASM_UNIFIED
1585         bool
1586
1587 config ARM_PATCH_IDIV
1588         bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1589         depends on CPU_32v7 && !XIP_KERNEL
1590         default y
1591         help
1592           The ARM compiler inserts calls to __aeabi_idiv() and
1593           __aeabi_uidiv() when it needs to perform division on signed
1594           and unsigned integers. Some v7 CPUs have support for the sdiv
1595           and udiv instructions that can be used to implement those
1596           functions.
1597
1598           Enabling this option allows the kernel to modify itself to
1599           replace the first two instructions of these library functions
1600           with the sdiv or udiv plus "bx lr" instructions when the CPU
1601           it is running on supports them. Typically this will be faster
1602           and less power intensive than running the original library
1603           code to do integer division.
1604
1605 config AEABI
1606         bool "Use the ARM EABI to compile the kernel"
1607         help
1608           This option allows for the kernel to be compiled using the latest
1609           ARM ABI (aka EABI).  This is only useful if you are using a user
1610           space environment that is also compiled with EABI.
1611
1612           Since there are major incompatibilities between the legacy ABI and
1613           EABI, especially with regard to structure member alignment, this
1614           option also changes the kernel syscall calling convention to
1615           disambiguate both ABIs and allow for backward compatibility support
1616           (selected with CONFIG_OABI_COMPAT).
1617
1618           To use this you need GCC version 4.0.0 or later.
1619
1620 config OABI_COMPAT
1621         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1622         depends on AEABI && !THUMB2_KERNEL
1623         help
1624           This option preserves the old syscall interface along with the
1625           new (ARM EABI) one. It also provides a compatibility layer to
1626           intercept syscalls that have structure arguments which layout
1627           in memory differs between the legacy ABI and the new ARM EABI
1628           (only for non "thumb" binaries). This option adds a tiny
1629           overhead to all syscalls and produces a slightly larger kernel.
1630
1631           The seccomp filter system will not be available when this is
1632           selected, since there is no way yet to sensibly distinguish
1633           between calling conventions during filtering.
1634
1635           If you know you'll be using only pure EABI user space then you
1636           can say N here. If this option is not selected and you attempt
1637           to execute a legacy ABI binary then the result will be
1638           UNPREDICTABLE (in fact it can be predicted that it won't work
1639           at all). If in doubt say N.
1640
1641 config ARCH_HAS_HOLES_MEMORYMODEL
1642         bool
1643
1644 config ARCH_SPARSEMEM_ENABLE
1645         bool
1646
1647 config ARCH_SPARSEMEM_DEFAULT
1648         def_bool ARCH_SPARSEMEM_ENABLE
1649
1650 config ARCH_SELECT_MEMORY_MODEL
1651         def_bool ARCH_SPARSEMEM_ENABLE
1652
1653 config HAVE_ARCH_PFN_VALID
1654         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1655
1656 config HAVE_GENERIC_RCU_GUP
1657         def_bool y
1658         depends on ARM_LPAE
1659
1660 config HIGHMEM
1661         bool "High Memory Support"
1662         depends on MMU
1663         help
1664           The address space of ARM processors is only 4 Gigabytes large
1665           and it has to accommodate user address space, kernel address
1666           space as well as some memory mapped IO. That means that, if you
1667           have a large amount of physical memory and/or IO, not all of the
1668           memory can be "permanently mapped" by the kernel. The physical
1669           memory that is not permanently mapped is called "high memory".
1670
1671           Depending on the selected kernel/user memory split, minimum
1672           vmalloc space and actual amount of RAM, you may not need this
1673           option which should result in a slightly faster kernel.
1674
1675           If unsure, say n.
1676
1677 config HIGHPTE
1678         bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1679         depends on HIGHMEM
1680         default y
1681         help
1682           The VM uses one page of physical memory for each page table.
1683           For systems with a lot of processes, this can use a lot of
1684           precious low memory, eventually leading to low memory being
1685           consumed by page tables.  Setting this option will allow
1686           user-space 2nd level page tables to reside in high memory.
1687
1688 config CPU_SW_DOMAIN_PAN
1689         bool "Enable use of CPU domains to implement privileged no-access"
1690         depends on MMU && !ARM_LPAE
1691         default y
1692         help
1693           Increase kernel security by ensuring that normal kernel accesses
1694           are unable to access userspace addresses.  This can help prevent
1695           use-after-free bugs becoming an exploitable privilege escalation
1696           by ensuring that magic values (such as LIST_POISON) will always
1697           fault when dereferenced.
1698
1699           CPUs with low-vector mappings use a best-efforts implementation.
1700           Their lower 1MB needs to remain accessible for the vectors, but
1701           the remainder of userspace will become appropriately inaccessible.
1702
1703 config HW_PERF_EVENTS
1704         def_bool y
1705         depends on ARM_PMU
1706
1707 config SYS_SUPPORTS_HUGETLBFS
1708        def_bool y
1709        depends on ARM_LPAE
1710
1711 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1712        def_bool y
1713        depends on ARM_LPAE
1714
1715 config ARCH_WANT_GENERAL_HUGETLB
1716         def_bool y
1717
1718 config ARM_MODULE_PLTS
1719         bool "Use PLTs to allow module memory to spill over into vmalloc area"
1720         depends on MODULES
1721         help
1722           Allocate PLTs when loading modules so that jumps and calls whose
1723           targets are too far away for their relative offsets to be encoded
1724           in the instructions themselves can be bounced via veneers in the
1725           module's PLT. This allows modules to be allocated in the generic
1726           vmalloc area after the dedicated module memory area has been
1727           exhausted. The modules will use slightly more memory, but after
1728           rounding up to page size, the actual memory footprint is usually
1729           the same.
1730
1731           Say y if you are getting out of memory errors while loading modules
1732
1733 source "mm/Kconfig"
1734
1735 config FORCE_MAX_ZONEORDER
1736         int "Maximum zone order"
1737         default "12" if SOC_AM33XX
1738         default "9" if SA1111 || ARCH_EFM32
1739         default "11"
1740         help
1741           The kernel memory allocator divides physically contiguous memory
1742           blocks into "zones", where each zone is a power of two number of
1743           pages.  This option selects the largest power of two that the kernel
1744           keeps in the memory allocator.  If you need to allocate very large
1745           blocks of physically contiguous memory, then you may need to
1746           increase this value.
1747
1748           This config option is actually maximum order plus one. For example,
1749           a value of 11 means that the largest free memory block is 2^10 pages.
1750
1751 config ALIGNMENT_TRAP
1752         bool
1753         depends on CPU_CP15_MMU
1754         default y if !ARCH_EBSA110
1755         select HAVE_PROC_CPU if PROC_FS
1756         help
1757           ARM processors cannot fetch/store information which is not
1758           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1759           address divisible by 4. On 32-bit ARM processors, these non-aligned
1760           fetch/store instructions will be emulated in software if you say
1761           here, which has a severe performance impact. This is necessary for
1762           correct operation of some network protocols. With an IP-only
1763           configuration it is safe to say N, otherwise say Y.
1764
1765 config UACCESS_WITH_MEMCPY
1766         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1767         depends on MMU
1768         default y if CPU_FEROCEON
1769         help
1770           Implement faster copy_to_user and clear_user methods for CPU
1771           cores where a 8-word STM instruction give significantly higher
1772           memory write throughput than a sequence of individual 32bit stores.
1773
1774           A possible side effect is a slight increase in scheduling latency
1775           between threads sharing the same address space if they invoke
1776           such copy operations with large buffers.
1777
1778           However, if the CPU data cache is using a write-allocate mode,
1779           this option is unlikely to provide any performance gain.
1780
1781 config SECCOMP
1782         bool
1783         prompt "Enable seccomp to safely compute untrusted bytecode"
1784         ---help---
1785           This kernel feature is useful for number crunching applications
1786           that may need to compute untrusted bytecode during their
1787           execution. By using pipes or other transports made available to
1788           the process as file descriptors supporting the read/write
1789           syscalls, it's possible to isolate those applications in
1790           their own address space using seccomp. Once seccomp is
1791           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1792           and the task is only allowed to execute a few safe syscalls
1793           defined by each seccomp mode.
1794
1795 config SWIOTLB
1796         def_bool y
1797
1798 config IOMMU_HELPER
1799         def_bool SWIOTLB
1800
1801 config PARAVIRT
1802         bool "Enable paravirtualization code"
1803         help
1804           This changes the kernel so it can modify itself when it is run
1805           under a hypervisor, potentially improving performance significantly
1806           over full virtualization.
1807
1808 config PARAVIRT_TIME_ACCOUNTING
1809         bool "Paravirtual steal time accounting"
1810         select PARAVIRT
1811         default n
1812         help
1813           Select this option to enable fine granularity task steal time
1814           accounting. Time spent executing other tasks in parallel with
1815           the current vCPU is discounted from the vCPU power. To account for
1816           that, there can be a small performance impact.
1817
1818           If in doubt, say N here.
1819
1820 config XEN_DOM0
1821         def_bool y
1822         depends on XEN
1823
1824 config XEN
1825         bool "Xen guest support on ARM"
1826         depends on ARM && AEABI && OF
1827         depends on CPU_V7 && !CPU_V6
1828         depends on !GENERIC_ATOMIC64
1829         depends on MMU
1830         select ARCH_DMA_ADDR_T_64BIT
1831         select ARM_PSCI
1832         select SWIOTLB_XEN
1833         select PARAVIRT
1834         help
1835           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1836
1837 endmenu
1838
1839 menu "Boot options"
1840
1841 config USE_OF
1842         bool "Flattened Device Tree support"
1843         select IRQ_DOMAIN
1844         select OF
1845         help
1846           Include support for flattened device tree machine descriptions.
1847
1848 config ATAGS
1849         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1850         default y
1851         help
1852           This is the traditional way of passing data to the kernel at boot
1853           time. If you are solely relying on the flattened device tree (or
1854           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1855           to remove ATAGS support from your kernel binary.  If unsure,
1856           leave this to y.
1857
1858 config DEPRECATED_PARAM_STRUCT
1859         bool "Provide old way to pass kernel parameters"
1860         depends on ATAGS
1861         help
1862           This was deprecated in 2001 and announced to live on for 5 years.
1863           Some old boot loaders still use this way.
1864
1865 # Compressed boot loader in ROM.  Yes, we really want to ask about
1866 # TEXT and BSS so we preserve their values in the config files.
1867 config ZBOOT_ROM_TEXT
1868         hex "Compressed ROM boot loader base address"
1869         default "0"
1870         help
1871           The physical address at which the ROM-able zImage is to be
1872           placed in the target.  Platforms which normally make use of
1873           ROM-able zImage formats normally set this to a suitable
1874           value in their defconfig file.
1875
1876           If ZBOOT_ROM is not enabled, this has no effect.
1877
1878 config ZBOOT_ROM_BSS
1879         hex "Compressed ROM boot loader BSS address"
1880         default "0"
1881         help
1882           The base address of an area of read/write memory in the target
1883           for the ROM-able zImage which must be available while the
1884           decompressor is running. It must be large enough to hold the
1885           entire decompressed kernel plus an additional 128 KiB.
1886           Platforms which normally make use of ROM-able zImage formats
1887           normally set this to a suitable value in their defconfig file.
1888
1889           If ZBOOT_ROM is not enabled, this has no effect.
1890
1891 config ZBOOT_ROM
1892         bool "Compressed boot loader in ROM/flash"
1893         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1894         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1895         help
1896           Say Y here if you intend to execute your compressed kernel image
1897           (zImage) directly from ROM or flash.  If unsure, say N.
1898
1899 config ARM_APPENDED_DTB
1900         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1901         depends on OF
1902         help
1903           With this option, the boot code will look for a device tree binary
1904           (DTB) appended to zImage
1905           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1906
1907           This is meant as a backward compatibility convenience for those
1908           systems with a bootloader that can't be upgraded to accommodate
1909           the documented boot protocol using a device tree.
1910
1911           Beware that there is very little in terms of protection against
1912           this option being confused by leftover garbage in memory that might
1913           look like a DTB header after a reboot if no actual DTB is appended
1914           to zImage.  Do not leave this option active in a production kernel
1915           if you don't intend to always append a DTB.  Proper passing of the
1916           location into r2 of a bootloader provided DTB is always preferable
1917           to this option.
1918
1919 config ARM_ATAG_DTB_COMPAT
1920         bool "Supplement the appended DTB with traditional ATAG information"
1921         depends on ARM_APPENDED_DTB
1922         help
1923           Some old bootloaders can't be updated to a DTB capable one, yet
1924           they provide ATAGs with memory configuration, the ramdisk address,
1925           the kernel cmdline string, etc.  Such information is dynamically
1926           provided by the bootloader and can't always be stored in a static
1927           DTB.  To allow a device tree enabled kernel to be used with such
1928           bootloaders, this option allows zImage to extract the information
1929           from the ATAG list and store it at run time into the appended DTB.
1930
1931 choice
1932         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1933         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1934
1935 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1936         bool "Use bootloader kernel arguments if available"
1937         help
1938           Uses the command-line options passed by the boot loader instead of
1939           the device tree bootargs property. If the boot loader doesn't provide
1940           any, the device tree bootargs property will be used.
1941
1942 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1943         bool "Extend with bootloader kernel arguments"
1944         help
1945           The command-line arguments provided by the boot loader will be
1946           appended to the the device tree bootargs property.
1947
1948 endchoice
1949
1950 config CMDLINE
1951         string "Default kernel command string"
1952         default ""
1953         help
1954           On some architectures (EBSA110 and CATS), there is currently no way
1955           for the boot loader to pass arguments to the kernel. For these
1956           architectures, you should supply some command-line options at build
1957           time by entering them here. As a minimum, you should specify the
1958           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1959
1960 choice
1961         prompt "Kernel command line type" if CMDLINE != ""
1962         default CMDLINE_FROM_BOOTLOADER
1963         depends on ATAGS
1964
1965 config CMDLINE_FROM_BOOTLOADER
1966         bool "Use bootloader kernel arguments if available"
1967         help
1968           Uses the command-line options passed by the boot loader. If
1969           the boot loader doesn't provide any, the default kernel command
1970           string provided in CMDLINE will be used.
1971
1972 config CMDLINE_EXTEND
1973         bool "Extend bootloader kernel arguments"
1974         help
1975           The command-line arguments provided by the boot loader will be
1976           appended to the default kernel command string.
1977
1978 config CMDLINE_FORCE
1979         bool "Always use the default kernel command string"
1980         help
1981           Always use the default kernel command string, even if the boot
1982           loader passes other arguments to the kernel.
1983           This is useful if you cannot or don't want to change the
1984           command-line options your boot loader passes to the kernel.
1985 endchoice
1986
1987 config XIP_KERNEL
1988         bool "Kernel Execute-In-Place from ROM"
1989         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1990         help
1991           Execute-In-Place allows the kernel to run from non-volatile storage
1992           directly addressable by the CPU, such as NOR flash. This saves RAM
1993           space since the text section of the kernel is not loaded from flash
1994           to RAM.  Read-write sections, such as the data section and stack,
1995           are still copied to RAM.  The XIP kernel is not compressed since
1996           it has to run directly from flash, so it will take more space to
1997           store it.  The flash address used to link the kernel object files,
1998           and for storing it, is configuration dependent. Therefore, if you
1999           say Y here, you must know the proper physical address where to
2000           store the kernel image depending on your own flash memory usage.
2001
2002           Also note that the make target becomes "make xipImage" rather than
2003           "make zImage" or "make Image".  The final kernel binary to put in
2004           ROM memory will be arch/arm/boot/xipImage.
2005
2006           If unsure, say N.
2007
2008 config XIP_PHYS_ADDR
2009         hex "XIP Kernel Physical Location"
2010         depends on XIP_KERNEL
2011         default "0x00080000"
2012         help
2013           This is the physical address in your flash memory the kernel will
2014           be linked for and stored to.  This address is dependent on your
2015           own flash usage.
2016
2017 config KEXEC
2018         bool "Kexec system call (EXPERIMENTAL)"
2019         depends on (!SMP || PM_SLEEP_SMP)
2020         depends on !CPU_V7M
2021         select KEXEC_CORE
2022         help
2023           kexec is a system call that implements the ability to shutdown your
2024           current kernel, and to start another kernel.  It is like a reboot
2025           but it is independent of the system firmware.   And like a reboot
2026           you can start any kernel with it, not just Linux.
2027
2028           It is an ongoing process to be certain the hardware in a machine
2029           is properly shutdown, so do not be surprised if this code does not
2030           initially work for you.
2031
2032 config ATAGS_PROC
2033         bool "Export atags in procfs"
2034         depends on ATAGS && KEXEC
2035         default y
2036         help
2037           Should the atags used to boot the kernel be exported in an "atags"
2038           file in procfs. Useful with kexec.
2039
2040 config CRASH_DUMP
2041         bool "Build kdump crash kernel (EXPERIMENTAL)"
2042         help
2043           Generate crash dump after being started by kexec. This should
2044           be normally only set in special crash dump kernels which are
2045           loaded in the main kernel with kexec-tools into a specially
2046           reserved region and then later executed after a crash by
2047           kdump/kexec. The crash dump kernel must be compiled to a
2048           memory address not used by the main kernel
2049
2050           For more details see Documentation/kdump/kdump.txt
2051
2052 config AUTO_ZRELADDR
2053         bool "Auto calculation of the decompressed kernel image address"
2054         help
2055           ZRELADDR is the physical address where the decompressed kernel
2056           image will be placed. If AUTO_ZRELADDR is selected, the address
2057           will be determined at run-time by masking the current IP with
2058           0xf8000000. This assumes the zImage being placed in the first 128MB
2059           from start of memory.
2060
2061 config EFI_STUB
2062         bool
2063
2064 config EFI
2065         bool "UEFI runtime support"
2066         depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2067         select UCS2_STRING
2068         select EFI_PARAMS_FROM_FDT
2069         select EFI_STUB
2070         select EFI_ARMSTUB
2071         select EFI_RUNTIME_WRAPPERS
2072         ---help---
2073           This option provides support for runtime services provided
2074           by UEFI firmware (such as non-volatile variables, realtime
2075           clock, and platform reset). A UEFI stub is also provided to
2076           allow the kernel to be booted as an EFI application. This
2077           is only useful for kernels that may run on systems that have
2078           UEFI firmware.
2079
2080 endmenu
2081
2082 menu "CPU Power Management"
2083
2084 source "drivers/cpufreq/Kconfig"
2085
2086 source "drivers/cpuidle/Kconfig"
2087
2088 endmenu
2089
2090 menu "Floating point emulation"
2091
2092 comment "At least one emulation must be selected"
2093
2094 config FPE_NWFPE
2095         bool "NWFPE math emulation"
2096         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2097         ---help---
2098           Say Y to include the NWFPE floating point emulator in the kernel.
2099           This is necessary to run most binaries. Linux does not currently
2100           support floating point hardware so you need to say Y here even if
2101           your machine has an FPA or floating point co-processor podule.
2102
2103           You may say N here if you are going to load the Acorn FPEmulator
2104           early in the bootup.
2105
2106 config FPE_NWFPE_XP
2107         bool "Support extended precision"
2108         depends on FPE_NWFPE
2109         help
2110           Say Y to include 80-bit support in the kernel floating-point
2111           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2112           Note that gcc does not generate 80-bit operations by default,
2113           so in most cases this option only enlarges the size of the
2114           floating point emulator without any good reason.
2115
2116           You almost surely want to say N here.
2117
2118 config FPE_FASTFPE
2119         bool "FastFPE math emulation (EXPERIMENTAL)"
2120         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2121         ---help---
2122           Say Y here to include the FAST floating point emulator in the kernel.
2123           This is an experimental much faster emulator which now also has full
2124           precision for the mantissa.  It does not support any exceptions.
2125           It is very simple, and approximately 3-6 times faster than NWFPE.
2126
2127           It should be sufficient for most programs.  It may be not suitable
2128           for scientific calculations, but you have to check this for yourself.
2129           If you do not feel you need a faster FP emulation you should better
2130           choose NWFPE.
2131
2132 config VFP
2133         bool "VFP-format floating point maths"
2134         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2135         help
2136           Say Y to include VFP support code in the kernel. This is needed
2137           if your hardware includes a VFP unit.
2138
2139           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2140           release notes and additional status information.
2141
2142           Say N if your target does not have VFP hardware.
2143
2144 config VFPv3
2145         bool
2146         depends on VFP
2147         default y if CPU_V7
2148
2149 config NEON
2150         bool "Advanced SIMD (NEON) Extension support"
2151         depends on VFPv3 && CPU_V7
2152         help
2153           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2154           Extension.
2155
2156 config KERNEL_MODE_NEON
2157         bool "Support for NEON in kernel mode"
2158         depends on NEON && AEABI
2159         help
2160           Say Y to include support for NEON in kernel mode.
2161
2162 endmenu
2163
2164 menu "Userspace binary formats"
2165
2166 source "fs/Kconfig.binfmt"
2167
2168 endmenu
2169
2170 menu "Power management options"
2171
2172 source "kernel/power/Kconfig"
2173
2174 config ARCH_SUSPEND_POSSIBLE
2175         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2176                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2177         def_bool y
2178
2179 config ARM_CPU_SUSPEND
2180         def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2181         depends on ARCH_SUSPEND_POSSIBLE
2182
2183 config ARCH_HIBERNATION_POSSIBLE
2184         bool
2185         depends on MMU
2186         default y if ARCH_SUSPEND_POSSIBLE
2187
2188 endmenu
2189
2190 source "net/Kconfig"
2191
2192 source "drivers/Kconfig"
2193
2194 source "drivers/firmware/Kconfig"
2195
2196 source "fs/Kconfig"
2197
2198 source "arch/arm/Kconfig.debug"
2199
2200 source "security/Kconfig"
2201
2202 source "crypto/Kconfig"
2203 if CRYPTO
2204 source "arch/arm/crypto/Kconfig"
2205 endif
2206
2207 source "lib/Kconfig"
2208
2209 source "arch/arm/kvm/Kconfig"