arch/arm/boot/dts/armada-388-rd.dts

   1 /*
   2  * Device Tree file for Marvell Armada 388 Reference Design board
   3  * (RD-88F6820-AP)
   4  *
   5  *  Copyright (C) 2014 Marvell
   6  *
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  *
  10  * This file is dual-licensed: you can use it either under the terms
  11  * of the GPL or the X11 license, at your option. Note that this dual
  12  * licensing only applies to this file, and not this project as a
  13  * whole.
  14  *
  15  *  a) This file is free software; you can redistribute it and/or
  16  *     modify it under the terms of the GNU General Public License as
  17  *     published by the Free Software Foundation; either version 2 of the
  18  *     License, or (at your option) any later version.
  19  *
  20  *     This file is distributed in the hope that it will be useful
  21  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  *     GNU General Public License for more details.
  24  *
  25  * Or, alternatively
  26  *
  27  *  b) Permission is hereby granted, free of charge, to any person
  28  *     obtaining a copy of this software and associated documentation
  29  *     files (the "Software"), to deal in the Software without
  30  *     restriction, including without limitation the rights to use
  31  *     copy, modify, merge, publish, distribute, sublicense, and/or
  32  *     sell copies of the Software, and to permit persons to whom the
  33  *     Software is furnished to do so, subject to the following
  34  *     conditions:
  35  *
  36  *     The above copyright notice and this permission notice shall be
  37  *     included in all copies or substantial portions of the Software.
  38  *
  39  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  40  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  41  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  42  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  43  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  44  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  45  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  46  *     OTHER DEALINGS IN THE SOFTWARE.
  47  */
  48
  49 /dts-v1/;
  50 #include "armada-388.dtsi"
  51
  52 / {
  53         model = "Marvell Armada 385 Reference Design";
  54         compatible = "marvell,a385-rd", "marvell,armada388",
  55                 "marvell,armada385","marvell,armada380";
  56
  57         chosen {
  58                 stdout-path = "serial0:115200n8";
  59         };
  60
  61         memory {
  62                 device_type = "memory";
  63                 reg = <0x00000000 0x10000000>; /* 256 MB */
  64         };
  65
  66         soc {
  67                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
  68                           MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
  69                           MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
  70                           MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
  71
  72                 internal-regs {
  73                         i2c@11000 {
  74                                 status = "okay";
  75                                 clock-frequency = <100000>;
  76                         };
  77
  78                         sdhci@d8000 {
  79                                 pinctrl-names = "default";
  80                                 pinctrl-0 = <&sdhci_pins>;
  81                                 broken-cd;
  82                                 no-1-8-v;
  83                                 wp-inverted;
  84                                 bus-width = <8>;
  85                                 status = "okay";
  86                         };
  87
  88                         serial@12000 {
  89                                 status = "okay";
  90                         };
  91
  92                         ethernet@30000 {
  93                                 status = "okay";
  94                                 phy = <&phy0>;
  95                                 phy-mode = "rgmii-id";
  96                         };
  97
  98                         ethernet@70000 {
  99                                 status = "okay";
 100                                 phy = <&phy1>;
 101                                 phy-mode = "rgmii-id";
 102                         };
 103
 104
 105                         mdio@72004 {
 106                                 phy0: ethernet-phy@0 {
 107                                         reg = <0>;
 108                                 };
 109
 110                                 phy1: ethernet-phy@1 {
 111                                         reg = <1>;
 112                                 };
 113                         };
 114
 115                         usb3@f0000 {
 116                                 status = "okay";
 117                         };
 118                 };
 119
 120                 pcie-controller {
 121                         status = "okay";
 122                         /*
 123                          * One PCIe units is accessible through
 124                          * standard PCIe slot on the board.
 125                          */
 126                         pcie@1,0 {
 127                                 /* Port 0, Lane 0 */
 128                                 status = "okay";
 129                         };
 130                 };
 131         };
 132 };
 133
 134 &spi0 {
 135         status = "okay";
 136
 137         spi-flash@0 {
 138                 #address-cells = <1>;
 139                 #size-cells = <1>;
 140                 compatible = "st,m25p128", "jedec,spi-nor";
 141                 reg = <0>; /* Chip select 0 */
 142                 spi-max-frequency = <108000000>;
 143         };
 144 };
 145