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[deliverable/linux.git] / arch / arm / boot / dts / armada-38x.dtsi
1 /*
2 * Device Tree Include file for Marvell Armada 38x family of SoCs.
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 *
10 * This file is dual-licensed: you can use it either under the terms
11 * of the GPL or the X11 license, at your option. Note that this dual
12 * licensing only applies to this file, and not this project as a
13 * whole.
14 *
15 * a) This file is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of the
18 * License, or (at your option) any later version.
19 *
20 * This file is distributed in the hope that it will be useful
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * Or, alternatively
26 *
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
34 * conditions:
35 *
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
38 *
39 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
47 */
48
49 #include "skeleton.dtsi"
50 #include <dt-bindings/interrupt-controller/arm-gic.h>
51 #include <dt-bindings/interrupt-controller/irq.h>
52
53 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
54
55 / {
56 model = "Marvell Armada 38x family SoC";
57 compatible = "marvell,armada380";
58
59 aliases {
60 gpio0 = &gpio0;
61 gpio1 = &gpio1;
62 serial0 = &uart0;
63 serial1 = &uart1;
64 };
65
66 pmu {
67 compatible = "arm,cortex-a9-pmu";
68 interrupts-extended = <&mpic 3>;
69 };
70
71 soc {
72 compatible = "marvell,armada380-mbus", "simple-bus";
73 #address-cells = <2>;
74 #size-cells = <1>;
75 controller = <&mbusc>;
76 interrupt-parent = <&gic>;
77 pcie-mem-aperture = <0xe0000000 0x8000000>;
78 pcie-io-aperture = <0xe8000000 0x100000>;
79
80 bootrom {
81 compatible = "marvell,bootrom";
82 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
83 };
84
85 devbus-bootcs {
86 compatible = "marvell,mvebu-devbus";
87 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
88 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 clocks = <&coreclk 0>;
92 status = "disabled";
93 };
94
95 devbus-cs0 {
96 compatible = "marvell,mvebu-devbus";
97 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
98 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
99 #address-cells = <1>;
100 #size-cells = <1>;
101 clocks = <&coreclk 0>;
102 status = "disabled";
103 };
104
105 devbus-cs1 {
106 compatible = "marvell,mvebu-devbus";
107 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
108 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
109 #address-cells = <1>;
110 #size-cells = <1>;
111 clocks = <&coreclk 0>;
112 status = "disabled";
113 };
114
115 devbus-cs2 {
116 compatible = "marvell,mvebu-devbus";
117 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
118 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
119 #address-cells = <1>;
120 #size-cells = <1>;
121 clocks = <&coreclk 0>;
122 status = "disabled";
123 };
124
125 devbus-cs3 {
126 compatible = "marvell,mvebu-devbus";
127 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
128 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
129 #address-cells = <1>;
130 #size-cells = <1>;
131 clocks = <&coreclk 0>;
132 status = "disabled";
133 };
134
135 internal-regs {
136 compatible = "simple-bus";
137 #address-cells = <1>;
138 #size-cells = <1>;
139 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
140
141 L2: cache-controller@8000 {
142 compatible = "arm,pl310-cache";
143 reg = <0x8000 0x1000>;
144 cache-unified;
145 cache-level = <2>;
146 arm,double-linefill-incr = <1>;
147 arm,double-linefill-wrap = <0>;
148 arm,double-linefill = <1>;
149 prefetch-data = <1>;
150 };
151
152 scu@c000 {
153 compatible = "arm,cortex-a9-scu";
154 reg = <0xc000 0x58>;
155 };
156
157 timer@c600 {
158 compatible = "arm,cortex-a9-twd-timer";
159 reg = <0xc600 0x20>;
160 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
161 clocks = <&coreclk 2>;
162 };
163
164 gic: interrupt-controller@d000 {
165 compatible = "arm,cortex-a9-gic";
166 #interrupt-cells = <3>;
167 #size-cells = <0>;
168 interrupt-controller;
169 reg = <0xd000 0x1000>,
170 <0xc100 0x100>;
171 };
172
173 i2c0: i2c@11000 {
174 compatible = "marvell,mv64xxx-i2c";
175 reg = <0x11000 0x20>;
176 #address-cells = <1>;
177 #size-cells = <0>;
178 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
179 timeout-ms = <1000>;
180 clocks = <&coreclk 0>;
181 status = "disabled";
182 };
183
184 i2c1: i2c@11100 {
185 compatible = "marvell,mv64xxx-i2c";
186 reg = <0x11100 0x20>;
187 #address-cells = <1>;
188 #size-cells = <0>;
189 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
190 timeout-ms = <1000>;
191 clocks = <&coreclk 0>;
192 status = "disabled";
193 };
194
195 uart0: serial@12000 {
196 compatible = "snps,dw-apb-uart";
197 reg = <0x12000 0x100>;
198 reg-shift = <2>;
199 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
200 reg-io-width = <1>;
201 clocks = <&coreclk 0>;
202 status = "disabled";
203 };
204
205 uart1: serial@12100 {
206 compatible = "snps,dw-apb-uart";
207 reg = <0x12100 0x100>;
208 reg-shift = <2>;
209 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
210 reg-io-width = <1>;
211 clocks = <&coreclk 0>;
212 status = "disabled";
213 };
214
215 pinctrl: pinctrl@18000 {
216 reg = <0x18000 0x20>;
217
218 ge0_rgmii_pins: ge-rgmii-pins-0 {
219 marvell,pins = "mpp6", "mpp7", "mpp8",
220 "mpp9", "mpp10", "mpp11",
221 "mpp12", "mpp13", "mpp14",
222 "mpp15", "mpp16", "mpp17";
223 marvell,function = "ge0";
224 };
225
226 ge1_rgmii_pins: ge-rgmii-pins-1 {
227 marvell,pins = "mpp21", "mpp27", "mpp28",
228 "mpp29", "mpp30", "mpp31",
229 "mpp32", "mpp37", "mpp38",
230 "mpp39", "mpp40", "mpp41";
231 marvell,function = "ge1";
232 };
233
234 i2c0_pins: i2c-pins-0 {
235 marvell,pins = "mpp2", "mpp3";
236 marvell,function = "i2c0";
237 };
238
239 mdio_pins: mdio-pins {
240 marvell,pins = "mpp4", "mpp5";
241 marvell,function = "ge";
242 };
243
244 ref_clk0_pins: ref-clk-pins-0 {
245 marvell,pins = "mpp45";
246 marvell,function = "ref";
247 };
248
249 ref_clk1_pins: ref-clk-pins-1 {
250 marvell,pins = "mpp46";
251 marvell,function = "ref";
252 };
253
254 spi0_pins: spi-pins-0 {
255 marvell,pins = "mpp22", "mpp23", "mpp24",
256 "mpp25";
257 marvell,function = "spi0";
258 };
259
260 spi1_pins: spi-pins-1 {
261 marvell,pins = "mpp56", "mpp57", "mpp58",
262 "mpp59";
263 marvell,function = "spi1";
264 };
265
266 nand_pins: nand-pins {
267 marvell,pins = "mpp22", "mpp34", "mpp23",
268 "mpp33", "mpp38", "mpp28",
269 "mpp40", "mpp42", "mpp35",
270 "mpp36", "mpp25", "mpp30",
271 "mpp32";
272 marvell,function = "dev";
273 };
274
275 uart0_pins: uart-pins-0 {
276 marvell,pins = "mpp0", "mpp1";
277 marvell,function = "ua0";
278 };
279
280 uart1_pins: uart-pins-1 {
281 marvell,pins = "mpp19", "mpp20";
282 marvell,function = "ua1";
283 };
284
285 sdhci_pins: sdhci-pins {
286 marvell,pins = "mpp48", "mpp49", "mpp50",
287 "mpp52", "mpp53", "mpp54",
288 "mpp55", "mpp57", "mpp58",
289 "mpp59";
290 marvell,function = "sd0";
291 };
292
293 sata0_pins: sata-pins-0 {
294 marvell,pins = "mpp20";
295 marvell,function = "sata0";
296 };
297
298 sata1_pins: sata-pins-1 {
299 marvell,pins = "mpp19";
300 marvell,function = "sata1";
301 };
302
303 sata2_pins: sata-pins-2 {
304 marvell,pins = "mpp47";
305 marvell,function = "sata2";
306 };
307
308 sata3_pins: sata-pins-3 {
309 marvell,pins = "mpp44";
310 marvell,function = "sata3";
311 };
312 };
313
314 gpio0: gpio@18100 {
315 compatible = "marvell,orion-gpio";
316 reg = <0x18100 0x40>;
317 ngpios = <32>;
318 gpio-controller;
319 #gpio-cells = <2>;
320 interrupt-controller;
321 #interrupt-cells = <2>;
322 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
326 };
327
328 gpio1: gpio@18140 {
329 compatible = "marvell,orion-gpio";
330 reg = <0x18140 0x40>;
331 ngpios = <28>;
332 gpio-controller;
333 #gpio-cells = <2>;
334 interrupt-controller;
335 #interrupt-cells = <2>;
336 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
340 };
341
342 system-controller@18200 {
343 compatible = "marvell,armada-380-system-controller",
344 "marvell,armada-370-xp-system-controller";
345 reg = <0x18200 0x100>;
346 };
347
348 gateclk: clock-gating-control@18220 {
349 compatible = "marvell,armada-380-gating-clock";
350 reg = <0x18220 0x4>;
351 clocks = <&coreclk 0>;
352 #clock-cells = <1>;
353 };
354
355 coreclk: mvebu-sar@18600 {
356 compatible = "marvell,armada-380-core-clock";
357 reg = <0x18600 0x04>;
358 #clock-cells = <1>;
359 };
360
361 mbusc: mbus-controller@20000 {
362 compatible = "marvell,mbus-controller";
363 reg = <0x20000 0x100>, <0x20180 0x20>;
364 };
365
366 mpic: interrupt-controller@20a00 {
367 compatible = "marvell,mpic";
368 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
369 #interrupt-cells = <1>;
370 #size-cells = <1>;
371 interrupt-controller;
372 msi-controller;
373 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
374 };
375
376 timer@20300 {
377 compatible = "marvell,armada-380-timer",
378 "marvell,armada-xp-timer";
379 reg = <0x20300 0x30>, <0x21040 0x30>;
380 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
381 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
382 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
383 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
384 <&mpic 5>,
385 <&mpic 6>;
386 clocks = <&coreclk 2>, <&refclk>;
387 clock-names = "nbclk", "fixed";
388 };
389
390 watchdog@20300 {
391 compatible = "marvell,armada-380-wdt";
392 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
393 clocks = <&coreclk 2>, <&refclk>;
394 clock-names = "nbclk", "fixed";
395 };
396
397 cpurst@20800 {
398 compatible = "marvell,armada-370-cpu-reset";
399 reg = <0x20800 0x10>;
400 };
401
402 mpcore-soc-ctrl@20d20 {
403 compatible = "marvell,armada-380-mpcore-soc-ctrl";
404 reg = <0x20d20 0x6c>;
405 };
406
407 coherency-fabric@21010 {
408 compatible = "marvell,armada-380-coherency-fabric";
409 reg = <0x21010 0x1c>;
410 };
411
412 pmsu@22000 {
413 compatible = "marvell,armada-380-pmsu";
414 reg = <0x22000 0x1000>;
415 };
416
417 /*
418 * As a special exception to the "order by
419 * register address" rule, the eth0 node is
420 * placed here to ensure that it gets
421 * registered as the first interface, since
422 * the network subsystem doesn't allow naming
423 * interfaces using DT aliases. Without this,
424 * the ordering of interfaces is different
425 * from the one used in U-Boot and the
426 * labeling of interfaces on the boards, which
427 * is very confusing for users.
428 */
429 eth0: ethernet@70000 {
430 compatible = "marvell,armada-370-neta";
431 reg = <0x70000 0x4000>;
432 interrupts-extended = <&mpic 8>;
433 clocks = <&gateclk 4>;
434 tx-csum-limit = <9800>;
435 status = "disabled";
436 };
437
438 eth1: ethernet@30000 {
439 compatible = "marvell,armada-370-neta";
440 reg = <0x30000 0x4000>;
441 interrupts-extended = <&mpic 10>;
442 clocks = <&gateclk 3>;
443 status = "disabled";
444 };
445
446 eth2: ethernet@34000 {
447 compatible = "marvell,armada-370-neta";
448 reg = <0x34000 0x4000>;
449 interrupts-extended = <&mpic 12>;
450 clocks = <&gateclk 2>;
451 status = "disabled";
452 };
453
454 usb@58000 {
455 compatible = "marvell,orion-ehci";
456 reg = <0x58000 0x500>;
457 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&gateclk 18>;
459 status = "disabled";
460 };
461
462 xor@60800 {
463 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
464 reg = <0x60800 0x100
465 0x60a00 0x100>;
466 clocks = <&gateclk 22>;
467 status = "okay";
468
469 xor00 {
470 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
471 dmacap,memcpy;
472 dmacap,xor;
473 };
474 xor01 {
475 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
476 dmacap,memcpy;
477 dmacap,xor;
478 dmacap,memset;
479 };
480 };
481
482 xor@60900 {
483 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
484 reg = <0x60900 0x100
485 0x60b00 0x100>;
486 clocks = <&gateclk 28>;
487 status = "okay";
488
489 xor10 {
490 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
491 dmacap,memcpy;
492 dmacap,xor;
493 };
494 xor11 {
495 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
496 dmacap,memcpy;
497 dmacap,xor;
498 dmacap,memset;
499 };
500 };
501
502 mdio: mdio@72004 {
503 #address-cells = <1>;
504 #size-cells = <0>;
505 compatible = "marvell,orion-mdio";
506 reg = <0x72004 0x4>;
507 clocks = <&gateclk 4>;
508 };
509
510 crypto@90000 {
511 compatible = "marvell,armada-38x-crypto";
512 reg = <0x90000 0x10000>;
513 reg-names = "regs";
514 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
516 clocks = <&gateclk 23>, <&gateclk 21>,
517 <&gateclk 14>, <&gateclk 16>;
518 clock-names = "cesa0", "cesa1",
519 "cesaz0", "cesaz1";
520 marvell,crypto-srams = <&crypto_sram0>,
521 <&crypto_sram1>;
522 marvell,crypto-sram-size = <0x800>;
523 };
524
525 rtc@a3800 {
526 compatible = "marvell,armada-380-rtc";
527 reg = <0xa3800 0x20>, <0x184a0 0x0c>;
528 reg-names = "rtc", "rtc-soc";
529 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
530 };
531
532 sata@a8000 {
533 compatible = "marvell,armada-380-ahci";
534 reg = <0xa8000 0x2000>;
535 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&gateclk 15>;
537 status = "disabled";
538 };
539
540 bm: bm@c8000 {
541 compatible = "marvell,armada-380-neta-bm";
542 reg = <0xc8000 0xac>;
543 clocks = <&gateclk 13>;
544 internal-mem = <&bm_bppi>;
545 status = "disabled";
546 };
547
548 sata@e0000 {
549 compatible = "marvell,armada-380-ahci";
550 reg = <0xe0000 0x2000>;
551 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&gateclk 30>;
553 status = "disabled";
554 };
555
556 coredivclk: clock@e4250 {
557 compatible = "marvell,armada-380-corediv-clock";
558 reg = <0xe4250 0xc>;
559 #clock-cells = <1>;
560 clocks = <&mainpll>;
561 clock-output-names = "nand";
562 };
563
564 thermal@e8078 {
565 compatible = "marvell,armada380-thermal";
566 reg = <0xe4078 0x4>, <0xe4074 0x4>;
567 status = "okay";
568 };
569
570 flash@d0000 {
571 compatible = "marvell,armada370-nand";
572 reg = <0xd0000 0x54>;
573 #address-cells = <1>;
574 #size-cells = <1>;
575 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&coredivclk 0>;
577 status = "disabled";
578 };
579
580 sdhci@d8000 {
581 compatible = "marvell,armada-380-sdhci";
582 reg-names = "sdhci", "mbus", "conf-sdio3";
583 reg = <0xd8000 0x1000>,
584 <0xdc000 0x100>,
585 <0x18454 0x4>;
586 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&gateclk 17>;
588 mrvl,clk-delay-cycles = <0x1F>;
589 status = "disabled";
590 };
591
592 usb3@f0000 {
593 compatible = "marvell,armada-380-xhci";
594 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
595 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&gateclk 9>;
597 status = "disabled";
598 };
599
600 usb3@f8000 {
601 compatible = "marvell,armada-380-xhci";
602 reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
603 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&gateclk 10>;
605 status = "disabled";
606 };
607 };
608
609 crypto_sram0: sa-sram0 {
610 compatible = "mmio-sram";
611 reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
612 clocks = <&gateclk 23>;
613 #address-cells = <1>;
614 #size-cells = <1>;
615 ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
616 };
617
618 crypto_sram1: sa-sram1 {
619 compatible = "mmio-sram";
620 reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
621 clocks = <&gateclk 21>;
622 #address-cells = <1>;
623 #size-cells = <1>;
624 ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
625 };
626
627 bm_bppi: bm-bppi {
628 compatible = "mmio-sram";
629 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
630 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
631 #address-cells = <1>;
632 #size-cells = <1>;
633 clocks = <&gateclk 13>;
634 no-memory-wc;
635 status = "disabled";
636 };
637
638 spi0: spi@10600 {
639 compatible = "marvell,armada-380-spi",
640 "marvell,orion-spi";
641 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
642 #address-cells = <1>;
643 #size-cells = <0>;
644 cell-index = <0>;
645 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&coreclk 0>;
647 status = "disabled";
648 };
649
650 spi1: spi@10680 {
651 compatible = "marvell,armada-380-spi",
652 "marvell,orion-spi";
653 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
654 #address-cells = <1>;
655 #size-cells = <0>;
656 cell-index = <1>;
657 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&coreclk 0>;
659 status = "disabled";
660 };
661 };
662
663 clocks {
664 /* 2 GHz fixed main PLL */
665 mainpll: mainpll {
666 compatible = "fixed-clock";
667 #clock-cells = <0>;
668 clock-frequency = <1000000000>;
669 };
670
671 /* 25 MHz reference crystal */
672 refclk: oscillator {
673 compatible = "fixed-clock";
674 #clock-cells = <0>;
675 clock-frequency = <25000000>;
676 };
677 };
678 };
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