arch/arm/boot/dts/imx6dl.dtsi

   1
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include "imx6dl-pinfunc.h"
  13 #include "imx6qdl.dtsi"
  14
  15 / {
  16         aliases {
  17                 i2c3 = &i2c4;
  18         };
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu@0 {
  25                         compatible = "arm,cortex-a9";
  26                         device_type = "cpu";
  27                         reg = <0>;
  28                         next-level-cache = <&L2>;
  29                         operating-points = <
  30                                 /* kHz    uV */
  31                                 996000  1250000
  32                                 792000  1175000
  33                                 396000  1150000
  34                         >;
  35                         fsl,soc-operating-points = <
  36                                 /* ARM kHz  SOC-PU uV */
  37                                 996000  1175000
  38                                 792000  1175000
  39                                 396000  1175000
  40                         >;
  41                         clock-latency = <61036>; /* two CLK32 periods */
  42                         clocks = <&clks IMX6QDL_CLK_ARM>,
  43                                  <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
  44                                  <&clks IMX6QDL_CLK_STEP>,
  45                                  <&clks IMX6QDL_CLK_PLL1_SW>,
  46                                  <&clks IMX6QDL_CLK_PLL1_SYS>;
  47                         clock-names = "arm", "pll2_pfd2_396m", "step",
  48                                       "pll1_sw", "pll1_sys";
  49                         arm-supply = <&reg_arm>;
  50                         pu-supply = <&reg_pu>;
  51                         soc-supply = <&reg_soc>;
  52                 };
  53
  54                 cpu@1 {
  55                         compatible = "arm,cortex-a9";
  56                         device_type = "cpu";
  57                         reg = <1>;
  58                         next-level-cache = <&L2>;
  59                 };
  60         };
  61
  62         soc {
  63                 ocram: sram@00900000 {
  64                         compatible = "mmio-sram";
  65                         reg = <0x00900000 0x20000>;
  66                         clocks = <&clks IMX6QDL_CLK_OCRAM>;
  67                 };
  68
  69                 aips1: aips-bus@02000000 {
  70                         iomuxc: iomuxc@020e0000 {
  71                                 compatible = "fsl,imx6dl-iomuxc";
  72                         };
  73
  74                         pxp: pxp@020f0000 {
  75                                 reg = <0x020f0000 0x4000>;
  76                                 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
  77                         };
  78
  79                         epdc: epdc@020f4000 {
  80                                 reg = <0x020f4000 0x4000>;
  81                                 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
  82                         };
  83
  84                         lcdif: lcdif@020f8000 {
  85                                 reg = <0x020f8000 0x4000>;
  86                                 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
  87                         };
  88                 };
  89
  90                 aips2: aips-bus@02100000 {
  91                         i2c4: i2c@021f8000 {
  92                                 #address-cells = <1>;
  93                                 #size-cells = <0>;
  94                                 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
  95                                 reg = <0x021f8000 0x4000>;
  96                                 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
  97                                 clocks = <&clks IMX6DL_CLK_I2C4>;
  98                                 status = "disabled";
  99                         };
 100                 };
 101         };
 102
 103         display-subsystem {
 104                 compatible = "fsl,imx-display-subsystem";
 105                 ports = <&ipu1_di0>, <&ipu1_di1>;
 106         };
 107
 108         gpu-subsystem {
 109                 compatible = "fsl,imx-gpu-subsystem";
 110                 cores = <&gpu_2d>, <&gpu_3d>;
 111         };
 112 };
 113
 114 &gpio1 {
 115         gpio-ranges = <&iomuxc  0 131 2>, <&iomuxc  2 137 8>, <&iomuxc 10 189 2>,
 116                       <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>,
 117                       <&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>,
 118                       <&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>,
 119                       <&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>,
 120                       <&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>,
 121                       <&iomuxc 30 129 1>, <&iomuxc 31 122 1>;
 122 };
 123
 124 &gpio2 {
 125         gpio-ranges = <&iomuxc  0 161 8>, <&iomuxc  8 208 8>, <&iomuxc 16  74 1>,
 126                       <&iomuxc 17  73 1>, <&iomuxc 18  72 1>, <&iomuxc 19  71 1>,
 127                       <&iomuxc 20  70 1>, <&iomuxc 21  69 1>, <&iomuxc 22  68 1>,
 128                       <&iomuxc 23  79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>,
 129                       <&iomuxc 28 113 4>;
 130 };
 131
 132 &gpio3 {
 133         gpio-ranges = <&iomuxc  0 97  2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,
 134                       <&iomuxc 16 81 16>;
 135 };
 136
 137 &gpio4 {
 138         gpio-ranges = <&iomuxc  5 136 1>, <&iomuxc  6 145 1>, <&iomuxc  7 150 1>,
 139                       <&iomuxc  8 146 1>, <&iomuxc  9 151 1>, <&iomuxc 10 147 1>,
 140                       <&iomuxc 11 151 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>,
 141                       <&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16  39 7>,
 142                       <&iomuxc 23  56 1>, <&iomuxc 24  61 7>, <&iomuxc 31  46 1>;
 143 };
 144
 145 &gpio5 {
 146         gpio-ranges = <&iomuxc  0 120 1>, <&iomuxc  2 77 1>, <&iomuxc  4 76 1>,
 147                       <&iomuxc  5  47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>,
 148                       <&iomuxc 19  36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>,
 149                       <&iomuxc 22  29 6>, <&iomuxc 28 19 4>;
 150 };
 151
 152 &gpio6 {
 153         gpio-ranges = <&iomuxc  0  23 6>, <&iomuxc  6  75 1>, <&iomuxc  7 156 1>,
 154                       <&iomuxc  8 155 1>, <&iomuxc  9 170 1>, <&iomuxc 10 169 1>,
 155                       <&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>,
 156                       <&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>,
 157                       <&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>,
 158                       <&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31  78 1>;
 159 };
 160
 161 &gpio7 {
 162         gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc  1 201 1>, <&iomuxc  2 196 1>,
 163                       <&iomuxc 3 195 1>, <&iomuxc  4 197 4>, <&iomuxc  8 205 1>,
 164                       <&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>;
 165 };
 166
 167 &gpt {
 168         compatible = "fsl,imx6dl-gpt";
 169 };
 170
 171 &hdmi {
 172         compatible = "fsl,imx6dl-hdmi";
 173 };
 174
 175 &ldb {
 176         clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
 177                  <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
 178                  <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
 179         clock-names = "di0_pll", "di1_pll",
 180                       "di0_sel", "di1_sel",
 181                       "di0", "di1";
 182 };
 183
 184 &vpu {
 185         compatible = "fsl,imx6dl-vpu", "cnm,coda960";
 186 };