arch/arm/boot/dts/imx6qdl-gw552x.dtsi

   1 /*
   2  * Copyright 2014 Gateworks Corporation
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <dt-bindings/gpio/gpio.h>
  13
  14 / {
  15         /* these are used by bootloader for disabling nodes */
  16         aliases {
  17                 led0 = &led0;
  18                 led1 = &led1;
  19                 led2 = &led2;
  20                 nand = &gpmi;
  21                 usb0 = &usbh1;
  22                 usb1 = &usbotg;
  23         };
  24
  25         chosen {
  26                 bootargs = "console=ttymxc1,115200";
  27         };
  28
  29         leds {
  30                 compatible = "gpio-leds";
  31                 pinctrl-names = "default";
  32                 pinctrl-0 = <&pinctrl_gpio_leds>;
  33
  34                 led0: user1 {
  35                         label = "user1";
  36                         gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
  37                         default-state = "on";
  38                         linux,default-trigger = "heartbeat";
  39                 };
  40
  41                 led1: user2 {
  42                         label = "user2";
  43                         gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
  44                         default-state = "off";
  45                 };
  46
  47                 led2: user3 {
  48                         label = "user3";
  49                         gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
  50                         default-state = "off";
  51                 };
  52         };
  53
  54         memory {
  55                 reg = <0x10000000 0x20000000>;
  56         };
  57
  58         regulators {
  59                 compatible = "simple-bus";
  60                 #address-cells = <1>;
  61                 #size-cells = <0>;
  62
  63                 reg_1p0v: regulator@0 {
  64                         compatible = "regulator-fixed";
  65                         reg = <0>;
  66                         regulator-name = "1P0V";
  67                         regulator-min-microvolt = <1000000>;
  68                         regulator-max-microvolt = <1000000>;
  69                         regulator-always-on;
  70                 };
  71
  72                 reg_3p3v: regulator@2 {
  73                         compatible = "regulator-fixed";
  74                         reg = <2>;
  75                         regulator-name = "3P3V";
  76                         regulator-min-microvolt = <3300000>;
  77                         regulator-max-microvolt = <3300000>;
  78                         regulator-always-on;
  79                 };
  80
  81                 reg_5p0v: regulator@3 {
  82                         compatible = "regulator-fixed";
  83                         reg = <3>;
  84                         regulator-name = "5P0V";
  85                         regulator-min-microvolt = <5000000>;
  86                         regulator-max-microvolt = <5000000>;
  87                         regulator-always-on;
  88                 };
  89         };
  90 };
  91
  92 &gpmi {
  93         pinctrl-names = "default";
  94         pinctrl-0 = <&pinctrl_gpmi_nand>;
  95         status = "okay";
  96 };
  97
  98 &hdmi {
  99         ddc-i2c-bus = <&i2c3>;
 100         status = "okay";
 101 };
 102
 103 &i2c1 {
 104         clock-frequency = <100000>;
 105         pinctrl-names = "default";
 106         pinctrl-0 = <&pinctrl_i2c1>;
 107         status = "okay";
 108
 109         eeprom1: eeprom@50 {
 110                 compatible = "atmel,24c02";
 111                 reg = <0x50>;
 112                 pagesize = <16>;
 113         };
 114
 115         eeprom2: eeprom@51 {
 116                 compatible = "atmel,24c02";
 117                 reg = <0x51>;
 118                 pagesize = <16>;
 119         };
 120
 121         eeprom3: eeprom@52 {
 122                 compatible = "atmel,24c02";
 123                 reg = <0x52>;
 124                 pagesize = <16>;
 125         };
 126
 127         eeprom4: eeprom@53 {
 128                 compatible = "atmel,24c02";
 129                 reg = <0x53>;
 130                 pagesize = <16>;
 131         };
 132
 133         gpio: pca9555@23 {
 134                 compatible = "nxp,pca9555";
 135                 reg = <0x23>;
 136                 gpio-controller;
 137                 #gpio-cells = <2>;
 138         };
 139
 140         rtc: ds1672@68 {
 141                 compatible = "dallas,ds1672";
 142                 reg = <0x68>;
 143         };
 144 };
 145
 146 &i2c2 {
 147         clock-frequency = <100000>;
 148         pinctrl-names = "default";
 149         pinctrl-0 = <&pinctrl_i2c2>;
 150         status = "okay";
 151 };
 152
 153 &i2c3 {
 154         clock-frequency = <100000>;
 155         pinctrl-names = "default";
 156         pinctrl-0 = <&pinctrl_i2c3>;
 157         status = "okay";
 158 };
 159
 160 &pcie {
 161         pinctrl-names = "default";
 162         pinctrl-0 = <&pinctrl_pcie>;
 163         reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
 164         status = "okay";
 165 };
 166
 167 &pwm2 {
 168         pinctrl-names = "default";
 169         pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 170         status = "disabled";
 171 };
 172
 173 &pwm3 {
 174         pinctrl-names = "default";
 175         pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 176         status = "disabled";
 177 };
 178
 179 &uart2 {
 180         pinctrl-names = "default";
 181         pinctrl-0 = <&pinctrl_uart2>;
 182         status = "okay";
 183 };
 184
 185 &uart3 {
 186         pinctrl-names = "default";
 187         pinctrl-0 = <&pinctrl_uart3>;
 188         status = "okay";
 189 };
 190
 191 &uart5 {
 192         pinctrl-names = "default";
 193         pinctrl-0 = <&pinctrl_uart5>;
 194         status = "okay"; };
 195
 196 &usbh1 {
 197         status = "okay";
 198 };
 199
 200 &iomuxc {
 201         imx6qdl-gw552x {
 202                 pinctrl_gpio_leds: gpioledsgrp {
 203                         fsl,pins = <
 204                                 MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
 205                                 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
 206                                 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x1b0b0
 207                         >;
 208                 };
 209
 210                 pinctrl_gpmi_nand: gpminandgrp {
 211                         fsl,pins = <
 212                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 213                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 214                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 215                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 216                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 217                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 218                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 219                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 220                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 221                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 222                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 223                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 224                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 225                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 226                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 227                         >;
 228                 };
 229
 230                 pinctrl_i2c1: i2c1grp {
 231                         fsl,pins = <
 232                                 MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 233                                 MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 234                         >;
 235                 };
 236
 237                 pinctrl_i2c2: i2c2grp {
 238                         fsl,pins = <
 239                                 MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 240                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 241                         >;
 242                 };
 243
 244                 pinctrl_i2c3: i2c3grp {
 245                         fsl,pins = <
 246                                 MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 247                                 MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 248                         >;
 249                 };
 250
 251                 pinctrl_pcie: pciegrp {
 252                         fsl,pins = <
 253                                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29        0x1b0b0
 254                         >;
 255                 };
 256
 257                 pinctrl_pwm2: pwm2grp {
 258                         fsl,pins = <
 259                                 MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 260                         >;
 261                 };
 262
 263                 pinctrl_pwm3: pwm3grp {
 264                         fsl,pins = <
 265                                 MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 266                         >;
 267                 };
 268
 269                 pinctrl_uart2: uart2grp {
 270                         fsl,pins = <
 271                                 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 272                                 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 273                         >;
 274                 };
 275
 276                 pinctrl_uart3: uart3grp {
 277                         fsl,pins = <
 278                                 MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 279                                 MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 280                         >;
 281                 };
 282
 283                 pinctrl_uart5: uart5grp {
 284                         fsl,pins = <
 285                                 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 286                                 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 287                         >;
 288                 };
 289         };
 290 };