arch/arm/boot/dts/imx7-colibri.dtsi

   1 /*
   2  * Copyright 2016 Toradex AG
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 / {
  44         bl: backlight {
  45                 compatible = "pwm-backlight";
  46                 pwms = <&pwm1 0 5000000>;
  47         };
  48
  49         reg_module_3v3: regulator-module-3v3 {
  50                 compatible = "regulator-fixed";
  51                 regulator-name = "+V3.3";
  52                 regulator-min-microvolt = <3300000>;
  53                 regulator-max-microvolt = <3300000>;
  54         };
  55
  56         reg_module_3v3_avdd: regulator-module-3v3-avdd {
  57                 compatible = "regulator-fixed";
  58                 regulator-name = "+V3.3_AVDD_AUDIO";
  59                 regulator-min-microvolt = <3300000>;
  60                 regulator-max-microvolt = <3300000>;
  61         };
  62
  63         reg_vref_1v8: regulator-vref-1v8 {
  64                 compatible = "regulator-fixed";
  65                 regulator-name = "vref-1v8";
  66                 regulator-min-microvolt = <1800000>;
  67                 regulator-max-microvolt = <1800000>;
  68         };
  69
  70         sound {
  71                 compatible = "simple-audio-card";
  72                 simple-audio-card,name = "imx7-sgtl5000";
  73                 simple-audio-card,format = "i2s";
  74                 simple-audio-card,bitclock-master = <&dailink_master>;
  75                 simple-audio-card,frame-master = <&dailink_master>;
  76                 simple-audio-card,cpu {
  77                         sound-dai = <&sai1>;
  78                 };
  79
  80                 dailink_master: simple-audio-card,codec {
  81                         sound-dai = <&codec>;
  82                         clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
  83                 };
  84         };
  85 };
  86
  87 &adc1 {
  88         vref-supply = <&reg_vref_1v8>;
  89 };
  90
  91 &adc2 {
  92         vref-supply = <&reg_vref_1v8>;
  93 };
  94
  95 &cpu0 {
  96         arm-supply = <&reg_DCDC2>;
  97 };
  98
  99 &fec1 {
 100         pinctrl-names = "default";
 101         pinctrl-0 = <&pinctrl_enet1>;
 102         clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
 103                 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
 104                 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
 105                 <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>;
 106         clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
 107         assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
 108                           <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
 109         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 110         assigned-clock-rates = <0>, <100000000>;
 111         phy-mode = "rmii";
 112         phy-supply = <&reg_LDO1>;
 113         fsl,magic-packet;
 114 };
 115
 116 &i2c1 {
 117         clock-frequency = <100000>;
 118         pinctrl-names = "default";
 119         pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>;
 120         status = "okay";
 121
 122         codec: sgtl5000@0a {
 123                 compatible = "fsl,sgtl5000";
 124                 #sound-dai-cells = <0>;
 125                 reg = <0x0a>;
 126                 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 127                 pinctrl-names = "default";
 128                 pinctrl-0 = <&pinctrl_sai1_mclk>;
 129                 VDDA-supply = <&reg_module_3v3_avdd>;
 130                 VDDIO-supply = <&reg_module_3v3>;
 131                 VDDD-supply = <&reg_DCDC3>;
 132         };
 133
 134         ad7879@2c {
 135                 compatible = "adi,ad7879-1";
 136                 reg = <0x2c>;
 137                 interrupt-parent = <&gpio1>;
 138                 interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
 139                 touchscreen-max-pressure = <4096>;
 140                 adi,resistance-plate-x = <120>;
 141                 adi,first-conversion-delay = /bits/ 8 <3>;
 142                 adi,acquisition-time = /bits/ 8 <1>;
 143                 adi,median-filter-size = /bits/ 8 <2>;
 144                 adi,averaging = /bits/ 8 <1>;
 145                 adi,conversion-interval = /bits/ 8 <255>;
 146         };
 147
 148         pmic@33 {
 149                 compatible = "ricoh,rn5t567";
 150                 reg = <0x33>;
 151
 152                 regulators {
 153                         reg_DCDC1: DCDC1 {  /* V1.0_SOC */
 154                                 regulator-min-microvolt =  <975000>;
 155                                 regulator-max-microvolt = <1125000>;
 156                                 regulator-boot-on;
 157                                 regulator-always-on;
 158                         };
 159
 160                         reg_DCDC2: DCDC2 { /* V1.1_ARM */
 161                                 regulator-min-microvolt =  <975000>;
 162                                 regulator-max-microvolt = <1125000>;
 163                                 regulator-boot-on;
 164                                 regulator-always-on;
 165                         };
 166
 167                         reg_DCDC3: DCDC3 { /* V1.8 */
 168                                 regulator-min-microvolt = <1775000>;
 169                                 regulator-max-microvolt = <1825000>;
 170                                 regulator-boot-on;
 171                                 regulator-always-on;
 172                         };
 173
 174                         reg_DCDC4: DCDC4 { /* V1.35_DRAM */
 175                                 regulator-min-microvolt = <1325000>;
 176                                 regulator-max-microvolt = <1375000>;
 177                                 regulator-boot-on;
 178                                 regulator-always-on;
 179                         };
 180
 181                         reg_LDO1: LDO1 { /* PWR_EN_+V3.3_ETH */
 182                                 regulator-min-microvolt = <1800000>;
 183                                 regulator-max-microvolt = <3300000>;
 184                                 regulator-always-on;
 185                         };
 186
 187                         reg_LDO2: LDO2 { /* +V1.8_SD */
 188                                 regulator-min-microvolt = <1775000>;
 189                                 regulator-max-microvolt = <3325000>;
 190                                 regulator-boot-on;
 191                                 regulator-always-on;
 192                         };
 193
 194                         reg_LDO3: LDO3 { /* PWR_EN_+V3.3_LPSR */
 195                                 regulator-min-microvolt = <3275000>;
 196                                 regulator-max-microvolt = <3325000>;
 197                                 regulator-boot-on;
 198                                 regulator-always-on;
 199                         };
 200
 201                         reg_LDO4: LDO4 { /* V1.8_LPSR */
 202                                 regulator-min-microvolt = <1775000>;
 203                                 regulator-max-microvolt = <1825000>;
 204                                 regulator-boot-on;
 205                                 regulator-always-on;
 206                         };
 207
 208                         reg_LDO5: LDO5 { /* PWR_EN_+V3.3 */
 209                                 regulator-min-microvolt = <1775000>;
 210                                 regulator-max-microvolt = <1825000>;
 211                                 regulator-boot-on;
 212                                 regulator-always-on;
 213                         };
 214                 };
 215         };
 216 };
 217
 218 &i2c4 {
 219         clock-frequency = <100000>;
 220         pinctrl-names = "default";
 221         pinctrl-0 = <&pinctrl_i2c4>;
 222 };
 223
 224 &lcdif {
 225         pinctrl-names = "default";
 226         pinctrl-0 = <&pinctrl_lcdif_dat
 227                      &pinctrl_lcdif_ctrl>;
 228 };
 229
 230 &pwm1 {
 231         pinctrl-names = "default";
 232         pinctrl-0 = <&pinctrl_pwm1>;
 233 };
 234
 235 &pwm2 {
 236         pinctrl-names = "default";
 237         pinctrl-0 = <&pinctrl_pwm2>;
 238 };
 239
 240 &pwm3 {
 241         pinctrl-names = "default";
 242         pinctrl-0 = <&pinctrl_pwm3>;
 243 };
 244
 245 &pwm4 {
 246         pinctrl-names = "default";
 247         pinctrl-0 = <&pinctrl_pwm4>;
 248 };
 249
 250 &reg_1p0d {
 251         vin-supply = <&reg_DCDC3>;
 252 };
 253
 254 &sai1 {
 255         pinctrl-names = "default";
 256         pinctrl-0 = <&pinctrl_sai1>;
 257         status = "okay";
 258 };
 259
 260 &snvs_pwrkey {
 261         status = "disabled";
 262 };
 263
 264 &uart1 {
 265         pinctrl-names = "default";
 266         pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>;
 267         assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
 268         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 269         uart-has-rtscts;
 270         fsl,dte-mode;
 271 };
 272
 273 &uart2 {
 274         pinctrl-names = "default";
 275         pinctrl-0 = <&pinctrl_uart2>;
 276         assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
 277         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 278         uart-has-rtscts;
 279         fsl,dte-mode;
 280 };
 281
 282 &uart3 {
 283         pinctrl-names = "default";
 284         pinctrl-0 = <&pinctrl_uart3>;
 285         assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
 286         assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
 287         fsl,dte-mode;
 288 };
 289
 290 &usbotg1 {
 291         dr_mode = "host";
 292 };
 293
 294 &usdhc1 {
 295         pinctrl-names = "default";
 296         pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
 297         no-1-8-v;
 298         cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
 299         disable-wp;
 300 };
 301
 302 &iomuxc {
 303         pinctrl-names = "default";
 304         pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>;
 305
 306         pinctrl_gpio1: gpio1-grp {
 307                 fsl,pins = <
 308                         MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3     0x14 /* SODIMM 55 */
 309                         MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2     0x14 /* SODIMM 63 */
 310                         MX7D_PAD_SD1_RESET_B__GPIO5_IO2         0X14 /* SODIMM 73 */
 311                         MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16       0X14 /* SODIMM 77 */
 312                         MX7D_PAD_EPDC_DATA09__GPIO2_IO9         0x14 /* SODIMM 89 */
 313                         MX7D_PAD_EPDC_DATA08__GPIO2_IO8         0x14 /* SODIMM 91 */
 314                         MX7D_PAD_LCD_RESET__GPIO3_IO4           0x14 /* SODIMM 93 */
 315                         MX7D_PAD_EPDC_DATA13__GPIO2_IO13        0x14 /* SODIMM 95 */
 316                         MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11    0x14 /* SODIMM 99 */
 317                         MX7D_PAD_EPDC_DATA10__GPIO2_IO10        0x14 /* SODIMM 105 */
 318                         MX7D_PAD_EPDC_DATA15__GPIO2_IO15        0x14 /* SODIMM 107 */
 319                         MX7D_PAD_EPDC_DATA00__GPIO2_IO0         0x14 /* SODIMM 111 */
 320                         MX7D_PAD_EPDC_DATA01__GPIO2_IO1         0x14 /* SODIMM 113 */
 321                         MX7D_PAD_EPDC_DATA02__GPIO2_IO2         0x14 /* SODIMM 115 */
 322                         MX7D_PAD_EPDC_DATA03__GPIO2_IO3         0x14 /* SODIMM 117 */
 323                         MX7D_PAD_EPDC_DATA04__GPIO2_IO4         0x14 /* SODIMM 119 */
 324                         MX7D_PAD_EPDC_DATA05__GPIO2_IO5         0x14 /* SODIMM 121 */
 325                         MX7D_PAD_EPDC_DATA06__GPIO2_IO6         0x14 /* SODIMM 123 */
 326                         MX7D_PAD_EPDC_DATA07__GPIO2_IO7         0x14 /* SODIMM 125 */
 327                         MX7D_PAD_EPDC_SDCE2__GPIO2_IO22         0x14 /* SODIMM 127 */
 328                         MX7D_PAD_UART3_RTS_B__GPIO4_IO6         0x14 /* SODIMM 131 */
 329                         MX7D_PAD_EPDC_GDRL__GPIO2_IO26          0x14 /* SODIMM 133 */
 330                         MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17       0x14 /* SODIMM 24 */
 331                         MX7D_PAD_SD2_DATA2__GPIO5_IO16          0x14 /* SODIMM 100 */
 332                         MX7D_PAD_SD2_DATA3__GPIO5_IO17          0x14 /* SODIMM 102 */
 333                         MX7D_PAD_EPDC_GDSP__GPIO2_IO27          0x14 /* SODIMM 104 */
 334                         MX7D_PAD_EPDC_BDR0__GPIO2_IO28          0x14 /* SODIMM 106 */
 335                         MX7D_PAD_EPDC_BDR1__GPIO2_IO29          0x14 /* SODIMM 110 */
 336                         MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30       0x14 /* SODIMM 112 */
 337                         MX7D_PAD_EPDC_SDCLK__GPIO2_IO16         0x14 /* SODIMM 114 */
 338                         MX7D_PAD_EPDC_SDLE__GPIO2_IO17          0x14 /* SODIMM 116 */
 339                         MX7D_PAD_EPDC_SDOE__GPIO2_IO18          0x14 /* SODIMM 118 */
 340                         MX7D_PAD_EPDC_SDSHR__GPIO2_IO19         0x14 /* SODIMM 120 */
 341                         MX7D_PAD_EPDC_SDCE0__GPIO2_IO20         0x14 /* SODIMM 122 */
 342                         MX7D_PAD_EPDC_SDCE1__GPIO2_IO21         0x14 /* SODIMM 124 */
 343                         MX7D_PAD_EPDC_DATA14__GPIO2_IO14        0x14 /* SODIMM 126 */
 344                         MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31      0x14 /* SODIMM 128 */
 345                         MX7D_PAD_EPDC_SDCE3__GPIO2_IO23         0x14 /* SODIMM 130 */
 346                         MX7D_PAD_EPDC_GDCLK__GPIO2_IO24         0x14 /* SODIMM 132 */
 347                         MX7D_PAD_EPDC_GDOE__GPIO2_IO25          0x14 /* SODIMM 134 */
 348                         MX7D_PAD_EPDC_DATA12__GPIO2_IO12        0x14 /* SODIMM 150 */
 349                         MX7D_PAD_EPDC_DATA11__GPIO2_IO11        0x14 /* SODIMM 152 */
 350                         MX7D_PAD_SD2_CLK__GPIO5_IO12            0x14 /* SODIMM 184 */
 351                         MX7D_PAD_SD2_CMD__GPIO5_IO13            0x14 /* SODIMM 186 */
 352                 >;
 353         };
 354
 355         pinctrl_gpio2: gpio2-grp { /* On X22 Camera interface */
 356                 fsl,pins = <
 357                         MX7D_PAD_ECSPI2_SS0__GPIO4_IO23         0x14 /* SODIMM 65 */
 358                         MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x14 /* SODIMM 69 */
 359                         MX7D_PAD_SD1_WP__GPIO5_IO1              0x14 /* SODIMM 71 */
 360                         MX7D_PAD_I2C4_SDA__GPIO4_IO15           0x14 /* SODIMM 75 */
 361                         MX7D_PAD_ECSPI1_MISO__GPIO4_IO18        0x14 /* SODIMM 79 */
 362                         MX7D_PAD_I2C3_SCL__GPIO4_IO12           0x14 /* SODIMM 81 */
 363                         MX7D_PAD_ECSPI2_MISO__GPIO4_IO22        0x14 /* SODIMM 85 */
 364                         MX7D_PAD_ECSPI1_SS0__GPIO4_IO19         0x14 /* SODIMM 97 */
 365                         MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16        0x14 /* SODIMM 101 */
 366                         MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17        0x14 /* SODIMM 103 */
 367                         MX7D_PAD_I2C3_SDA__GPIO4_IO13           0x14 /* SODIMM 94 */
 368                         MX7D_PAD_I2C4_SCL__GPIO4_IO14           0x14 /* SODIMM 96 */
 369                         MX7D_PAD_SD2_RESET_B__GPIO5_IO11        0x14 /* SODIMM 98 */
 370                 >;
 371         };
 372
 373         pinctrl_gpio3: gpio3-grp { /* LCD 18-23 */
 374                 fsl,pins = <
 375                         MX7D_PAD_LCD_DATA18__GPIO3_IO23         0x14 /* SODIMM 136 */
 376                         MX7D_PAD_LCD_DATA19__GPIO3_IO24         0x14 /* SODIMM 138 */
 377                         MX7D_PAD_LCD_DATA20__GPIO3_IO25         0x14 /* SODIMM 140 */
 378                         MX7D_PAD_LCD_DATA21__GPIO3_IO26         0x14 /* SODIMM 142 */
 379                         MX7D_PAD_LCD_DATA22__GPIO3_IO27         0x14 /* SODIMM 146 */
 380                         MX7D_PAD_LCD_DATA23__GPIO3_IO28         0x14 /* SODIMM 148 */
 381                 >;
 382         };
 383
 384         pinctrl_gpio4: gpio4-grp { /* Alternatively CAN2 */
 385                 fsl,pins = <
 386                         MX7D_PAD_GPIO1_IO15__GPIO1_IO15         0x14 /* SODIMM 178 */
 387                         MX7D_PAD_GPIO1_IO14__GPIO1_IO14         0x14 /* SODIMM 188 */
 388                 >;
 389         };
 390
 391         pinctrl_i2c1_int: i2c1-int-grp { /* PMIC / TOUCH */
 392                 fsl,pins = <
 393                         MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79
 394                 >;
 395         };
 396
 397         pinctrl_enet1: enet1grp {
 398                 fsl,pins = <
 399                         MX7D_PAD_ENET1_CRS__GPIO7_IO14                  0x14
 400                         MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73
 401                         MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x73
 402                         MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x73
 403                         MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER           0x73
 404
 405                         MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73
 406                         MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x73
 407                         MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x73
 408                         MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1          0x73
 409                         MX7D_PAD_SD2_CD_B__ENET1_MDIO                   0x3
 410                         MX7D_PAD_SD2_WP__ENET1_MDC                      0x3
 411                 >;
 412         };
 413
 414         pinctrl_ecspi3_cs: ecspi3-cs-grp {
 415                 fsl,pins = <
 416                         MX7D_PAD_I2C2_SDA__GPIO4_IO11           0x14
 417                 >;
 418         };
 419
 420         pinctrl_ecspi3: ecspi3-grp {
 421                 fsl,pins = <
 422                         MX7D_PAD_I2C1_SCL__ECSPI3_MISO          0x2
 423                         MX7D_PAD_I2C1_SDA__ECSPI3_MOSI          0x2
 424                         MX7D_PAD_I2C2_SCL__ECSPI3_SCLK          0x2
 425                 >;
 426         };
 427
 428         pinctrl_flexcan2: flexcan2-grp {
 429                 fsl,pins = <
 430                         MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX        0x59
 431                         MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX        0x59
 432                 >;
 433         };
 434
 435         pinctrl_gpmi_nand: gpmi-nand-grp {
 436                 fsl,pins = <
 437                         MX7D_PAD_SD3_CLK__NAND_CLE              0x71
 438                         MX7D_PAD_SD3_CMD__NAND_ALE              0x71
 439                         MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B       0x71
 440                         MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B       0x71
 441                         MX7D_PAD_SAI1_TX_DATA__NAND_READY_B     0x74
 442                         MX7D_PAD_SD3_STROBE__NAND_RE_B          0x71
 443                         MX7D_PAD_SD3_RESET_B__NAND_WE_B         0x71
 444                         MX7D_PAD_SD3_DATA0__NAND_DATA00         0x71
 445                         MX7D_PAD_SD3_DATA1__NAND_DATA01         0x71
 446                         MX7D_PAD_SD3_DATA2__NAND_DATA02         0x71
 447                         MX7D_PAD_SD3_DATA3__NAND_DATA03         0x71
 448                         MX7D_PAD_SD3_DATA4__NAND_DATA04         0x71
 449                         MX7D_PAD_SD3_DATA5__NAND_DATA05         0x71
 450                         MX7D_PAD_SD3_DATA6__NAND_DATA06         0x71
 451                         MX7D_PAD_SD3_DATA7__NAND_DATA07         0x71
 452                 >;
 453         };
 454
 455         pinctrl_i2c4: i2c4-grp {
 456                 fsl,pins = <
 457                         MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA      0x4000007f
 458                         MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL      0x4000007f
 459                 >;
 460         };
 461
 462         pinctrl_lcdif_dat: lcdif-dat-grp {
 463                 fsl,pins = <
 464                         MX7D_PAD_LCD_DATA00__LCD_DATA0          0x79
 465                         MX7D_PAD_LCD_DATA01__LCD_DATA1          0x79
 466                         MX7D_PAD_LCD_DATA02__LCD_DATA2          0x79
 467                         MX7D_PAD_LCD_DATA03__LCD_DATA3          0x79
 468                         MX7D_PAD_LCD_DATA04__LCD_DATA4          0x79
 469                         MX7D_PAD_LCD_DATA05__LCD_DATA5          0x79
 470                         MX7D_PAD_LCD_DATA06__LCD_DATA6          0x79
 471                         MX7D_PAD_LCD_DATA07__LCD_DATA7          0x79
 472                         MX7D_PAD_LCD_DATA08__LCD_DATA8          0x79
 473                         MX7D_PAD_LCD_DATA09__LCD_DATA9          0x79
 474                         MX7D_PAD_LCD_DATA10__LCD_DATA10         0x79
 475                         MX7D_PAD_LCD_DATA11__LCD_DATA11         0x79
 476                         MX7D_PAD_LCD_DATA12__LCD_DATA12         0x79
 477                         MX7D_PAD_LCD_DATA13__LCD_DATA13         0x79
 478                         MX7D_PAD_LCD_DATA14__LCD_DATA14         0x79
 479                         MX7D_PAD_LCD_DATA15__LCD_DATA15         0x79
 480                         MX7D_PAD_LCD_DATA16__LCD_DATA16         0x79
 481                         MX7D_PAD_LCD_DATA17__LCD_DATA17         0x79
 482                 >;
 483         };
 484
 485         pinctrl_lcdif_dat_24: lcdif-dat-24-grp {
 486                 fsl,pins = <
 487                         MX7D_PAD_LCD_DATA18__LCD_DATA18         0x79
 488                         MX7D_PAD_LCD_DATA19__LCD_DATA19         0x79
 489                         MX7D_PAD_LCD_DATA20__LCD_DATA20         0x79
 490                         MX7D_PAD_LCD_DATA21__LCD_DATA21         0x79
 491                         MX7D_PAD_LCD_DATA22__LCD_DATA22         0x79
 492                         MX7D_PAD_LCD_DATA23__LCD_DATA23         0x79
 493                 >;
 494         };
 495
 496         pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
 497                 fsl,pins = <
 498                         MX7D_PAD_LCD_CLK__LCD_CLK               0x79
 499                         MX7D_PAD_LCD_ENABLE__LCD_ENABLE         0x79
 500                         MX7D_PAD_LCD_VSYNC__LCD_VSYNC           0x79
 501                         MX7D_PAD_LCD_HSYNC__LCD_HSYNC           0x79
 502                 >;
 503         };
 504
 505         pinctrl_pwm1: pwm1-grp {
 506                 fsl,pins = <
 507                         MX7D_PAD_GPIO1_IO08__PWM1_OUT           0x79
 508                 >;
 509         };
 510
 511         pinctrl_pwm2: pwm2-grp {
 512                 fsl,pins = <
 513                         MX7D_PAD_GPIO1_IO09__PWM2_OUT           0x79
 514                 >;
 515         };
 516
 517         pinctrl_pwm3: pwm3-grp {
 518                 fsl,pins = <
 519                         MX7D_PAD_GPIO1_IO10__PWM3_OUT           0x79
 520                 >;
 521         };
 522
 523         pinctrl_pwm4: pwm4-grp {
 524                 fsl,pins = <
 525                         MX7D_PAD_GPIO1_IO11__PWM4_OUT           0x79
 526                 >;
 527         };
 528
 529         pinctrl_uart1: uart1-grp {
 530                 fsl,pins = <
 531                         MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX    0x79
 532                         MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX    0x79
 533                         MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS    0x79
 534                         MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS    0x79
 535                 >;
 536         };
 537
 538         pinctrl_uart1_ctrl1: uart1-ctrl1-grp {
 539                 fsl,pins = <
 540                         MX7D_PAD_SD2_DATA1__GPIO5_IO15          0x14 /* DCD */
 541                         MX7D_PAD_SD2_DATA0__GPIO5_IO14          0x14 /* DTR */
 542                 >;
 543         };
 544
 545         pinctrl_uart2: uart2-grp {
 546                 fsl,pins = <
 547                         MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79
 548                         MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79
 549                         MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79
 550                         MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79
 551                 >;
 552         };
 553         pinctrl_uart3: uart3-grp {
 554                 fsl,pins = <
 555                         MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79
 556                         MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79
 557                 >;
 558         };
 559
 560         pinctrl_usbotg2_reg: gpio-usbotg2-vbus {
 561                 fsl,pins = <
 562                         MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 USBH PEN */
 563                 >;
 564         };
 565
 566         pinctrl_usdhc1: usdhc1-grp {
 567                 fsl,pins = <
 568                         MX7D_PAD_SD1_CMD__SD1_CMD       0x59
 569                         MX7D_PAD_SD1_CLK__SD1_CLK       0x19
 570                         MX7D_PAD_SD1_DATA0__SD1_DATA0   0x59
 571                         MX7D_PAD_SD1_DATA1__SD1_DATA1   0x59
 572                         MX7D_PAD_SD1_DATA2__SD1_DATA2   0x59
 573                         MX7D_PAD_SD1_DATA3__SD1_DATA3   0x59
 574                 >;
 575         };
 576
 577         pinctrl_sai1: sai1-grp {
 578                 fsl,pins = <
 579                         MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK     0x1f
 580                         MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC     0x1f
 581                         MX7D_PAD_ENET1_COL__SAI1_TX_DATA0       0x30
 582                         MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0    0x1f
 583                 >;
 584         };
 585
 586         pinctrl_sai1_mclk: sai1grp_mclk {
 587                 fsl,pins = <
 588                         MX7D_PAD_SAI1_MCLK__SAI1_MCLK           0x1f
 589                 >;
 590         };
 591 };
 592
 593 &iomuxc_lpsr {
 594         pinctrl-names = "default";
 595         pinctrl-0 = <&pinctrl_gpio_lpsr>;
 596
 597         pinctrl_gpio_lpsr: gpio1-grp {
 598                 fsl,pins = <
 599                         MX7D_PAD_GPIO1_IO01__GPIO1_IO1  0x59
 600                         MX7D_PAD_GPIO1_IO02__GPIO1_IO2  0x59
 601                         MX7D_PAD_GPIO1_IO03__GPIO1_IO3  0x59
 602                 >;
 603         };
 604
 605         pinctrl_i2c1: i2c1-grp {
 606                 fsl,pins = <
 607                         MX7D_PAD_GPIO1_IO05__I2C1_SDA   0x4000007f
 608                         MX7D_PAD_GPIO1_IO04__I2C1_SCL   0x4000007f
 609                 >;
 610         };
 611
 612         pinctrl_cd_usdhc1: usdhc1-cd-grp {
 613                 fsl,pins = <
 614                         MX7D_PAD_GPIO1_IO00__GPIO1_IO0  0x59 /* CD */
 615                 >;
 616         };
 617
 618         pinctrl_uart1_ctrl2: uart1-ctrl2-grp {
 619                 fsl,pins = <
 620                         MX7D_PAD_GPIO1_IO07__GPIO1_IO7  0x14 /* DSR */
 621                         MX7D_PAD_GPIO1_IO06__GPIO1_IO6  0x14 /* RI */
 622                 >;
 623         };
 624 };