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Merge remote-tracking branch 'selinux/next'
[deliverable/linux.git] / arch / arm / boot / dts / imx7s.dtsi
1 /*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 * Copyright 2016 Toradex AG
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44 #include <dt-bindings/clock/imx7d-clock.h>
45 #include <dt-bindings/gpio/gpio.h>
46 #include <dt-bindings/input/input.h>
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include "imx7d-pinfunc.h"
49 #include "skeleton.dtsi"
50
51 / {
52 aliases {
53 gpio0 = &gpio1;
54 gpio1 = &gpio2;
55 gpio2 = &gpio3;
56 gpio3 = &gpio4;
57 gpio4 = &gpio5;
58 gpio5 = &gpio6;
59 gpio6 = &gpio7;
60 i2c0 = &i2c1;
61 i2c1 = &i2c2;
62 i2c2 = &i2c3;
63 i2c3 = &i2c4;
64 mmc0 = &usdhc1;
65 mmc1 = &usdhc2;
66 mmc2 = &usdhc3;
67 serial0 = &uart1;
68 serial1 = &uart2;
69 serial2 = &uart3;
70 serial3 = &uart4;
71 serial4 = &uart5;
72 serial5 = &uart6;
73 serial6 = &uart7;
74 spi0 = &ecspi1;
75 spi1 = &ecspi2;
76 spi2 = &ecspi3;
77 spi3 = &ecspi4;
78 };
79
80 cpus {
81 #address-cells = <1>;
82 #size-cells = <0>;
83
84 cpu0: cpu@0 {
85 compatible = "arm,cortex-a7";
86 device_type = "cpu";
87 reg = <0>;
88 clock-frequency = <792000000>;
89 clock-latency = <61036>; /* two CLK32 periods */
90 clocks = <&clks IMX7D_CLK_ARM>;
91 };
92 };
93
94 ckil: clock-cki {
95 compatible = "fixed-clock";
96 #clock-cells = <0>;
97 clock-frequency = <32768>;
98 clock-output-names = "ckil";
99 };
100
101 osc: clock-osc {
102 compatible = "fixed-clock";
103 #clock-cells = <0>;
104 clock-frequency = <24000000>;
105 clock-output-names = "osc";
106 };
107
108 soc {
109 #address-cells = <1>;
110 #size-cells = <1>;
111 compatible = "simple-bus";
112 interrupt-parent = <&intc>;
113 ranges;
114
115 funnel@30041000 {
116 compatible = "arm,coresight-funnel", "arm,primecell";
117 reg = <0x30041000 0x1000>;
118 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
119 clock-names = "apb_pclk";
120
121 ca_funnel_ports: ports {
122 #address-cells = <1>;
123 #size-cells = <0>;
124
125 /* funnel input ports */
126 port@0 {
127 reg = <0>;
128 ca_funnel_in_port0: endpoint {
129 slave-mode;
130 remote-endpoint = <&etm0_out_port>;
131 };
132 };
133
134 /* funnel output port */
135 port@2 {
136 reg = <0>;
137 ca_funnel_out_port0: endpoint {
138 remote-endpoint = <&hugo_funnel_in_port0>;
139 };
140 };
141
142 /* the other input ports are not connect to anything */
143 };
144 };
145
146 etm@3007c000 {
147 compatible = "arm,coresight-etm3x", "arm,primecell";
148 reg = <0x3007c000 0x1000>;
149 cpu = <&cpu0>;
150 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
151 clock-names = "apb_pclk";
152
153 port {
154 etm0_out_port: endpoint {
155 remote-endpoint = <&ca_funnel_in_port0>;
156 };
157 };
158 };
159
160 funnel@30083000 {
161 compatible = "arm,coresight-funnel", "arm,primecell";
162 reg = <0x30083000 0x1000>;
163 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
164 clock-names = "apb_pclk";
165
166 ports {
167 #address-cells = <1>;
168 #size-cells = <0>;
169
170 /* funnel input ports */
171 port@0 {
172 reg = <0>;
173 hugo_funnel_in_port0: endpoint {
174 slave-mode;
175 remote-endpoint = <&ca_funnel_out_port0>;
176 };
177 };
178
179 port@1 {
180 reg = <1>;
181 hugo_funnel_in_port1: endpoint {
182 slave-mode; /* M4 input */
183 };
184 };
185
186 port@2 {
187 reg = <0>;
188 hugo_funnel_out_port0: endpoint {
189 remote-endpoint = <&etf_in_port>;
190 };
191 };
192
193 /* the other input ports are not connect to anything */
194 };
195 };
196
197 etf@30084000 {
198 compatible = "arm,coresight-tmc", "arm,primecell";
199 reg = <0x30084000 0x1000>;
200 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
201 clock-names = "apb_pclk";
202
203 ports {
204 #address-cells = <1>;
205 #size-cells = <0>;
206
207 port@0 {
208 reg = <0>;
209 etf_in_port: endpoint {
210 slave-mode;
211 remote-endpoint = <&hugo_funnel_out_port0>;
212 };
213 };
214
215 port@1 {
216 reg = <0>;
217 etf_out_port: endpoint {
218 remote-endpoint = <&replicator_in_port0>;
219 };
220 };
221 };
222 };
223
224 etr@30086000 {
225 compatible = "arm,coresight-tmc", "arm,primecell";
226 reg = <0x30086000 0x1000>;
227 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
228 clock-names = "apb_pclk";
229
230 port {
231 etr_in_port: endpoint {
232 slave-mode;
233 remote-endpoint = <&replicator_out_port1>;
234 };
235 };
236 };
237
238 tpiu@30087000 {
239 compatible = "arm,coresight-tpiu", "arm,primecell";
240 reg = <0x30087000 0x1000>;
241 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
242 clock-names = "apb_pclk";
243
244 port {
245 tpiu_in_port: endpoint {
246 slave-mode;
247 remote-endpoint = <&replicator_out_port1>;
248 };
249 };
250 };
251
252 replicator {
253 /*
254 * non-configurable replicators don't show up on the
255 * AMBA bus. As such no need to add "arm,primecell"
256 */
257 compatible = "arm,coresight-replicator";
258
259 ports {
260 #address-cells = <1>;
261 #size-cells = <0>;
262
263 /* replicator output ports */
264 port@0 {
265 reg = <0>;
266 replicator_out_port0: endpoint {
267 remote-endpoint = <&tpiu_in_port>;
268 };
269 };
270
271 port@1 {
272 reg = <1>;
273 replicator_out_port1: endpoint {
274 remote-endpoint = <&etr_in_port>;
275 };
276 };
277
278 /* replicator input port */
279 port@2 {
280 reg = <0>;
281 replicator_in_port0: endpoint {
282 slave-mode;
283 remote-endpoint = <&etf_out_port>;
284 };
285 };
286 };
287 };
288
289 intc: interrupt-controller@31001000 {
290 compatible = "arm,cortex-a7-gic";
291 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
292 #interrupt-cells = <3>;
293 interrupt-controller;
294 reg = <0x31001000 0x1000>,
295 <0x31002000 0x2000>,
296 <0x31004000 0x2000>,
297 <0x31006000 0x2000>;
298 };
299
300 timer {
301 compatible = "arm,armv7-timer";
302 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
303 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
304 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
305 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
306 };
307
308 aips1: aips-bus@30000000 {
309 compatible = "fsl,aips-bus", "simple-bus";
310 #address-cells = <1>;
311 #size-cells = <1>;
312 reg = <0x30000000 0x400000>;
313 ranges;
314
315 gpio1: gpio@30200000 {
316 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
317 reg = <0x30200000 0x10000>;
318 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
319 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
320 gpio-controller;
321 #gpio-cells = <2>;
322 interrupt-controller;
323 #interrupt-cells = <2>;
324 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>;
325 };
326
327 gpio2: gpio@30210000 {
328 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
329 reg = <0x30210000 0x10000>;
330 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
332 gpio-controller;
333 #gpio-cells = <2>;
334 interrupt-controller;
335 #interrupt-cells = <2>;
336 gpio-ranges = <&iomuxc 0 13 32>;
337 };
338
339 gpio3: gpio@30220000 {
340 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
341 reg = <0x30220000 0x10000>;
342 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
344 gpio-controller;
345 #gpio-cells = <2>;
346 interrupt-controller;
347 #interrupt-cells = <2>;
348 gpio-ranges = <&iomuxc 0 45 29>;
349 };
350
351 gpio4: gpio@30230000 {
352 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
353 reg = <0x30230000 0x10000>;
354 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
356 gpio-controller;
357 #gpio-cells = <2>;
358 interrupt-controller;
359 #interrupt-cells = <2>;
360 gpio-ranges = <&iomuxc 0 74 24>;
361 };
362
363 gpio5: gpio@30240000 {
364 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
365 reg = <0x30240000 0x10000>;
366 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
367 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
368 gpio-controller;
369 #gpio-cells = <2>;
370 interrupt-controller;
371 #interrupt-cells = <2>;
372 gpio-ranges = <&iomuxc 0 98 18>;
373 };
374
375 gpio6: gpio@30250000 {
376 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
377 reg = <0x30250000 0x10000>;
378 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
379 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
380 gpio-controller;
381 #gpio-cells = <2>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
384 gpio-ranges = <&iomuxc 0 116 23>;
385 };
386
387 gpio7: gpio@30260000 {
388 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
389 reg = <0x30260000 0x10000>;
390 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
391 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
392 gpio-controller;
393 #gpio-cells = <2>;
394 interrupt-controller;
395 #interrupt-cells = <2>;
396 gpio-ranges = <&iomuxc 0 139 16>;
397 };
398
399 wdog1: wdog@30280000 {
400 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
401 reg = <0x30280000 0x10000>;
402 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
404 };
405
406 wdog2: wdog@30290000 {
407 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
408 reg = <0x30290000 0x10000>;
409 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
411 status = "disabled";
412 };
413
414 wdog3: wdog@302a0000 {
415 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
416 reg = <0x302a0000 0x10000>;
417 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
419 status = "disabled";
420 };
421
422 wdog4: wdog@302b0000 {
423 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
424 reg = <0x302b0000 0x10000>;
425 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
427 status = "disabled";
428 };
429
430 iomuxc_lpsr: iomuxc-lpsr@302c0000 {
431 compatible = "fsl,imx7d-iomuxc-lpsr";
432 reg = <0x302c0000 0x10000>;
433 fsl,input-sel = <&iomuxc>;
434 };
435
436 gpt1: gpt@302d0000 {
437 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
438 reg = <0x302d0000 0x10000>;
439 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&clks IMX7D_CLK_DUMMY>,
441 <&clks IMX7D_GPT1_ROOT_CLK>;
442 clock-names = "ipg", "per";
443 };
444
445 gpt2: gpt@302e0000 {
446 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
447 reg = <0x302e0000 0x10000>;
448 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&clks IMX7D_CLK_DUMMY>,
450 <&clks IMX7D_GPT2_ROOT_CLK>;
451 clock-names = "ipg", "per";
452 status = "disabled";
453 };
454
455 gpt3: gpt@302f0000 {
456 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
457 reg = <0x302f0000 0x10000>;
458 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
459 clocks = <&clks IMX7D_CLK_DUMMY>,
460 <&clks IMX7D_GPT3_ROOT_CLK>;
461 clock-names = "ipg", "per";
462 status = "disabled";
463 };
464
465 gpt4: gpt@30300000 {
466 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
467 reg = <0x30300000 0x10000>;
468 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&clks IMX7D_CLK_DUMMY>,
470 <&clks IMX7D_GPT4_ROOT_CLK>;
471 clock-names = "ipg", "per";
472 status = "disabled";
473 };
474
475 iomuxc: iomuxc@30330000 {
476 compatible = "fsl,imx7d-iomuxc";
477 reg = <0x30330000 0x10000>;
478 };
479
480 gpr: iomuxc-gpr@30340000 {
481 compatible = "fsl,imx7d-iomuxc-gpr", "syscon";
482 reg = <0x30340000 0x10000>;
483 };
484
485 ocotp: ocotp-ctrl@30350000 {
486 compatible = "syscon";
487 reg = <0x30350000 0x10000>;
488 clocks = <&clks IMX7D_CLK_DUMMY>;
489 status = "disabled";
490 };
491
492 anatop: anatop@30360000 {
493 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
494 "syscon", "simple-bus";
495 reg = <0x30360000 0x10000>;
496 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
498
499 reg_1p0d: regulator-vdd1p0d {
500 compatible = "fsl,anatop-regulator";
501 regulator-name = "vdd1p0d";
502 regulator-min-microvolt = <800000>;
503 regulator-max-microvolt = <1200000>;
504 anatop-reg-offset = <0x210>;
505 anatop-vol-bit-shift = <8>;
506 anatop-vol-bit-width = <5>;
507 anatop-min-bit-val = <8>;
508 anatop-min-voltage = <800000>;
509 anatop-max-voltage = <1200000>;
510 anatop-enable-bit = <31>;
511 };
512 };
513
514 snvs: snvs@30370000 {
515 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
516 reg = <0x30370000 0x10000>;
517
518 snvs_rtc: snvs-rtc-lp {
519 compatible = "fsl,sec-v4.0-mon-rtc-lp";
520 regmap = <&snvs>;
521 offset = <0x34>;
522 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
524 };
525
526 snvs_poweroff: snvs-poweroff {
527 compatible = "syscon-poweroff";
528 regmap = <&snvs>;
529 offset = <0x38>;
530 mask = <0x60>;
531 };
532
533 snvs_pwrkey: snvs-powerkey {
534 compatible = "fsl,sec-v4.0-pwrkey";
535 regmap = <&snvs>;
536 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
537 linux,keycode = <KEY_POWER>;
538 wakeup-source;
539 };
540 };
541
542 clks: ccm@30380000 {
543 compatible = "fsl,imx7d-ccm";
544 reg = <0x30380000 0x10000>;
545 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
547 #clock-cells = <1>;
548 clocks = <&ckil>, <&osc>;
549 clock-names = "ckil", "osc";
550 };
551
552 src: src@30390000 {
553 compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon";
554 reg = <0x30390000 0x10000>;
555 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
556 #reset-cells = <1>;
557 };
558 };
559
560 aips2: aips-bus@30400000 {
561 compatible = "fsl,aips-bus", "simple-bus";
562 #address-cells = <1>;
563 #size-cells = <1>;
564 reg = <0x30400000 0x400000>;
565 ranges;
566
567 adc1: adc@30610000 {
568 compatible = "fsl,imx7d-adc";
569 reg = <0x30610000 0x10000>;
570 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
572 clock-names = "adc";
573 status = "disabled";
574 };
575
576 adc2: adc@30620000 {
577 compatible = "fsl,imx7d-adc";
578 reg = <0x30620000 0x10000>;
579 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&clks IMX7D_ADC_ROOT_CLK>;
581 clock-names = "adc";
582 status = "disabled";
583 };
584
585 ecspi4: ecspi@30630000 {
586 #address-cells = <1>;
587 #size-cells = <0>;
588 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
589 reg = <0x30630000 0x10000>;
590 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
591 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
592 <&clks IMX7D_ECSPI4_ROOT_CLK>;
593 clock-names = "ipg", "per";
594 status = "disabled";
595 };
596
597 pwm1: pwm@30660000 {
598 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
599 reg = <0x30660000 0x10000>;
600 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
601 clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
602 <&clks IMX7D_PWM1_ROOT_CLK>;
603 clock-names = "ipg", "per";
604 #pwm-cells = <2>;
605 status = "disabled";
606 };
607
608 pwm2: pwm@30670000 {
609 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
610 reg = <0x30670000 0x10000>;
611 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
613 <&clks IMX7D_PWM2_ROOT_CLK>;
614 clock-names = "ipg", "per";
615 #pwm-cells = <2>;
616 status = "disabled";
617 };
618
619 pwm3: pwm@30680000 {
620 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
621 reg = <0x30680000 0x10000>;
622 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
623 clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
624 <&clks IMX7D_PWM3_ROOT_CLK>;
625 clock-names = "ipg", "per";
626 #pwm-cells = <2>;
627 status = "disabled";
628 };
629
630 pwm4: pwm@30690000 {
631 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
632 reg = <0x30690000 0x10000>;
633 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
635 <&clks IMX7D_PWM4_ROOT_CLK>;
636 clock-names = "ipg", "per";
637 #pwm-cells = <2>;
638 status = "disabled";
639 };
640
641 lcdif: lcdif@30730000 {
642 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
643 reg = <0x30730000 0x10000>;
644 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
646 <&clks IMX7D_CLK_DUMMY>,
647 <&clks IMX7D_CLK_DUMMY>;
648 clock-names = "pix", "axi", "disp_axi";
649 status = "disabled";
650 };
651 };
652
653 aips3: aips-bus@30800000 {
654 compatible = "fsl,aips-bus", "simple-bus";
655 #address-cells = <1>;
656 #size-cells = <1>;
657 reg = <0x30800000 0x400000>;
658 ranges;
659
660 ecspi1: ecspi@30820000 {
661 #address-cells = <1>;
662 #size-cells = <0>;
663 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
664 reg = <0x30820000 0x10000>;
665 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
666 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
667 <&clks IMX7D_ECSPI1_ROOT_CLK>;
668 clock-names = "ipg", "per";
669 status = "disabled";
670 };
671
672 ecspi2: ecspi@30830000 {
673 #address-cells = <1>;
674 #size-cells = <0>;
675 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
676 reg = <0x30830000 0x10000>;
677 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
678 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
679 <&clks IMX7D_ECSPI2_ROOT_CLK>;
680 clock-names = "ipg", "per";
681 status = "disabled";
682 };
683
684 ecspi3: ecspi@30840000 {
685 #address-cells = <1>;
686 #size-cells = <0>;
687 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
688 reg = <0x30840000 0x10000>;
689 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
691 <&clks IMX7D_ECSPI3_ROOT_CLK>;
692 clock-names = "ipg", "per";
693 status = "disabled";
694 };
695
696 uart1: serial@30860000 {
697 compatible = "fsl,imx7d-uart",
698 "fsl,imx6q-uart";
699 reg = <0x30860000 0x10000>;
700 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
701 clocks = <&clks IMX7D_UART1_ROOT_CLK>,
702 <&clks IMX7D_UART1_ROOT_CLK>;
703 clock-names = "ipg", "per";
704 status = "disabled";
705 };
706
707 uart2: serial@30890000 {
708 compatible = "fsl,imx7d-uart",
709 "fsl,imx6q-uart";
710 reg = <0x30890000 0x10000>;
711 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
712 clocks = <&clks IMX7D_UART2_ROOT_CLK>,
713 <&clks IMX7D_UART2_ROOT_CLK>;
714 clock-names = "ipg", "per";
715 status = "disabled";
716 };
717
718 uart3: serial@30880000 {
719 compatible = "fsl,imx7d-uart",
720 "fsl,imx6q-uart";
721 reg = <0x30880000 0x10000>;
722 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
723 clocks = <&clks IMX7D_UART3_ROOT_CLK>,
724 <&clks IMX7D_UART3_ROOT_CLK>;
725 clock-names = "ipg", "per";
726 status = "disabled";
727 };
728
729 sai1: sai@308a0000 {
730 #sound-dai-cells = <0>;
731 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
732 reg = <0x308a0000 0x10000>;
733 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&clks IMX7D_SAI1_IPG_CLK>,
735 <&clks IMX7D_SAI1_ROOT_CLK>,
736 <&clks IMX7D_CLK_DUMMY>,
737 <&clks IMX7D_CLK_DUMMY>;
738 clock-names = "bus", "mclk1", "mclk2", "mclk3";
739 dma-names = "rx", "tx";
740 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
741 status = "disabled";
742 };
743
744 sai2: sai@308b0000 {
745 #sound-dai-cells = <0>;
746 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
747 reg = <0x308b0000 0x10000>;
748 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
749 clocks = <&clks IMX7D_SAI2_IPG_CLK>,
750 <&clks IMX7D_SAI2_ROOT_CLK>,
751 <&clks IMX7D_CLK_DUMMY>,
752 <&clks IMX7D_CLK_DUMMY>;
753 clock-names = "bus", "mclk1", "mclk2", "mclk3";
754 dma-names = "rx", "tx";
755 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
756 status = "disabled";
757 };
758
759 sai3: sai@308c0000 {
760 #sound-dai-cells = <0>;
761 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
762 reg = <0x308c0000 0x10000>;
763 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
764 clocks = <&clks IMX7D_SAI3_IPG_CLK>,
765 <&clks IMX7D_SAI3_ROOT_CLK>,
766 <&clks IMX7D_CLK_DUMMY>,
767 <&clks IMX7D_CLK_DUMMY>;
768 clock-names = "bus", "mclk1", "mclk2", "mclk3";
769 dma-names = "rx", "tx";
770 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
771 status = "disabled";
772 };
773
774 flexcan1: can@30a00000 {
775 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
776 reg = <0x30a00000 0x10000>;
777 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
778 clocks = <&clks IMX7D_CLK_DUMMY>,
779 <&clks IMX7D_CAN1_ROOT_CLK>;
780 clock-names = "ipg", "per";
781 status = "disabled";
782 };
783
784 flexcan2: can@30a10000 {
785 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
786 reg = <0x30a10000 0x10000>;
787 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&clks IMX7D_CLK_DUMMY>,
789 <&clks IMX7D_CAN2_ROOT_CLK>;
790 clock-names = "ipg", "per";
791 status = "disabled";
792 };
793
794 i2c1: i2c@30a20000 {
795 #address-cells = <1>;
796 #size-cells = <0>;
797 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
798 reg = <0x30a20000 0x10000>;
799 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
800 clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
801 status = "disabled";
802 };
803
804 i2c2: i2c@30a30000 {
805 #address-cells = <1>;
806 #size-cells = <0>;
807 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
808 reg = <0x30a30000 0x10000>;
809 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
810 clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
811 status = "disabled";
812 };
813
814 i2c3: i2c@30a40000 {
815 #address-cells = <1>;
816 #size-cells = <0>;
817 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
818 reg = <0x30a40000 0x10000>;
819 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
820 clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
821 status = "disabled";
822 };
823
824 i2c4: i2c@30a50000 {
825 #address-cells = <1>;
826 #size-cells = <0>;
827 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
828 reg = <0x30a50000 0x10000>;
829 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
830 clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
831 status = "disabled";
832 };
833
834 uart4: serial@30a60000 {
835 compatible = "fsl,imx7d-uart",
836 "fsl,imx6q-uart";
837 reg = <0x30a60000 0x10000>;
838 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
839 clocks = <&clks IMX7D_UART4_ROOT_CLK>,
840 <&clks IMX7D_UART4_ROOT_CLK>;
841 clock-names = "ipg", "per";
842 status = "disabled";
843 };
844
845 uart5: serial@30a70000 {
846 compatible = "fsl,imx7d-uart",
847 "fsl,imx6q-uart";
848 reg = <0x30a70000 0x10000>;
849 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&clks IMX7D_UART5_ROOT_CLK>,
851 <&clks IMX7D_UART5_ROOT_CLK>;
852 clock-names = "ipg", "per";
853 status = "disabled";
854 };
855
856 uart6: serial@30a80000 {
857 compatible = "fsl,imx7d-uart",
858 "fsl,imx6q-uart";
859 reg = <0x30a80000 0x10000>;
860 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&clks IMX7D_UART6_ROOT_CLK>,
862 <&clks IMX7D_UART6_ROOT_CLK>;
863 clock-names = "ipg", "per";
864 status = "disabled";
865 };
866
867 uart7: serial@30a90000 {
868 compatible = "fsl,imx7d-uart",
869 "fsl,imx6q-uart";
870 reg = <0x30a90000 0x10000>;
871 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&clks IMX7D_UART7_ROOT_CLK>,
873 <&clks IMX7D_UART7_ROOT_CLK>;
874 clock-names = "ipg", "per";
875 status = "disabled";
876 };
877
878 usbotg1: usb@30b10000 {
879 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
880 reg = <0x30b10000 0x200>;
881 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
882 clocks = <&clks IMX7D_USB_CTRL_CLK>;
883 fsl,usbphy = <&usbphynop1>;
884 fsl,usbmisc = <&usbmisc1 0>;
885 phy-clkgate-delay-us = <400>;
886 status = "disabled";
887 };
888
889 usbh: usb@30b30000 {
890 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
891 reg = <0x30b30000 0x200>;
892 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&clks IMX7D_USB_CTRL_CLK>;
894 fsl,usbphy = <&usbphynop3>;
895 fsl,usbmisc = <&usbmisc3 0>;
896 phy_type = "hsic";
897 dr_mode = "host";
898 phy-clkgate-delay-us = <400>;
899 status = "disabled";
900 };
901
902 usbmisc1: usbmisc@30b10200 {
903 #index-cells = <1>;
904 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
905 reg = <0x30b10200 0x200>;
906 };
907
908 usbmisc3: usbmisc@30b30200 {
909 #index-cells = <1>;
910 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
911 reg = <0x30b30200 0x200>;
912 };
913
914 usbphynop1: usbphynop1 {
915 compatible = "usb-nop-xceiv";
916 clocks = <&clks IMX7D_USB_PHY1_CLK>;
917 clock-names = "main_clk";
918 };
919
920 usbphynop3: usbphynop3 {
921 compatible = "usb-nop-xceiv";
922 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
923 clock-names = "main_clk";
924 };
925
926 usdhc1: usdhc@30b40000 {
927 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
928 reg = <0x30b40000 0x10000>;
929 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
930 clocks = <&clks IMX7D_CLK_DUMMY>,
931 <&clks IMX7D_CLK_DUMMY>,
932 <&clks IMX7D_USDHC1_ROOT_CLK>;
933 clock-names = "ipg", "ahb", "per";
934 bus-width = <4>;
935 status = "disabled";
936 };
937
938 usdhc2: usdhc@30b50000 {
939 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
940 reg = <0x30b50000 0x10000>;
941 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
942 clocks = <&clks IMX7D_CLK_DUMMY>,
943 <&clks IMX7D_CLK_DUMMY>,
944 <&clks IMX7D_USDHC2_ROOT_CLK>;
945 clock-names = "ipg", "ahb", "per";
946 bus-width = <4>;
947 status = "disabled";
948 };
949
950 usdhc3: usdhc@30b60000 {
951 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
952 reg = <0x30b60000 0x10000>;
953 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
954 clocks = <&clks IMX7D_CLK_DUMMY>,
955 <&clks IMX7D_CLK_DUMMY>,
956 <&clks IMX7D_USDHC3_ROOT_CLK>;
957 clock-names = "ipg", "ahb", "per";
958 bus-width = <4>;
959 status = "disabled";
960 };
961
962 sdma: sdma@30bd0000 {
963 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
964 reg = <0x30bd0000 0x10000>;
965 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
966 clocks = <&clks IMX7D_SDMA_CORE_CLK>,
967 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
968 clock-names = "ipg", "ahb";
969 #dma-cells = <3>;
970 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
971 };
972
973 fec1: ethernet@30be0000 {
974 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
975 reg = <0x30be0000 0x10000>;
976 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
977 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
978 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
979 clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
980 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
981 <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
982 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
983 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
984 clock-names = "ipg", "ahb", "ptp",
985 "enet_clk_ref", "enet_out";
986 fsl,num-tx-queues=<3>;
987 fsl,num-rx-queues=<3>;
988 status = "disabled";
989 };
990 };
991 };
992 };
Linux kernel - Deliverables
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