arch/arm/boot/dts/integratorap.dts

   1 /*
   2  * Device Tree for the ARM Integrator/AP platform
   3  */
   4
   5 /dts-v1/;
   6 /include/ "integrator.dtsi"
   7
   8 / {
   9         model = "ARM Integrator/AP";
  10         compatible = "arm,integrator-ap";
  11         dma-ranges = <0x80000000 0x0 0x80000000>;
  12
  13         aliases {
  14                 arm,timer-primary = &timer2;
  15                 arm,timer-secondary = &timer1;
  16         };
  17
  18         chosen {
  19                 bootargs = "root=/dev/ram0 console=ttyAM0,38400n8 earlyprintk";
  20         };
  21
  22         /* 24 MHz chrystal on the core module */
  23         xtal24mhz: xtal24mhz@24M {
  24                 #clock-cells = <0>;
  25                 compatible = "fixed-clock";
  26                 clock-frequency = <24000000>;
  27         };
  28
  29         pclk: pclk@0 {
  30                 #clock-cells = <0>;
  31                 compatible = "fixed-factor-clock";
  32                 clock-div = <1>;
  33                 clock-mult = <1>;
  34                 clocks = <&xtal24mhz>;
  35         };
  36
  37         /* The UART clock is 14.74 MHz divided by an ICS525 */
  38         uartclk: uartclk@14.74M {
  39                 #clock-cells = <0>;
  40                 compatible = "fixed-clock";
  41                 clock-frequency = <14745600>;
  42         };
  43
  44         syscon {
  45                 compatible = "arm,integrator-ap-syscon";
  46                 reg = <0x11000000 0x100>;
  47                 interrupt-parent = <&pic>;
  48                 /* These are the logical module IRQs */
  49                 interrupts = <9>, <10>, <11>, <12>;
  50         };
  51
  52         timer0: timer@13000000 {
  53                 compatible = "arm,integrator-timer";
  54                 clocks = <&xtal24mhz>;
  55         };
  56
  57         timer1: timer@13000100 {
  58                 compatible = "arm,integrator-timer";
  59                 clocks = <&xtal24mhz>;
  60         };
  61
  62         timer2: timer@13000200 {
  63                 compatible = "arm,integrator-timer";
  64                 clocks = <&xtal24mhz>;
  65         };
  66
  67         pic: pic@14000000 {
  68                 valid-mask = <0x003fffff>;
  69         };
  70
  71         pci: pciv3@62000000 {
  72                 compatible = "v3,v360epc-pci";
  73                 #interrupt-cells = <1>;
  74                 #size-cells = <2>;
  75                 #address-cells = <3>;
  76                 reg = <0x62000000 0x10000>;
  77                 interrupt-parent = <&pic>;
  78                 interrupts = <17>; /* Bus error IRQ */
  79                 ranges = <0x00000000 0 0x61000000 /* config space */
  80                         0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */
  81                         0x01000000 0 0x0 /* I/O space */
  82                         0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */
  83                         0x02000000 0 0x00000000 /* non-prefectable memory */
  84                         0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */
  85                         0x42000000 0 0x10000000 /* prefetchable memory */
  86                         0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */
  87                 interrupt-map-mask = <0xf800 0 0 0x7>;
  88                 interrupt-map = <
  89                 /* IDSEL 9 */
  90                 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
  91                 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
  92                 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
  93                 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
  94                 /* IDSEL 10 */
  95                 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
  96                 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
  97                 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
  98                 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
  99                 /* IDSEL 11 */
 100                 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
 101                 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
 102                 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
 103                 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
 104                 /* IDSEL 12 */
 105                 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
 106                 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
 107                 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
 108                 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
 109                 >;
 110         };
 111
 112         fpga {
 113                 /*
 114                  * The Integator/AP predates the idea to have magic numbers
 115                  * identifying the PrimeCell in hardware, thus we have to
 116                  * supply these from the device tree.
 117                  */
 118                 rtc: rtc@15000000 {
 119                         compatible = "arm,pl030", "arm,primecell";
 120                         arm,primecell-periphid = <0x00041030>;
 121                         clocks = <&pclk>;
 122                         clock-names = "apb_pclk";
 123                 };
 124
 125                 uart0: uart@16000000 {
 126                         compatible = "arm,pl010", "arm,primecell";
 127                         arm,primecell-periphid = <0x00041010>;
 128                         clocks = <&uartclk>, <&pclk>;
 129                         clock-names = "uartclk", "apb_pclk";
 130                 };
 131
 132                 uart1: uart@17000000 {
 133                         compatible = "arm,pl010", "arm,primecell";
 134                         arm,primecell-periphid = <0x00041010>;
 135                         clocks = <&uartclk>, <&pclk>;
 136                         clock-names = "uartclk", "apb_pclk";
 137                 };
 138
 139                 kmi0: kmi@18000000 {
 140                         compatible = "arm,pl050", "arm,primecell";
 141                         arm,primecell-periphid = <0x00041050>;
 142                         clocks = <&xtal24mhz>, <&pclk>;
 143                         clock-names = "KMIREFCLK", "apb_pclk";
 144                 };
 145
 146                 kmi1: kmi@19000000 {
 147                         compatible = "arm,pl050", "arm,primecell";
 148                         arm,primecell-periphid = <0x00041050>;
 149                         clocks = <&xtal24mhz>, <&pclk>;
 150                         clock-names = "KMIREFCLK", "apb_pclk";
 151                 };
 152         };
 153 };