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Merge tag 'linux-kselftest-4.8-rc1-fixes' of git://git.kernel.org/pub/scm/linux/kerne...
[deliverable/linux.git] / arch / arm / boot / dts / qcom-apq8064.dtsi
1 /dts-v1/;
2
3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
6 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 / {
10 model = "Qualcomm APQ8064";
11 compatible = "qcom,apq8064";
12 interrupt-parent = <&intc>;
13
14 reserved-memory {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 ranges;
18
19 smem_region: smem@80000000 {
20 reg = <0x80000000 0x200000>;
21 no-map;
22 };
23 };
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu@0 {
30 compatible = "qcom,krait";
31 enable-method = "qcom,kpss-acc-v1";
32 device_type = "cpu";
33 reg = <0>;
34 next-level-cache = <&L2>;
35 qcom,acc = <&acc0>;
36 qcom,saw = <&saw0>;
37 cpu-idle-states = <&CPU_SPC>;
38 };
39
40 cpu@1 {
41 compatible = "qcom,krait";
42 enable-method = "qcom,kpss-acc-v1";
43 device_type = "cpu";
44 reg = <1>;
45 next-level-cache = <&L2>;
46 qcom,acc = <&acc1>;
47 qcom,saw = <&saw1>;
48 cpu-idle-states = <&CPU_SPC>;
49 };
50
51 cpu@2 {
52 compatible = "qcom,krait";
53 enable-method = "qcom,kpss-acc-v1";
54 device_type = "cpu";
55 reg = <2>;
56 next-level-cache = <&L2>;
57 qcom,acc = <&acc2>;
58 qcom,saw = <&saw2>;
59 cpu-idle-states = <&CPU_SPC>;
60 };
61
62 cpu@3 {
63 compatible = "qcom,krait";
64 enable-method = "qcom,kpss-acc-v1";
65 device_type = "cpu";
66 reg = <3>;
67 next-level-cache = <&L2>;
68 qcom,acc = <&acc3>;
69 qcom,saw = <&saw3>;
70 cpu-idle-states = <&CPU_SPC>;
71 };
72
73 L2: l2-cache {
74 compatible = "cache";
75 cache-level = <2>;
76 };
77
78 idle-states {
79 CPU_SPC: spc {
80 compatible = "qcom,idle-state-spc",
81 "arm,idle-state";
82 entry-latency-us = <400>;
83 exit-latency-us = <900>;
84 min-residency-us = <3000>;
85 };
86 };
87 };
88
89 cpu-pmu {
90 compatible = "qcom,krait-pmu";
91 interrupts = <1 10 0x304>;
92 };
93
94 clocks {
95 cxo_board {
96 compatible = "fixed-clock";
97 #clock-cells = <0>;
98 clock-frequency = <19200000>;
99 };
100
101 pxo_board {
102 compatible = "fixed-clock";
103 #clock-cells = <0>;
104 clock-frequency = <27000000>;
105 };
106
107 sleep_clk {
108 compatible = "fixed-clock";
109 #clock-cells = <0>;
110 clock-frequency = <32768>;
111 };
112 };
113
114 sfpb_mutex: hwmutex {
115 compatible = "qcom,sfpb-mutex";
116 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
117 #hwlock-cells = <1>;
118 };
119
120 smem {
121 compatible = "qcom,smem";
122 memory-region = <&smem_region>;
123
124 hwlocks = <&sfpb_mutex 3>;
125 };
126
127 smd {
128 compatible = "qcom,smd";
129
130 modem@0 {
131 interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
132
133 qcom,ipc = <&l2cc 8 3>;
134 qcom,smd-edge = <0>;
135
136 status = "disabled";
137 };
138
139 q6@1 {
140 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
141
142 qcom,ipc = <&l2cc 8 15>;
143 qcom,smd-edge = <1>;
144
145 status = "disabled";
146 };
147
148 dsps@3 {
149 interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
150
151 qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
152 qcom,smd-edge = <3>;
153
154 status = "disabled";
155 };
156
157 riva@6 {
158 interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
159
160 qcom,ipc = <&l2cc 8 25>;
161 qcom,smd-edge = <6>;
162
163 status = "disabled";
164 };
165 };
166
167 smsm {
168 compatible = "qcom,smsm";
169
170 #address-cells = <1>;
171 #size-cells = <0>;
172
173 qcom,ipc-1 = <&l2cc 8 4>;
174 qcom,ipc-2 = <&l2cc 8 14>;
175 qcom,ipc-3 = <&l2cc 8 23>;
176 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
177
178 apps_smsm: apps@0 {
179 reg = <0>;
180 #qcom,state-cells = <1>;
181 };
182
183 modem_smsm: modem@1 {
184 reg = <1>;
185 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
186
187 interrupt-controller;
188 #interrupt-cells = <2>;
189 };
190
191 q6_smsm: q6@2 {
192 reg = <2>;
193 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
194
195 interrupt-controller;
196 #interrupt-cells = <2>;
197 };
198
199 wcnss_smsm: wcnss@3 {
200 reg = <3>;
201 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
202
203 interrupt-controller;
204 #interrupt-cells = <2>;
205 };
206
207 dsps_smsm: dsps@4 {
208 reg = <4>;
209 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
210
211 interrupt-controller;
212 #interrupt-cells = <2>;
213 };
214 };
215
216 soc: soc {
217 #address-cells = <1>;
218 #size-cells = <1>;
219 ranges;
220 compatible = "simple-bus";
221
222 tlmm_pinmux: pinctrl@800000 {
223 compatible = "qcom,apq8064-pinctrl";
224 reg = <0x800000 0x4000>;
225
226 gpio-controller;
227 #gpio-cells = <2>;
228 interrupt-controller;
229 #interrupt-cells = <2>;
230 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
231
232 pinctrl-names = "default";
233 pinctrl-0 = <&ps_hold>;
234 };
235
236 sfpb_wrapper_mutex: syscon@1200000 {
237 compatible = "syscon";
238 reg = <0x01200000 0x8000>;
239 };
240
241 intc: interrupt-controller@2000000 {
242 compatible = "qcom,msm-qgic2";
243 interrupt-controller;
244 #interrupt-cells = <3>;
245 reg = <0x02000000 0x1000>,
246 <0x02002000 0x1000>;
247 };
248
249 timer@200a000 {
250 compatible = "qcom,kpss-timer",
251 "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
252 interrupts = <1 1 0x301>,
253 <1 2 0x301>,
254 <1 3 0x301>;
255 reg = <0x0200a000 0x100>;
256 clock-frequency = <27000000>,
257 <32768>;
258 cpu-offset = <0x80000>;
259 };
260
261 acc0: clock-controller@2088000 {
262 compatible = "qcom,kpss-acc-v1";
263 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
264 };
265
266 acc1: clock-controller@2098000 {
267 compatible = "qcom,kpss-acc-v1";
268 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
269 };
270
271 acc2: clock-controller@20a8000 {
272 compatible = "qcom,kpss-acc-v1";
273 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
274 };
275
276 acc3: clock-controller@20b8000 {
277 compatible = "qcom,kpss-acc-v1";
278 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
279 };
280
281 saw0: power-controller@2089000 {
282 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
283 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
284 regulator;
285 };
286
287 saw1: power-controller@2099000 {
288 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
289 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
290 regulator;
291 };
292
293 saw2: power-controller@20a9000 {
294 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
295 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
296 regulator;
297 };
298
299 saw3: power-controller@20b9000 {
300 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
301 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
302 regulator;
303 };
304
305 sps_sic_non_secure: sps-sic-non-secure@12100000 {
306 compatible = "syscon";
307 reg = <0x12100000 0x10000>;
308 };
309
310 gsbi1: gsbi@12440000 {
311 status = "disabled";
312 compatible = "qcom,gsbi-v1.0.0";
313 cell-index = <1>;
314 reg = <0x12440000 0x100>;
315 clocks = <&gcc GSBI1_H_CLK>;
316 clock-names = "iface";
317 #address-cells = <1>;
318 #size-cells = <1>;
319 ranges;
320
321 syscon-tcsr = <&tcsr>;
322
323 gsbi1_serial: serial@12450000 {
324 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
325 reg = <0x12450000 0x100>,
326 <0x12400000 0x03>;
327 interrupts = <0 193 0x0>;
328 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
329 clock-names = "core", "iface";
330 status = "disabled";
331 };
332
333 gsbi1_i2c: i2c@12460000 {
334 compatible = "qcom,i2c-qup-v1.1.1";
335 pinctrl-0 = <&i2c1_pins>;
336 pinctrl-1 = <&i2c1_pins_sleep>;
337 pinctrl-names = "default", "sleep";
338 reg = <0x12460000 0x1000>;
339 interrupts = <0 194 IRQ_TYPE_NONE>;
340 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
341 clock-names = "core", "iface";
342 #address-cells = <1>;
343 #size-cells = <0>;
344 };
345
346 };
347
348 gsbi2: gsbi@12480000 {
349 status = "disabled";
350 compatible = "qcom,gsbi-v1.0.0";
351 cell-index = <2>;
352 reg = <0x12480000 0x100>;
353 clocks = <&gcc GSBI2_H_CLK>;
354 clock-names = "iface";
355 #address-cells = <1>;
356 #size-cells = <1>;
357 ranges;
358
359 syscon-tcsr = <&tcsr>;
360
361 gsbi2_i2c: i2c@124a0000 {
362 compatible = "qcom,i2c-qup-v1.1.1";
363 reg = <0x124a0000 0x1000>;
364 pinctrl-0 = <&i2c2_pins>;
365 pinctrl-1 = <&i2c2_pins_sleep>;
366 pinctrl-names = "default", "sleep";
367 interrupts = <0 196 IRQ_TYPE_NONE>;
368 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
369 clock-names = "core", "iface";
370 #address-cells = <1>;
371 #size-cells = <0>;
372 };
373 };
374
375 gsbi3: gsbi@16200000 {
376 status = "disabled";
377 compatible = "qcom,gsbi-v1.0.0";
378 cell-index = <3>;
379 reg = <0x16200000 0x100>;
380 clocks = <&gcc GSBI3_H_CLK>;
381 clock-names = "iface";
382 #address-cells = <1>;
383 #size-cells = <1>;
384 ranges;
385 gsbi3_i2c: i2c@16280000 {
386 compatible = "qcom,i2c-qup-v1.1.1";
387 pinctrl-0 = <&i2c3_pins>;
388 pinctrl-1 = <&i2c3_pins_sleep>;
389 pinctrl-names = "default", "sleep";
390 reg = <0x16280000 0x1000>;
391 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
392 clocks = <&gcc GSBI3_QUP_CLK>,
393 <&gcc GSBI3_H_CLK>;
394 clock-names = "core", "iface";
395 #address-cells = <1>;
396 #size-cells = <0>;
397 };
398 };
399
400 gsbi4: gsbi@16300000 {
401 status = "disabled";
402 compatible = "qcom,gsbi-v1.0.0";
403 cell-index = <4>;
404 reg = <0x16300000 0x03>;
405 clocks = <&gcc GSBI4_H_CLK>;
406 clock-names = "iface";
407 #address-cells = <1>;
408 #size-cells = <1>;
409 ranges;
410
411 gsbi4_i2c: i2c@16380000 {
412 compatible = "qcom,i2c-qup-v1.1.1";
413 pinctrl-0 = <&i2c4_pins>;
414 pinctrl-1 = <&i2c4_pins_sleep>;
415 pinctrl-names = "default", "sleep";
416 reg = <0x16380000 0x1000>;
417 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
418 clocks = <&gcc GSBI4_QUP_CLK>,
419 <&gcc GSBI4_H_CLK>;
420 clock-names = "core", "iface";
421 };
422 };
423
424 gsbi5: gsbi@1a200000 {
425 status = "disabled";
426 compatible = "qcom,gsbi-v1.0.0";
427 cell-index = <5>;
428 reg = <0x1a200000 0x03>;
429 clocks = <&gcc GSBI5_H_CLK>;
430 clock-names = "iface";
431 #address-cells = <1>;
432 #size-cells = <1>;
433 ranges;
434
435 gsbi5_serial: serial@1a240000 {
436 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
437 reg = <0x1a240000 0x100>,
438 <0x1a200000 0x03>;
439 interrupts = <0 154 0x0>;
440 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
441 clock-names = "core", "iface";
442 status = "disabled";
443 };
444
445 gsbi5_spi: spi@1a280000 {
446 compatible = "qcom,spi-qup-v1.1.1";
447 reg = <0x1a280000 0x1000>;
448 interrupts = <0 155 0>;
449 pinctrl-0 = <&spi5_default>;
450 pinctrl-1 = <&spi5_sleep>;
451 pinctrl-names = "default", "sleep";
452 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
453 clock-names = "core", "iface";
454 status = "disabled";
455 #address-cells = <1>;
456 #size-cells = <0>;
457 };
458 };
459
460 gsbi6: gsbi@16500000 {
461 status = "disabled";
462 compatible = "qcom,gsbi-v1.0.0";
463 cell-index = <6>;
464 reg = <0x16500000 0x03>;
465 clocks = <&gcc GSBI6_H_CLK>;
466 clock-names = "iface";
467 #address-cells = <1>;
468 #size-cells = <1>;
469 ranges;
470
471 gsbi6_serial: serial@16540000 {
472 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
473 reg = <0x16540000 0x100>,
474 <0x16500000 0x03>;
475 interrupts = <0 156 0x0>;
476 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
477 clock-names = "core", "iface";
478 status = "disabled";
479 };
480
481 gsbi6_i2c: i2c@16580000 {
482 compatible = "qcom,i2c-qup-v1.1.1";
483 pinctrl-0 = <&i2c6_pins>;
484 pinctrl-1 = <&i2c6_pins_sleep>;
485 pinctrl-names = "default", "sleep";
486 reg = <0x16580000 0x1000>;
487 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
488 clocks = <&gcc GSBI6_QUP_CLK>,
489 <&gcc GSBI6_H_CLK>;
490 clock-names = "core", "iface";
491 };
492 };
493
494 gsbi7: gsbi@16600000 {
495 status = "disabled";
496 compatible = "qcom,gsbi-v1.0.0";
497 cell-index = <7>;
498 reg = <0x16600000 0x100>;
499 clocks = <&gcc GSBI7_H_CLK>;
500 clock-names = "iface";
501 #address-cells = <1>;
502 #size-cells = <1>;
503 ranges;
504 syscon-tcsr = <&tcsr>;
505
506 gsbi7_serial: serial@16640000 {
507 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
508 reg = <0x16640000 0x1000>,
509 <0x16600000 0x1000>;
510 interrupts = <0 158 0x0>;
511 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
512 clock-names = "core", "iface";
513 status = "disabled";
514 };
515
516 gsbi7_i2c: i2c@16680000 {
517 compatible = "qcom,i2c-qup-v1.1.1";
518 pinctrl-0 = <&i2c7_pins>;
519 pinctrl-1 = <&i2c7_pins_sleep>;
520 pinctrl-names = "default", "sleep";
521 reg = <0x16680000 0x1000>;
522 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
523 clocks = <&gcc GSBI7_QUP_CLK>,
524 <&gcc GSBI7_H_CLK>;
525 clock-names = "core", "iface";
526 status = "disabled";
527 };
528 };
529
530 rng@1a500000 {
531 compatible = "qcom,prng";
532 reg = <0x1a500000 0x200>;
533 clocks = <&gcc PRNG_CLK>;
534 clock-names = "core";
535 };
536
537 qcom,ssbi@500000 {
538 compatible = "qcom,ssbi";
539 reg = <0x00500000 0x1000>;
540 qcom,controller-type = "pmic-arbiter";
541
542 pmicintc: pmic@0 {
543 compatible = "qcom,pm8921";
544 interrupt-parent = <&tlmm_pinmux>;
545 interrupts = <74 8>;
546 #interrupt-cells = <2>;
547 interrupt-controller;
548 #address-cells = <1>;
549 #size-cells = <0>;
550
551 pm8921_gpio: gpio@150 {
552
553 compatible = "qcom,pm8921-gpio",
554 "qcom,ssbi-gpio";
555 reg = <0x150>;
556 interrupts = <192 1>, <193 1>, <194 1>,
557 <195 1>, <196 1>, <197 1>,
558 <198 1>, <199 1>, <200 1>,
559 <201 1>, <202 1>, <203 1>,
560 <204 1>, <205 1>, <206 1>,
561 <207 1>, <208 1>, <209 1>,
562 <210 1>, <211 1>, <212 1>,
563 <213 1>, <214 1>, <215 1>,
564 <216 1>, <217 1>, <218 1>,
565 <219 1>, <220 1>, <221 1>,
566 <222 1>, <223 1>, <224 1>,
567 <225 1>, <226 1>, <227 1>,
568 <228 1>, <229 1>, <230 1>,
569 <231 1>, <232 1>, <233 1>,
570 <234 1>, <235 1>;
571
572 gpio-controller;
573 #gpio-cells = <2>;
574
575 };
576
577 pm8921_mpps: mpps@50 {
578 compatible = "qcom,pm8921-mpp",
579 "qcom,ssbi-mpp";
580 reg = <0x50>;
581 gpio-controller;
582 #gpio-cells = <2>;
583 interrupts =
584 <128 1>, <129 1>, <130 1>, <131 1>,
585 <132 1>, <133 1>, <134 1>, <135 1>,
586 <136 1>, <137 1>, <138 1>, <139 1>;
587 };
588
589 rtc@11d {
590 compatible = "qcom,pm8921-rtc";
591 interrupt-parent = <&pmicintc>;
592 interrupts = <39 1>;
593 reg = <0x11d>;
594 allow-set-time;
595 };
596
597 pwrkey@1c {
598 compatible = "qcom,pm8921-pwrkey";
599 reg = <0x1c>;
600 interrupt-parent = <&pmicintc>;
601 interrupts = <50 1>, <51 1>;
602 debounce = <15625>;
603 pull-up;
604 };
605 };
606 };
607
608 gcc: clock-controller@900000 {
609 compatible = "qcom,gcc-apq8064";
610 reg = <0x00900000 0x4000>;
611 #clock-cells = <1>;
612 #reset-cells = <1>;
613 };
614
615 lcc: clock-controller@28000000 {
616 compatible = "qcom,lcc-apq8064";
617 reg = <0x28000000 0x1000>;
618 #clock-cells = <1>;
619 #reset-cells = <1>;
620 };
621
622 mmcc: clock-controller@4000000 {
623 compatible = "qcom,mmcc-apq8064";
624 reg = <0x4000000 0x1000>;
625 #clock-cells = <1>;
626 #reset-cells = <1>;
627 };
628
629 l2cc: clock-controller@2011000 {
630 compatible = "syscon";
631 reg = <0x2011000 0x1000>;
632 };
633
634 rpm@108000 {
635 compatible = "qcom,rpm-apq8064";
636 reg = <0x108000 0x1000>;
637 qcom,ipc = <&l2cc 0x8 2>;
638
639 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
640 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
641 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
642 interrupt-names = "ack", "err", "wakeup";
643
644 rpmcc: clock-controller {
645 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
646 #clock-cells = <1>;
647 };
648
649 regulators {
650 compatible = "qcom,rpm-pm8921-regulators";
651
652 pm8921_s1: s1 {};
653 pm8921_s2: s2 {};
654 pm8921_s3: s3 {};
655 pm8921_s4: s4 {};
656 pm8921_s7: s7 {};
657 pm8921_s8: s8 {};
658
659 pm8921_l1: l1 {};
660 pm8921_l2: l2 {};
661 pm8921_l3: l3 {};
662 pm8921_l4: l4 {};
663 pm8921_l5: l5 {};
664 pm8921_l6: l6 {};
665 pm8921_l7: l7 {};
666 pm8921_l8: l8 {};
667 pm8921_l9: l9 {};
668 pm8921_l10: l10 {};
669 pm8921_l11: l11 {};
670 pm8921_l12: l12 {};
671 pm8921_l14: l14 {};
672 pm8921_l15: l15 {};
673 pm8921_l16: l16 {};
674 pm8921_l17: l17 {};
675 pm8921_l18: l18 {};
676 pm8921_l21: l21 {};
677 pm8921_l22: l22 {};
678 pm8921_l23: l23 {};
679 pm8921_l24: l24 {};
680 pm8921_l25: l25 {};
681 pm8921_l26: l26 {};
682 pm8921_l27: l27 {};
683 pm8921_l28: l28 {};
684 pm8921_l29: l29 {};
685
686 pm8921_lvs1: lvs1 {};
687 pm8921_lvs2: lvs2 {};
688 pm8921_lvs3: lvs3 {};
689 pm8921_lvs4: lvs4 {};
690 pm8921_lvs5: lvs5 {};
691 pm8921_lvs6: lvs6 {};
692 pm8921_lvs7: lvs7 {};
693
694 pm8921_usb_switch: usb-switch {};
695
696 pm8921_hdmi_switch: hdmi-switch {
697 bias-pull-down;
698 };
699
700 pm8921_ncp: ncp {};
701 };
702 };
703
704 usb1_phy: phy@12500000 {
705 compatible = "qcom,usb-otg-ci";
706 reg = <0x12500000 0x400>;
707 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
708 status = "disabled";
709 dr_mode = "host";
710
711 clocks = <&gcc USB_HS1_XCVR_CLK>,
712 <&gcc USB_HS1_H_CLK>;
713 clock-names = "core", "iface";
714
715 resets = <&gcc USB_HS1_RESET>;
716 reset-names = "link";
717 };
718
719 usb3_phy: phy@12520000 {
720 compatible = "qcom,usb-otg-ci";
721 reg = <0x12520000 0x400>;
722 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
723 status = "disabled";
724 dr_mode = "host";
725
726 clocks = <&gcc USB_HS3_XCVR_CLK>,
727 <&gcc USB_HS3_H_CLK>;
728 clock-names = "core", "iface";
729
730 resets = <&gcc USB_HS3_RESET>;
731 reset-names = "link";
732 };
733
734 usb4_phy: phy@12530000 {
735 compatible = "qcom,usb-otg-ci";
736 reg = <0x12530000 0x400>;
737 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
738 status = "disabled";
739 dr_mode = "host";
740
741 clocks = <&gcc USB_HS4_XCVR_CLK>,
742 <&gcc USB_HS4_H_CLK>;
743 clock-names = "core", "iface";
744
745 resets = <&gcc USB_HS4_RESET>;
746 reset-names = "link";
747 };
748
749 gadget1: gadget@12500000 {
750 compatible = "qcom,ci-hdrc";
751 reg = <0x12500000 0x400>;
752 status = "disabled";
753 dr_mode = "peripheral";
754 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
755 usb-phy = <&usb1_phy>;
756 };
757
758 usb1: usb@12500000 {
759 compatible = "qcom,ehci-host";
760 reg = <0x12500000 0x400>;
761 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
762 status = "disabled";
763 usb-phy = <&usb1_phy>;
764 };
765
766 usb3: usb@12520000 {
767 compatible = "qcom,ehci-host";
768 reg = <0x12520000 0x400>;
769 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
770 status = "disabled";
771 usb-phy = <&usb3_phy>;
772 };
773
774 usb4: usb@12530000 {
775 compatible = "qcom,ehci-host";
776 reg = <0x12530000 0x400>;
777 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
778 status = "disabled";
779 usb-phy = <&usb4_phy>;
780 };
781
782 sata_phy0: phy@1b400000 {
783 compatible = "qcom,apq8064-sata-phy";
784 status = "disabled";
785 reg = <0x1b400000 0x200>;
786 reg-names = "phy_mem";
787 clocks = <&gcc SATA_PHY_CFG_CLK>;
788 clock-names = "cfg";
789 #phy-cells = <0>;
790 };
791
792 sata0: sata@29000000 {
793 compatible = "qcom,apq8064-ahci", "generic-ahci";
794 status = "disabled";
795 reg = <0x29000000 0x180>;
796 interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
797
798 clocks = <&gcc SFAB_SATA_S_H_CLK>,
799 <&gcc SATA_H_CLK>,
800 <&gcc SATA_A_CLK>,
801 <&gcc SATA_RXOOB_CLK>,
802 <&gcc SATA_PMALIVE_CLK>;
803 clock-names = "slave_iface",
804 "iface",
805 "bus",
806 "rxoob",
807 "core_pmalive";
808
809 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
810 <&gcc SATA_PMALIVE_CLK>;
811 assigned-clock-rates = <100000000>, <100000000>;
812
813 phys = <&sata_phy0>;
814 phy-names = "sata-phy";
815 ports-implemented = <0x1>;
816 };
817
818 /* Temporary fixed regulator */
819 sdcc1bam:dma@12402000{
820 compatible = "qcom,bam-v1.3.0";
821 reg = <0x12402000 0x8000>;
822 interrupts = <0 98 0>;
823 clocks = <&gcc SDC1_H_CLK>;
824 clock-names = "bam_clk";
825 #dma-cells = <1>;
826 qcom,ee = <0>;
827 };
828
829 sdcc3bam:dma@12182000{
830 compatible = "qcom,bam-v1.3.0";
831 reg = <0x12182000 0x8000>;
832 interrupts = <0 96 0>;
833 clocks = <&gcc SDC3_H_CLK>;
834 clock-names = "bam_clk";
835 #dma-cells = <1>;
836 qcom,ee = <0>;
837 };
838
839 sdcc4bam:dma@121c2000{
840 compatible = "qcom,bam-v1.3.0";
841 reg = <0x121c2000 0x8000>;
842 interrupts = <0 95 0>;
843 clocks = <&gcc SDC4_H_CLK>;
844 clock-names = "bam_clk";
845 #dma-cells = <1>;
846 qcom,ee = <0>;
847 };
848
849 amba {
850 compatible = "simple-bus";
851 #address-cells = <1>;
852 #size-cells = <1>;
853 ranges;
854 sdcc1: sdcc@12400000 {
855 status = "disabled";
856 compatible = "arm,pl18x", "arm,primecell";
857 arm,primecell-periphid = <0x00051180>;
858 reg = <0x12400000 0x2000>;
859 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
860 interrupt-names = "cmd_irq";
861 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
862 clock-names = "mclk", "apb_pclk";
863 bus-width = <8>;
864 max-frequency = <96000000>;
865 non-removable;
866 cap-sd-highspeed;
867 cap-mmc-highspeed;
868 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
869 dma-names = "tx", "rx";
870 };
871
872 sdcc3: sdcc@12180000 {
873 compatible = "arm,pl18x", "arm,primecell";
874 arm,primecell-periphid = <0x00051180>;
875 status = "disabled";
876 reg = <0x12180000 0x2000>;
877 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
878 interrupt-names = "cmd_irq";
879 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
880 clock-names = "mclk", "apb_pclk";
881 bus-width = <4>;
882 cap-sd-highspeed;
883 cap-mmc-highspeed;
884 max-frequency = <192000000>;
885 no-1-8-v;
886 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
887 dma-names = "tx", "rx";
888 };
889
890 sdcc4: sdcc@121c0000 {
891 compatible = "arm,pl18x", "arm,primecell";
892 arm,primecell-periphid = <0x00051180>;
893 status = "disabled";
894 reg = <0x121c0000 0x2000>;
895 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
896 interrupt-names = "cmd_irq";
897 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
898 clock-names = "mclk", "apb_pclk";
899 bus-width = <4>;
900 cap-sd-highspeed;
901 cap-mmc-highspeed;
902 max-frequency = <48000000>;
903 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
904 dma-names = "tx", "rx";
905 pinctrl-names = "default";
906 pinctrl-0 = <&sdc4_gpios>;
907 };
908 };
909
910 tcsr: syscon@1a400000 {
911 compatible = "qcom,tcsr-apq8064", "syscon";
912 reg = <0x1a400000 0x100>;
913 };
914
915 pcie: pci@1b500000 {
916 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
917 reg = <0x1b500000 0x1000
918 0x1b502000 0x80
919 0x1b600000 0x100
920 0x0ff00000 0x100000>;
921 reg-names = "dbi", "elbi", "parf", "config";
922 device_type = "pci";
923 linux,pci-domain = <0>;
924 bus-range = <0x00 0xff>;
925 num-lanes = <1>;
926 #address-cells = <3>;
927 #size-cells = <2>;
928 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
929 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
930 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
931 interrupt-names = "msi";
932 #interrupt-cells = <1>;
933 interrupt-map-mask = <0 0 0 0x7>;
934 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
935 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
936 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
937 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
938 clocks = <&gcc PCIE_A_CLK>,
939 <&gcc PCIE_H_CLK>,
940 <&gcc PCIE_PHY_REF_CLK>;
941 clock-names = "core", "iface", "phy";
942 resets = <&gcc PCIE_ACLK_RESET>,
943 <&gcc PCIE_HCLK_RESET>,
944 <&gcc PCIE_POR_RESET>,
945 <&gcc PCIE_PCI_RESET>,
946 <&gcc PCIE_PHY_RESET>;
947 reset-names = "axi", "ahb", "por", "pci", "phy";
948 status = "disabled";
949 };
950 };
951 };
952 #include "qcom-apq8064-pins.dtsi"
Linux kernel - Deliverables
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