3 /include/ "skeleton.dtsi"
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
10 model = "Qualcomm MSM8660";
11 compatible = "qcom,msm8660";
12 interrupt-parent = <&intc>;
19 compatible = "qcom,scorpion";
20 enable-method = "qcom,gcc-msm8660";
23 next-level-cache = <&L2>;
27 compatible = "qcom,scorpion";
28 enable-method = "qcom,gcc-msm8660";
31 next-level-cache = <&L2>;
41 compatible = "qcom,scorpion-mp-pmu";
42 interrupts = <1 9 0x304>;
47 compatible = "fixed-clock";
49 clock-frequency = <19200000>;
53 compatible = "fixed-clock";
55 clock-frequency = <27000000>;
59 compatible = "fixed-clock";
61 clock-frequency = <32768>;
69 compatible = "simple-bus";
71 intc: interrupt-controller@2080000 {
72 compatible = "qcom,msm-8660-qgic";
74 #interrupt-cells = <3>;
75 reg = < 0x02080000 0x1000 >,
76 < 0x02081000 0x1000 >;
80 compatible = "qcom,scss-timer", "qcom,msm-timer";
81 interrupts = <1 0 0x301>,
84 reg = <0x02000000 0x100>;
85 clock-frequency = <27000000>,
87 cpu-offset = <0x40000>;
90 tlmm: pinctrl@800000 {
91 compatible = "qcom,msm8660-pinctrl";
92 reg = <0x800000 0x4000>;
96 interrupts = <0 16 0x4>;
98 #interrupt-cells = <2>;
102 gcc: clock-controller@900000 {
103 compatible = "qcom,gcc-msm8660";
106 reg = <0x900000 0x4000>;
109 gsbi12: gsbi@19c00000 {
110 compatible = "qcom,gsbi-v1.0.0";
112 reg = <0x19c00000 0x100>;
113 clocks = <&gcc GSBI12_H_CLK>;
114 clock-names = "iface";
115 #address-cells = <1>;
119 syscon-tcsr = <&tcsr>;
121 gsbi12_serial: serial@19c40000 {
122 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
123 reg = <0x19c40000 0x1000>,
125 interrupts = <0 195 IRQ_TYPE_NONE>;
126 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
127 clock-names = "core", "iface";
131 gsbi12_i2c: i2c@19c80000 {
132 compatible = "qcom,i2c-qup-v1.1.1";
133 reg = <0x19c80000 0x1000>;
134 interrupts = <0 196 IRQ_TYPE_NONE>;
135 clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
136 clock-names = "core", "iface";
137 #address-cells = <1>;
144 compatible = "qcom,ssbi";
145 reg = <0x500000 0x1000>;
146 qcom,controller-type = "pmic-arbiter";
149 compatible = "qcom,pm8058";
150 interrupt-parent = <&tlmm>;
152 #interrupt-cells = <2>;
153 interrupt-controller;
154 #address-cells = <1>;
157 pm8058_gpio: gpio@150 {
158 compatible = "qcom,pm8058-gpio",
161 interrupt-parent = <&pmicintc>;
162 interrupts = <192 1>, <193 1>, <194 1>,
163 <195 1>, <196 1>, <197 1>,
164 <198 1>, <199 1>, <200 1>,
165 <201 1>, <202 1>, <203 1>,
166 <204 1>, <205 1>, <206 1>,
167 <207 1>, <208 1>, <209 1>,
168 <210 1>, <211 1>, <212 1>,
169 <213 1>, <214 1>, <215 1>,
170 <216 1>, <217 1>, <218 1>,
171 <219 1>, <220 1>, <221 1>,
172 <222 1>, <223 1>, <224 1>,
173 <225 1>, <226 1>, <227 1>,
174 <228 1>, <229 1>, <230 1>,
175 <231 1>, <232 1>, <233 1>,
182 pm8058_mpps: mpps@50 {
183 compatible = "qcom,pm8058-mpp",
188 interrupt-parent = <&pmicintc>;
190 <128 1>, <129 1>, <130 1>, <131 1>,
191 <132 1>, <133 1>, <134 1>, <135 1>,
192 <136 1>, <137 1>, <138 1>, <139 1>;
196 compatible = "qcom,pm8058-pwrkey";
198 interrupt-parent = <&pmicintc>;
199 interrupts = <50 1>, <51 1>;
205 compatible = "qcom,pm8058-keypad";
207 interrupt-parent = <&pmicintc>;
208 interrupts = <74 1>, <75 1>;
215 compatible = "qcom,pm8058-rtc";
217 interrupt-parent = <&pmicintc>;
223 compatible = "qcom,pm8058-vib";
229 l2cc: clock-controller@2082000 {
230 compatible = "syscon";
231 reg = <0x02082000 0x1000>;
235 compatible = "qcom,rpm-msm8660";
236 reg = <0x00104000 0x1000>;
237 qcom,ipc = <&l2cc 0x8 2>;
239 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
240 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
241 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
242 interrupt-names = "ack", "err", "wakeup";
243 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
246 rpmcc: clock-controller {
247 compatible = "qcom,rpmcc-apq8660", "qcom,rpmcc";
252 compatible = "qcom,rpm-pm8901-regulators";
262 /* S0 and S1 Handled as SAW regulators by SPM */
267 pm8901_lvs0: lvs0 {};
268 pm8901_lvs1: lvs1 {};
269 pm8901_lvs2: lvs2 {};
270 pm8901_lvs3: lvs3 {};
276 compatible = "qcom,rpm-pm8058-regulators";
311 pm8058_lvs0: lvs0 {};
312 pm8058_lvs1: lvs1 {};
318 /* Temporary fixed regulator */
319 vsdcc_fixed: vsdcc-regulator {
320 compatible = "regulator-fixed";
321 regulator-name = "SDCC Power";
322 regulator-min-microvolt = <2700000>;
323 regulator-max-microvolt = <2700000>;
328 compatible = "simple-bus";
329 #address-cells = <1>;
332 sdcc1: sdcc@12400000 {
334 compatible = "arm,pl18x", "arm,primecell";
335 arm,primecell-periphid = <0x00051180>;
336 reg = <0x12400000 0x8000>;
337 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
338 interrupt-names = "cmd_irq";
339 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
340 clock-names = "mclk", "apb_pclk";
342 max-frequency = <48000000>;
346 vmmc-supply = <&vsdcc_fixed>;
349 sdcc3: sdcc@12180000 {
350 compatible = "arm,pl18x", "arm,primecell";
351 arm,primecell-periphid = <0x00051180>;
353 reg = <0x12180000 0x8000>;
354 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
355 interrupt-names = "cmd_irq";
356 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
357 clock-names = "mclk", "apb_pclk";
361 max-frequency = <48000000>;
363 vmmc-supply = <&vsdcc_fixed>;
366 sdcc5: sdcc@12200000 {
367 compatible = "arm,pl18x", "arm,primecell";
368 arm,primecell-periphid = <0x00051180>;
370 reg = <0x12200000 0x8000>;
371 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
372 interrupt-names = "cmd_irq";
373 clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
374 clock-names = "mclk", "apb_pclk";
378 max-frequency = <48000000>;
379 vmmc-supply = <&vsdcc_fixed>;
383 tcsr: syscon@1a400000 {
384 compatible = "qcom,tcsr-msm8660", "syscon";
385 reg = <0x1a400000 0x100>;