arch/arm/boot/dts/rk3066a.dtsi

   1 /*
   2  * Copyright (c) 2013 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This file is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This file is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/pinctrl/rockchip.h>
  46 #include <dt-bindings/clock/rk3066a-cru.h>
  47 #include "rk3xxx.dtsi"
  48
  49 / {
  50         compatible = "rockchip,rk3066a";
  51
  52         cpus {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55                 enable-method = "rockchip,rk3066-smp";
  56
  57                 cpu0: cpu@0 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a9";
  60                         next-level-cache = <&L2>;
  61                         reg = <0x0>;
  62                         operating-points = <
  63                                 /* kHz    uV */
  64                                 1416000 1300000
  65                                 1200000 1175000
  66                                 1008000 1125000
  67                                 816000  1125000
  68                                 600000  1100000
  69                                 504000  1100000
  70                                 312000  1075000
  71                         >;
  72                         clock-latency = <40000>;
  73                         clocks = <&cru ARMCLK>;
  74                 };
  75                 cpu@1 {
  76                         device_type = "cpu";
  77                         compatible = "arm,cortex-a9";
  78                         next-level-cache = <&L2>;
  79                         reg = <0x1>;
  80                 };
  81         };
  82
  83         sram: sram@10080000 {
  84                 compatible = "mmio-sram";
  85                 reg = <0x10080000 0x10000>;
  86                 #address-cells = <1>;
  87                 #size-cells = <1>;
  88                 ranges = <0 0x10080000 0x10000>;
  89
  90                 smp-sram@0 {
  91                         compatible = "rockchip,rk3066-smp-sram";
  92                         reg = <0x0 0x50>;
  93                 };
  94         };
  95
  96         i2s0: i2s@10118000 {
  97                 compatible = "rockchip,rk3066-i2s";
  98                 reg = <0x10118000 0x2000>;
  99                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 100                 #address-cells = <1>;
 101                 #size-cells = <0>;
 102                 pinctrl-names = "default";
 103                 pinctrl-0 = <&i2s0_bus>;
 104                 dmas = <&dmac1_s 4>, <&dmac1_s 5>;
 105                 dma-names = "tx", "rx";
 106                 clock-names = "i2s_hclk", "i2s_clk";
 107                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 108                 rockchip,playback-channels = <8>;
 109                 rockchip,capture-channels = <2>;
 110                 status = "disabled";
 111         };
 112
 113         i2s1: i2s@1011a000 {
 114                 compatible = "rockchip,rk3066-i2s";
 115                 reg = <0x1011a000 0x2000>;
 116                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 117                 #address-cells = <1>;
 118                 #size-cells = <0>;
 119                 pinctrl-names = "default";
 120                 pinctrl-0 = <&i2s1_bus>;
 121                 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
 122                 dma-names = "tx", "rx";
 123                 clock-names = "i2s_hclk", "i2s_clk";
 124                 clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
 125                 rockchip,playback-channels = <2>;
 126                 rockchip,capture-channels = <2>;
 127                 status = "disabled";
 128         };
 129
 130         i2s2: i2s@1011c000 {
 131                 compatible = "rockchip,rk3066-i2s";
 132                 reg = <0x1011c000 0x2000>;
 133                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 134                 #address-cells = <1>;
 135                 #size-cells = <0>;
 136                 pinctrl-names = "default";
 137                 pinctrl-0 = <&i2s2_bus>;
 138                 dmas = <&dmac1_s 9>, <&dmac1_s 10>;
 139                 dma-names = "tx", "rx";
 140                 clock-names = "i2s_hclk", "i2s_clk";
 141                 clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
 142                 rockchip,playback-channels = <2>;
 143                 rockchip,capture-channels = <2>;
 144                 status = "disabled";
 145         };
 146
 147         cru: clock-controller@20000000 {
 148                 compatible = "rockchip,rk3066a-cru";
 149                 reg = <0x20000000 0x1000>;
 150                 rockchip,grf = <&grf>;
 151
 152                 #clock-cells = <1>;
 153                 #reset-cells = <1>;
 154         };
 155
 156         timer@2000e000 {
 157                 compatible = "snps,dw-apb-timer-osc";
 158                 reg = <0x2000e000 0x100>;
 159                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 160                 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
 161                 clock-names = "timer", "pclk";
 162         };
 163
 164         efuse: efuse@20010000 {
 165                 compatible = "rockchip,rockchip-efuse";
 166                 reg = <0x20010000 0x4000>;
 167                 #address-cells = <1>;
 168                 #size-cells = <1>;
 169                 clocks = <&cru PCLK_EFUSE>;
 170                 clock-names = "pclk_efuse";
 171
 172                 cpu_leakage: cpu_leakage@17 {
 173                         reg = <0x17 0x1>;
 174                 };
 175         };
 176
 177         timer@20038000 {
 178                 compatible = "snps,dw-apb-timer-osc";
 179                 reg = <0x20038000 0x100>;
 180                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 181                 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
 182                 clock-names = "timer", "pclk";
 183         };
 184
 185         timer@2003a000 {
 186                 compatible = "snps,dw-apb-timer-osc";
 187                 reg = <0x2003a000 0x100>;
 188                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 189                 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
 190                 clock-names = "timer", "pclk";
 191         };
 192
 193         tsadc: tsadc@20060000 {
 194                 compatible = "rockchip,rk3066-tsadc";
 195                 reg = <0x20060000 0x100>;
 196                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 197                 clock-names = "saradc", "apb_pclk";
 198                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 199                 #io-channel-cells = <1>;
 200                 status = "disabled";
 201         };
 202
 203         usbphy: phy {
 204                 compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
 205                 rockchip,grf = <&grf>;
 206                 #address-cells = <1>;
 207                 #size-cells = <0>;
 208                 status = "disabled";
 209
 210                 usbphy0: usb-phy@17c {
 211                         #phy-cells = <0>;
 212                         reg = <0x17c>;
 213                         clocks = <&cru SCLK_OTGPHY0>;
 214                         clock-names = "phyclk";
 215                         #clock-cells = <0>;
 216                 };
 217
 218                 usbphy1: usb-phy@188 {
 219                         #phy-cells = <0>;
 220                         reg = <0x188>;
 221                         clocks = <&cru SCLK_OTGPHY1>;
 222                         clock-names = "phyclk";
 223                         #clock-cells = <0>;
 224                 };
 225         };
 226
 227         pinctrl: pinctrl {
 228                 compatible = "rockchip,rk3066a-pinctrl";
 229                 rockchip,grf = <&grf>;
 230                 #address-cells = <1>;
 231                 #size-cells = <1>;
 232                 ranges;
 233
 234                 gpio0: gpio0@20034000 {
 235                         compatible = "rockchip,gpio-bank";
 236                         reg = <0x20034000 0x100>;
 237                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 238                         clocks = <&cru PCLK_GPIO0>;
 239
 240                         gpio-controller;
 241                         #gpio-cells = <2>;
 242
 243                         interrupt-controller;
 244                         #interrupt-cells = <2>;
 245                 };
 246
 247                 gpio1: gpio1@2003c000 {
 248                         compatible = "rockchip,gpio-bank";
 249                         reg = <0x2003c000 0x100>;
 250                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 251                         clocks = <&cru PCLK_GPIO1>;
 252
 253                         gpio-controller;
 254                         #gpio-cells = <2>;
 255
 256                         interrupt-controller;
 257                         #interrupt-cells = <2>;
 258                 };
 259
 260                 gpio2: gpio2@2003e000 {
 261                         compatible = "rockchip,gpio-bank";
 262                         reg = <0x2003e000 0x100>;
 263                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 264                         clocks = <&cru PCLK_GPIO2>;
 265
 266                         gpio-controller;
 267                         #gpio-cells = <2>;
 268
 269                         interrupt-controller;
 270                         #interrupt-cells = <2>;
 271                 };
 272
 273                 gpio3: gpio3@20080000 {
 274                         compatible = "rockchip,gpio-bank";
 275                         reg = <0x20080000 0x100>;
 276                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 277                         clocks = <&cru PCLK_GPIO3>;
 278
 279                         gpio-controller;
 280                         #gpio-cells = <2>;
 281
 282                         interrupt-controller;
 283                         #interrupt-cells = <2>;
 284                 };
 285
 286                 gpio4: gpio4@20084000 {
 287                         compatible = "rockchip,gpio-bank";
 288                         reg = <0x20084000 0x100>;
 289                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 290                         clocks = <&cru PCLK_GPIO4>;
 291
 292                         gpio-controller;
 293                         #gpio-cells = <2>;
 294
 295                         interrupt-controller;
 296                         #interrupt-cells = <2>;
 297                 };
 298
 299                 gpio6: gpio6@2000a000 {
 300                         compatible = "rockchip,gpio-bank";
 301                         reg = <0x2000a000 0x100>;
 302                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 303                         clocks = <&cru PCLK_GPIO6>;
 304
 305                         gpio-controller;
 306                         #gpio-cells = <2>;
 307
 308                         interrupt-controller;
 309                         #interrupt-cells = <2>;
 310                 };
 311
 312                 pcfg_pull_default: pcfg_pull_default {
 313                         bias-pull-pin-default;
 314                 };
 315
 316                 pcfg_pull_none: pcfg_pull_none {
 317                         bias-disable;
 318                 };
 319
 320                 emac {
 321                         emac_xfer: emac-xfer {
 322                                 rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
 323                                                 <RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
 324                                                 <RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
 325                                                 <RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
 326                                                 <RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
 327                                                 <RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */
 328                                                 <RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
 329                                                 <RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */
 330                         };
 331
 332                         emac_mdio: emac-mdio {
 333                                 rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */
 334                                                 <RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */
 335                         };
 336                 };
 337
 338                 emmc {
 339                         emmc_clk: emmc-clk {
 340                                 rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
 341                         };
 342
 343                         emmc_cmd: emmc-cmd {
 344                                 rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
 345                         };
 346
 347                         emmc_rst: emmc-rst {
 348                                 rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
 349                         };
 350
 351                         /*
 352                          * The data pins are shared between nandc and emmc and
 353                          * not accessible through pinctrl. Also they should've
 354                          * been already set correctly by firmware, as
 355                          * flash/emmc is the boot-device.
 356                          */
 357                 };
 358
 359                 i2c0 {
 360                         i2c0_xfer: i2c0-xfer {
 361                                 rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
 362                                                 <RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
 363                         };
 364                 };
 365
 366                 i2c1 {
 367                         i2c1_xfer: i2c1-xfer {
 368                                 rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
 369                                                 <RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
 370                         };
 371                 };
 372
 373                 i2c2 {
 374                         i2c2_xfer: i2c2-xfer {
 375                                 rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
 376                                                 <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
 377                         };
 378                 };
 379
 380                 i2c3 {
 381                         i2c3_xfer: i2c3-xfer {
 382                                 rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
 383                                                 <RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
 384                         };
 385                 };
 386
 387                 i2c4 {
 388                         i2c4_xfer: i2c4-xfer {
 389                                 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
 390                                                 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
 391                         };
 392                 };
 393
 394                 pwm0 {
 395                         pwm0_out: pwm0-out {
 396                                 rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
 397                         };
 398                 };
 399
 400                 pwm1 {
 401                         pwm1_out: pwm1-out {
 402                                 rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
 403                         };
 404                 };
 405
 406                 pwm2 {
 407                         pwm2_out: pwm2-out {
 408                                 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
 409                         };
 410                 };
 411
 412                 pwm3 {
 413                         pwm3_out: pwm3-out {
 414                                 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
 415                         };
 416                 };
 417
 418                 spi0 {
 419                         spi0_clk: spi0-clk {
 420                                 rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
 421                         };
 422                         spi0_cs0: spi0-cs0 {
 423                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
 424                         };
 425                         spi0_tx: spi0-tx {
 426                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
 427                         };
 428                         spi0_rx: spi0-rx {
 429                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
 430                         };
 431                         spi0_cs1: spi0-cs1 {
 432                                 rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
 433                         };
 434                 };
 435
 436                 spi1 {
 437                         spi1_clk: spi1-clk {
 438                                 rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
 439                         };
 440                         spi1_cs0: spi1-cs0 {
 441                                 rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
 442                         };
 443                         spi1_rx: spi1-rx {
 444                                 rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
 445                         };
 446                         spi1_tx: spi1-tx {
 447                                 rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
 448                         };
 449                         spi1_cs1: spi1-cs1 {
 450                                 rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
 451                         };
 452                 };
 453
 454                 uart0 {
 455                         uart0_xfer: uart0-xfer {
 456                                 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
 457                                                 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
 458                         };
 459
 460                         uart0_cts: uart0-cts {
 461                                 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
 462                         };
 463
 464                         uart0_rts: uart0-rts {
 465                                 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
 466                         };
 467                 };
 468
 469                 uart1 {
 470                         uart1_xfer: uart1-xfer {
 471                                 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
 472                                                 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
 473                         };
 474
 475                         uart1_cts: uart1-cts {
 476                                 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
 477                         };
 478
 479                         uart1_rts: uart1-rts {
 480                                 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
 481                         };
 482                 };
 483
 484                 uart2 {
 485                         uart2_xfer: uart2-xfer {
 486                                 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
 487                                                 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
 488                         };
 489                         /* no rts / cts for uart2 */
 490                 };
 491
 492                 uart3 {
 493                         uart3_xfer: uart3-xfer {
 494                                 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
 495                                                 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
 496                         };
 497
 498                         uart3_cts: uart3-cts {
 499                                 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
 500                         };
 501
 502                         uart3_rts: uart3-rts {
 503                                 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
 504                         };
 505                 };
 506
 507                 sd0 {
 508                         sd0_clk: sd0-clk {
 509                                 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
 510                         };
 511
 512                         sd0_cmd: sd0-cmd {
 513                                 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
 514                         };
 515
 516                         sd0_cd: sd0-cd {
 517                                 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
 518                         };
 519
 520                         sd0_wp: sd0-wp {
 521                                 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
 522                         };
 523
 524                         sd0_bus1: sd0-bus-width1 {
 525                                 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
 526                         };
 527
 528                         sd0_bus4: sd0-bus-width4 {
 529                                 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
 530                                                 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
 531                                                 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
 532                                                 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
 533                         };
 534                 };
 535
 536                 sd1 {
 537                         sd1_clk: sd1-clk {
 538                                 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
 539                         };
 540
 541                         sd1_cmd: sd1-cmd {
 542                                 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
 543                         };
 544
 545                         sd1_cd: sd1-cd {
 546                                 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
 547                         };
 548
 549                         sd1_wp: sd1-wp {
 550                                 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
 551                         };
 552
 553                         sd1_bus1: sd1-bus-width1 {
 554                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
 555                         };
 556
 557                         sd1_bus4: sd1-bus-width4 {
 558                                 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
 559                                                 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
 560                                                 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
 561                                                 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
 562                         };
 563                 };
 564
 565                 i2s0 {
 566                         i2s0_bus: i2s0-bus {
 567                                 rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
 568                                                 <RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
 569                                                 <RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
 570                                                 <RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
 571                                                 <RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
 572                                                 <RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
 573                                                 <RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
 574                                                 <RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
 575                                                 <RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
 576                         };
 577                 };
 578
 579                 i2s1 {
 580                         i2s1_bus: i2s1-bus {
 581                                 rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
 582                                                 <RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
 583                                                 <RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
 584                                                 <RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
 585                                                 <RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
 586                                                 <RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
 587                         };
 588                 };
 589
 590                 i2s2 {
 591                         i2s2_bus: i2s2-bus {
 592                                 rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
 593                                                 <RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
 594                                                 <RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
 595                                                 <RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
 596                                                 <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
 597                                                 <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
 598                         };
 599                 };
 600         };
 601 };
 602
 603 &i2c0 {
 604         pinctrl-names = "default";
 605         pinctrl-0 = <&i2c0_xfer>;
 606 };
 607
 608 &i2c1 {
 609         pinctrl-names = "default";
 610         pinctrl-0 = <&i2c1_xfer>;
 611 };
 612
 613 &i2c2 {
 614         pinctrl-names = "default";
 615         pinctrl-0 = <&i2c2_xfer>;
 616 };
 617
 618 &i2c3 {
 619         pinctrl-names = "default";
 620         pinctrl-0 = <&i2c3_xfer>;
 621 };
 622
 623 &i2c4 {
 624         pinctrl-names = "default";
 625         pinctrl-0 = <&i2c4_xfer>;
 626 };
 627
 628 &mmc0 {
 629         pinctrl-names = "default";
 630         pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
 631 };
 632
 633 &mmc1 {
 634         pinctrl-names = "default";
 635         pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
 636 };
 637
 638 &pwm0 {
 639         pinctrl-names = "default";
 640         pinctrl-0 = <&pwm0_out>;
 641 };
 642
 643 &pwm1 {
 644         pinctrl-names = "default";
 645         pinctrl-0 = <&pwm1_out>;
 646 };
 647
 648 &pwm2 {
 649         pinctrl-names = "default";
 650         pinctrl-0 = <&pwm2_out>;
 651 };
 652
 653 &pwm3 {
 654         pinctrl-names = "default";
 655         pinctrl-0 = <&pwm3_out>;
 656 };
 657
 658 &spi0 {
 659         pinctrl-names = "default";
 660         pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 661 };
 662
 663 &spi1 {
 664         pinctrl-names = "default";
 665         pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 666 };
 667
 668 &uart0 {
 669         pinctrl-names = "default";
 670         pinctrl-0 = <&uart0_xfer>;
 671 };
 672
 673 &uart1 {
 674         pinctrl-names = "default";
 675         pinctrl-0 = <&uart1_xfer>;
 676 };
 677
 678 &uart2 {
 679         pinctrl-names = "default";
 680         pinctrl-0 = <&uart2_xfer>;
 681 };
 682
 683 &uart3 {
 684         pinctrl-names = "default";
 685         pinctrl-0 = <&uart3_xfer>;
 686 };
 687
 688 &wdt {
 689         compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
 690 };
 691
 692 &emac {
 693         compatible = "rockchip,rk3066-emac";
 694 };