2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3288-cru.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/power/rk3288-power.h>
48 #include <dt-bindings/soc/rockchip,boot-mode.h>
54 compatible = "rockchip,rk3288";
56 interrupt-parent = <&gic>;
81 compatible = "arm,cortex-a12-pmu";
82 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
86 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
92 enable-method = "rockchip,rk3066-smp";
93 rockchip,pmu = <&pmu>;
97 compatible = "arm,cortex-a12";
99 resets = <&cru SRST_CORE0>;
115 #cooling-cells = <2>; /* min followed by max */
116 clock-latency = <40000>;
117 clocks = <&cru ARMCLK>;
121 compatible = "arm,cortex-a12";
123 resets = <&cru SRST_CORE1>;
127 compatible = "arm,cortex-a12";
129 resets = <&cru SRST_CORE2>;
133 compatible = "arm,cortex-a12";
135 resets = <&cru SRST_CORE3>;
140 compatible = "simple-bus";
141 #address-cells = <1>;
145 dmac_peri: dma-controller@ff250000 {
146 compatible = "arm,pl330", "arm,primecell";
147 reg = <0xff250000 0x4000>;
148 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
151 arm,pl330-broken-no-flushp;
152 clocks = <&cru ACLK_DMAC2>;
153 clock-names = "apb_pclk";
156 dmac_bus_ns: dma-controller@ff600000 {
157 compatible = "arm,pl330", "arm,primecell";
158 reg = <0xff600000 0x4000>;
159 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
162 arm,pl330-broken-no-flushp;
163 clocks = <&cru ACLK_DMAC1>;
164 clock-names = "apb_pclk";
168 dmac_bus_s: dma-controller@ffb20000 {
169 compatible = "arm,pl330", "arm,primecell";
170 reg = <0xffb20000 0x4000>;
171 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
174 arm,pl330-broken-no-flushp;
175 clocks = <&cru ACLK_DMAC1>;
176 clock-names = "apb_pclk";
181 #address-cells = <1>;
186 * The rk3288 cannot use the memory area above 0xfe000000
187 * for dma operations for some reason. While there is
188 * probably a better solution available somewhere, we
189 * haven't found it yet and while devices with 2GB of ram
190 * are not affected, this issue prevents 4GB from booting.
191 * So to make these devices at least bootable, block
192 * this area for the time being until the real solution
195 dma-unusable@fe000000 {
196 reg = <0xfe000000 0x1000000>;
201 compatible = "fixed-clock";
202 clock-frequency = <24000000>;
203 clock-output-names = "xin24m";
208 compatible = "arm,armv7-timer";
209 arm,cpu-registers-not-fw-configured;
210 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
211 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
212 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
213 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
214 clock-frequency = <24000000>;
217 timer: timer@ff810000 {
218 compatible = "rockchip,rk3288-timer";
219 reg = <0xff810000 0x20>;
220 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&xin24m>, <&cru PCLK_TIMER>;
222 clock-names = "timer", "pclk";
226 compatible = "rockchip,display-subsystem";
227 ports = <&vopl_out>, <&vopb_out>;
230 sdmmc: dwmmc@ff0c0000 {
231 compatible = "rockchip,rk3288-dw-mshc";
232 clock-freq-min-max = <400000 150000000>;
233 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
234 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
235 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
236 fifo-depth = <0x100>;
237 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
238 reg = <0xff0c0000 0x4000>;
242 sdio0: dwmmc@ff0d0000 {
243 compatible = "rockchip,rk3288-dw-mshc";
244 clock-freq-min-max = <400000 150000000>;
245 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
246 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
247 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
248 fifo-depth = <0x100>;
249 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
250 reg = <0xff0d0000 0x4000>;
254 sdio1: dwmmc@ff0e0000 {
255 compatible = "rockchip,rk3288-dw-mshc";
256 clock-freq-min-max = <400000 150000000>;
257 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
258 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
259 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
260 fifo-depth = <0x100>;
261 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
262 reg = <0xff0e0000 0x4000>;
266 emmc: dwmmc@ff0f0000 {
267 compatible = "rockchip,rk3288-dw-mshc";
268 clock-freq-min-max = <400000 150000000>;
269 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
270 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
271 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
272 fifo-depth = <0x100>;
273 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
274 reg = <0xff0f0000 0x4000>;
278 saradc: saradc@ff100000 {
279 compatible = "rockchip,saradc";
280 reg = <0xff100000 0x100>;
281 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
282 #io-channel-cells = <1>;
283 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
284 clock-names = "saradc", "apb_pclk";
285 resets = <&cru SRST_SARADC>;
286 reset-names = "saradc-apb";
291 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
292 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
293 clock-names = "spiclk", "apb_pclk";
294 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
295 dma-names = "tx", "rx";
296 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
297 pinctrl-names = "default";
298 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
299 reg = <0xff110000 0x1000>;
300 #address-cells = <1>;
306 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
307 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
308 clock-names = "spiclk", "apb_pclk";
309 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
310 dma-names = "tx", "rx";
311 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
312 pinctrl-names = "default";
313 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
314 reg = <0xff120000 0x1000>;
315 #address-cells = <1>;
321 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
322 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
323 clock-names = "spiclk", "apb_pclk";
324 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
325 dma-names = "tx", "rx";
326 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
327 pinctrl-names = "default";
328 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
329 reg = <0xff130000 0x1000>;
330 #address-cells = <1>;
336 compatible = "rockchip,rk3288-i2c";
337 reg = <0xff140000 0x1000>;
338 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
339 #address-cells = <1>;
342 clocks = <&cru PCLK_I2C1>;
343 pinctrl-names = "default";
344 pinctrl-0 = <&i2c1_xfer>;
349 compatible = "rockchip,rk3288-i2c";
350 reg = <0xff150000 0x1000>;
351 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
352 #address-cells = <1>;
355 clocks = <&cru PCLK_I2C3>;
356 pinctrl-names = "default";
357 pinctrl-0 = <&i2c3_xfer>;
362 compatible = "rockchip,rk3288-i2c";
363 reg = <0xff160000 0x1000>;
364 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
365 #address-cells = <1>;
368 clocks = <&cru PCLK_I2C4>;
369 pinctrl-names = "default";
370 pinctrl-0 = <&i2c4_xfer>;
375 compatible = "rockchip,rk3288-i2c";
376 reg = <0xff170000 0x1000>;
377 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
378 #address-cells = <1>;
381 clocks = <&cru PCLK_I2C5>;
382 pinctrl-names = "default";
383 pinctrl-0 = <&i2c5_xfer>;
387 uart0: serial@ff180000 {
388 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
389 reg = <0xff180000 0x100>;
390 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
394 clock-names = "baudclk", "apb_pclk";
395 pinctrl-names = "default";
396 pinctrl-0 = <&uart0_xfer>;
400 uart1: serial@ff190000 {
401 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
402 reg = <0xff190000 0x100>;
403 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
407 clock-names = "baudclk", "apb_pclk";
408 pinctrl-names = "default";
409 pinctrl-0 = <&uart1_xfer>;
413 uart2: serial@ff690000 {
414 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
415 reg = <0xff690000 0x100>;
416 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
420 clock-names = "baudclk", "apb_pclk";
421 pinctrl-names = "default";
422 pinctrl-0 = <&uart2_xfer>;
426 uart3: serial@ff1b0000 {
427 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
428 reg = <0xff1b0000 0x100>;
429 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
433 clock-names = "baudclk", "apb_pclk";
434 pinctrl-names = "default";
435 pinctrl-0 = <&uart3_xfer>;
439 uart4: serial@ff1c0000 {
440 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
441 reg = <0xff1c0000 0x100>;
442 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
446 clock-names = "baudclk", "apb_pclk";
447 pinctrl-names = "default";
448 pinctrl-0 = <&uart4_xfer>;
453 reserve_thermal: reserve_thermal {
454 polling-delay-passive = <1000>; /* milliseconds */
455 polling-delay = <5000>; /* milliseconds */
457 thermal-sensors = <&tsadc 0>;
460 cpu_thermal: cpu_thermal {
461 polling-delay-passive = <100>; /* milliseconds */
462 polling-delay = <5000>; /* milliseconds */
464 thermal-sensors = <&tsadc 1>;
467 cpu_alert0: cpu_alert0 {
468 temperature = <70000>; /* millicelsius */
469 hysteresis = <2000>; /* millicelsius */
472 cpu_alert1: cpu_alert1 {
473 temperature = <75000>; /* millicelsius */
474 hysteresis = <2000>; /* millicelsius */
478 temperature = <90000>; /* millicelsius */
479 hysteresis = <2000>; /* millicelsius */
486 trip = <&cpu_alert0>;
488 <&cpu0 THERMAL_NO_LIMIT 6>;
491 trip = <&cpu_alert1>;
493 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
498 gpu_thermal: gpu_thermal {
499 polling-delay-passive = <100>; /* milliseconds */
500 polling-delay = <5000>; /* milliseconds */
502 thermal-sensors = <&tsadc 2>;
505 gpu_alert0: gpu_alert0 {
506 temperature = <70000>; /* millicelsius */
507 hysteresis = <2000>; /* millicelsius */
511 temperature = <90000>; /* millicelsius */
512 hysteresis = <2000>; /* millicelsius */
519 trip = <&gpu_alert0>;
521 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
527 tsadc: tsadc@ff280000 {
528 compatible = "rockchip,rk3288-tsadc";
529 reg = <0xff280000 0x100>;
530 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
532 clock-names = "tsadc", "apb_pclk";
533 resets = <&cru SRST_TSADC>;
534 reset-names = "tsadc-apb";
535 pinctrl-names = "init", "default", "sleep";
536 pinctrl-0 = <&otp_gpio>;
537 pinctrl-1 = <&otp_out>;
538 pinctrl-2 = <&otp_gpio>;
539 #thermal-sensor-cells = <1>;
540 rockchip,hw-tshut-temp = <95000>;
544 gmac: ethernet@ff290000 {
545 compatible = "rockchip,rk3288-gmac";
546 reg = <0xff290000 0x10000>;
547 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
548 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
549 interrupt-names = "macirq", "eth_wake_irq";
550 rockchip,grf = <&grf>;
551 clocks = <&cru SCLK_MAC>,
552 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
553 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
554 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
555 clock-names = "stmmaceth",
556 "mac_clk_rx", "mac_clk_tx",
557 "clk_mac_ref", "clk_mac_refout",
558 "aclk_mac", "pclk_mac";
559 resets = <&cru SRST_MAC>;
560 reset-names = "stmmaceth";
564 usb_host0_ehci: usb@ff500000 {
565 compatible = "generic-ehci";
566 reg = <0xff500000 0x100>;
567 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
568 clocks = <&cru HCLK_USBHOST0>;
569 clock-names = "usbhost";
575 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
577 usb_host1: usb@ff540000 {
578 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
580 reg = <0xff540000 0x40000>;
581 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&cru HCLK_USBHOST1>;
586 phy-names = "usb2-phy";
590 usb_otg: usb@ff580000 {
591 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
593 reg = <0xff580000 0x40000>;
594 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&cru HCLK_OTG0>;
598 g-np-tx-fifo-size = <16>;
599 g-rx-fifo-size = <275>;
600 g-tx-fifo-size = <256 128 128 64 64 32>;
603 phy-names = "usb2-phy";
607 usb_hsic: usb@ff5c0000 {
608 compatible = "generic-ehci";
609 reg = <0xff5c0000 0x100>;
610 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
611 clocks = <&cru HCLK_HSIC>;
612 clock-names = "usbhost";
617 compatible = "rockchip,rk3288-i2c";
618 reg = <0xff650000 0x1000>;
619 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
620 #address-cells = <1>;
623 clocks = <&cru PCLK_I2C0>;
624 pinctrl-names = "default";
625 pinctrl-0 = <&i2c0_xfer>;
630 compatible = "rockchip,rk3288-i2c";
631 reg = <0xff660000 0x1000>;
632 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
633 #address-cells = <1>;
636 clocks = <&cru PCLK_I2C2>;
637 pinctrl-names = "default";
638 pinctrl-0 = <&i2c2_xfer>;
643 compatible = "rockchip,rk3288-pwm";
644 reg = <0xff680000 0x10>;
646 pinctrl-names = "default";
647 pinctrl-0 = <&pwm0_pin>;
648 clocks = <&cru PCLK_PWM>;
654 compatible = "rockchip,rk3288-pwm";
655 reg = <0xff680010 0x10>;
657 pinctrl-names = "default";
658 pinctrl-0 = <&pwm1_pin>;
659 clocks = <&cru PCLK_PWM>;
665 compatible = "rockchip,rk3288-pwm";
666 reg = <0xff680020 0x10>;
668 pinctrl-names = "default";
669 pinctrl-0 = <&pwm2_pin>;
670 clocks = <&cru PCLK_PWM>;
676 compatible = "rockchip,rk3288-pwm";
677 reg = <0xff680030 0x10>;
679 pinctrl-names = "default";
680 pinctrl-0 = <&pwm3_pin>;
681 clocks = <&cru PCLK_PWM>;
686 bus_intmem@ff700000 {
687 compatible = "mmio-sram";
688 reg = <0xff700000 0x18000>;
689 #address-cells = <1>;
691 ranges = <0 0xff700000 0x18000>;
693 compatible = "rockchip,rk3066-smp-sram";
699 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
700 reg = <0xff720000 0x1000>;
703 pmu: power-management@ff730000 {
704 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
705 reg = <0xff730000 0x100>;
707 power: power-controller {
708 compatible = "rockchip,rk3288-power-controller";
709 #power-domain-cells = <1>;
710 #address-cells = <1>;
713 assigned-clocks = <&cru SCLK_EDP_24M>;
714 assigned-clock-parents = <&xin24m>;
717 * Note: Although SCLK_* are the working clocks
718 * of device without including on the NOC, needed for
721 * The clocks on the which NOC:
722 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
723 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
724 * ACLK_RGA is on ACLK_RGA_NIU.
725 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
727 * Which clock are device clocks:
729 * *_IEP IEP:Image Enhancement Processor
730 * *_ISP ISP:Image Signal Processing
731 * *_VIP VIP:Video Input Processor
732 * *_VOP* VOP:Visual Output Processor
739 pd_vio@RK3288_PD_VIO {
740 reg = <RK3288_PD_VIO>;
741 clocks = <&cru ACLK_IEP>,
755 <&cru PCLK_EDP_CTRL>,
756 <&cru PCLK_HDMI_CTRL>,
757 <&cru PCLK_LVDS_PHY>,
758 <&cru PCLK_MIPI_CSI>,
759 <&cru PCLK_MIPI_DSI0>,
760 <&cru PCLK_MIPI_DSI1>,
769 * Note: The following 3 are HEVC(H.265) clocks,
770 * and on the ACLK_HEVC_NIU (NOC).
772 pd_hevc@RK3288_PD_HEVC {
773 reg = <RK3288_PD_HEVC>;
774 clocks = <&cru ACLK_HEVC>,
775 <&cru SCLK_HEVC_CABAC>,
776 <&cru SCLK_HEVC_CORE>;
780 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
781 * (video endecoder & decoder) clocks that on the
782 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
784 pd_video@RK3288_PD_VIDEO {
785 reg = <RK3288_PD_VIDEO>;
786 clocks = <&cru ACLK_VCODEC>,
791 * Note: ACLK_GPU is the GPU clock,
792 * and on the ACLK_GPU_NIU (NOC).
794 pd_gpu@RK3288_PD_GPU {
795 reg = <RK3288_PD_GPU>;
796 clocks = <&cru ACLK_GPU>;
801 compatible = "syscon-reboot-mode";
803 mode-normal = <BOOT_NORMAL>;
804 mode-recovery = <BOOT_RECOVERY>;
805 mode-bootloader = <BOOT_FASTBOOT>;
806 mode-loader = <BOOT_BL_DOWNLOAD>;
810 sgrf: syscon@ff740000 {
811 compatible = "rockchip,rk3288-sgrf", "syscon";
812 reg = <0xff740000 0x1000>;
815 cru: clock-controller@ff760000 {
816 compatible = "rockchip,rk3288-cru";
817 reg = <0xff760000 0x1000>;
818 rockchip,grf = <&grf>;
821 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
822 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
823 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
824 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
826 assigned-clock-rates = <594000000>, <400000000>,
827 <500000000>, <300000000>,
828 <150000000>, <75000000>,
829 <300000000>, <150000000>,
833 grf: syscon@ff770000 {
834 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
835 reg = <0xff770000 0x1000>;
838 compatible = "rockchip,rk3288-dp-phy";
839 clocks = <&cru SCLK_EDP_24M>;
845 io_domains: io-domains {
846 compatible = "rockchip,rk3288-io-voltage-domain";
851 compatible = "rockchip,rk3288-usb-phy";
852 #address-cells = <1>;
856 usbphy0: usb-phy@320 {
859 clocks = <&cru SCLK_OTGPHY0>;
860 clock-names = "phyclk";
864 usbphy1: usb-phy@334 {
867 clocks = <&cru SCLK_OTGPHY1>;
868 clock-names = "phyclk";
872 usbphy2: usb-phy@348 {
875 clocks = <&cru SCLK_OTGPHY2>;
876 clock-names = "phyclk";
882 wdt: watchdog@ff800000 {
883 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
884 reg = <0xff800000 0x100>;
885 clocks = <&cru PCLK_WDT>;
886 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
890 spdif: sound@ff88b0000 {
891 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
892 reg = <0xff8b0000 0x10000>;
893 #sound-dai-cells = <0>;
894 clock-names = "hclk", "mclk";
895 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
896 dmas = <&dmac_bus_s 3>;
898 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
899 pinctrl-names = "default";
900 pinctrl-0 = <&spdif_tx>;
901 rockchip,grf = <&grf>;
906 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
907 reg = <0xff890000 0x10000>;
908 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
909 #address-cells = <1>;
911 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
912 dma-names = "tx", "rx";
913 clock-names = "i2s_hclk", "i2s_clk";
914 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
915 pinctrl-names = "default";
916 pinctrl-0 = <&i2s0_bus>;
917 rockchip,playback-channels = <8>;
918 rockchip,capture-channels = <2>;
922 crypto: cypto-controller@ff8a0000 {
923 compatible = "rockchip,rk3288-crypto";
924 reg = <0xff8a0000 0x4000>;
925 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
926 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
927 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
928 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
929 resets = <&cru SRST_CRYPTO>;
930 reset-names = "crypto-rst";
935 compatible = "rockchip,rk3288-vop";
936 reg = <0xff930000 0x19c>;
937 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
938 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
939 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
940 power-domains = <&power RK3288_PD_VIO>;
941 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
942 reset-names = "axi", "ahb", "dclk";
943 iommus = <&vopb_mmu>;
947 #address-cells = <1>;
950 vopb_out_hdmi: endpoint@0 {
952 remote-endpoint = <&hdmi_in_vopb>;
955 vopb_out_edp: endpoint@1 {
957 remote-endpoint = <&edp_in_vopb>;
960 vopb_out_mipi: endpoint@2 {
962 remote-endpoint = <&mipi_in_vopb>;
967 vopb_mmu: iommu@ff930300 {
968 compatible = "rockchip,iommu";
969 reg = <0xff930300 0x100>;
970 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
971 interrupt-names = "vopb_mmu";
972 power-domains = <&power RK3288_PD_VIO>;
978 compatible = "rockchip,rk3288-vop";
979 reg = <0xff940000 0x19c>;
980 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
981 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
982 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
983 power-domains = <&power RK3288_PD_VIO>;
984 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
985 reset-names = "axi", "ahb", "dclk";
986 iommus = <&vopl_mmu>;
990 #address-cells = <1>;
993 vopl_out_hdmi: endpoint@0 {
995 remote-endpoint = <&hdmi_in_vopl>;
998 vopl_out_edp: endpoint@1 {
1000 remote-endpoint = <&edp_in_vopl>;
1003 vopl_out_mipi: endpoint@2 {
1005 remote-endpoint = <&mipi_in_vopl>;
1010 vopl_mmu: iommu@ff940300 {
1011 compatible = "rockchip,iommu";
1012 reg = <0xff940300 0x100>;
1013 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1014 interrupt-names = "vopl_mmu";
1015 power-domains = <&power RK3288_PD_VIO>;
1017 status = "disabled";
1020 mipi_dsi: mipi@ff960000 {
1021 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1022 reg = <0xff960000 0x4000>;
1023 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1024 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1025 clock-names = "ref", "pclk";
1026 power-domains = <&power RK3288_PD_VIO>;
1027 rockchip,grf = <&grf>;
1028 #address-cells = <1>;
1030 status = "disabled";
1034 #address-cells = <1>;
1036 mipi_in_vopb: endpoint@0 {
1038 remote-endpoint = <&vopb_out_mipi>;
1040 mipi_in_vopl: endpoint@1 {
1042 remote-endpoint = <&vopl_out_mipi>;
1049 compatible = "rockchip,rk3288-dp";
1050 reg = <0xff970000 0x4000>;
1051 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1052 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1053 clock-names = "dp", "pclk";
1056 resets = <&cru SRST_EDP>;
1058 rockchip,grf = <&grf>;
1059 status = "disabled";
1062 #address-cells = <1>;
1066 #address-cells = <1>;
1068 edp_in_vopb: endpoint@0 {
1070 remote-endpoint = <&vopb_out_edp>;
1072 edp_in_vopl: endpoint@1 {
1074 remote-endpoint = <&vopl_out_edp>;
1080 hdmi: hdmi@ff980000 {
1081 compatible = "rockchip,rk3288-dw-hdmi";
1082 reg = <0xff980000 0x20000>;
1084 rockchip,grf = <&grf>;
1085 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1086 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1087 clock-names = "iahb", "isfr";
1088 power-domains = <&power RK3288_PD_VIO>;
1089 status = "disabled";
1093 #address-cells = <1>;
1095 hdmi_in_vopb: endpoint@0 {
1097 remote-endpoint = <&vopb_out_hdmi>;
1099 hdmi_in_vopl: endpoint@1 {
1101 remote-endpoint = <&vopl_out_hdmi>;
1107 gic: interrupt-controller@ffc01000 {
1108 compatible = "arm,gic-400";
1109 interrupt-controller;
1110 #interrupt-cells = <3>;
1111 #address-cells = <0>;
1113 reg = <0xffc01000 0x1000>,
1114 <0xffc02000 0x1000>,
1115 <0xffc04000 0x2000>,
1116 <0xffc06000 0x2000>;
1117 interrupts = <GIC_PPI 9 0xf04>;
1120 efuse: efuse@ffb40000 {
1121 compatible = "rockchip,rockchip-efuse";
1122 reg = <0xffb40000 0x20>;
1123 #address-cells = <1>;
1125 clocks = <&cru PCLK_EFUSE256>;
1126 clock-names = "pclk_efuse";
1128 cpu_leakage: cpu_leakage@17 {
1134 compatible = "rockchip,rk3288-pinctrl";
1135 rockchip,grf = <&grf>;
1136 rockchip,pmu = <&pmu>;
1137 #address-cells = <1>;
1141 gpio0: gpio0@ff750000 {
1142 compatible = "rockchip,gpio-bank";
1143 reg = <0xff750000 0x100>;
1144 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1145 clocks = <&cru PCLK_GPIO0>;
1150 interrupt-controller;
1151 #interrupt-cells = <2>;
1154 gpio1: gpio1@ff780000 {
1155 compatible = "rockchip,gpio-bank";
1156 reg = <0xff780000 0x100>;
1157 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1158 clocks = <&cru PCLK_GPIO1>;
1163 interrupt-controller;
1164 #interrupt-cells = <2>;
1167 gpio2: gpio2@ff790000 {
1168 compatible = "rockchip,gpio-bank";
1169 reg = <0xff790000 0x100>;
1170 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1171 clocks = <&cru PCLK_GPIO2>;
1176 interrupt-controller;
1177 #interrupt-cells = <2>;
1180 gpio3: gpio3@ff7a0000 {
1181 compatible = "rockchip,gpio-bank";
1182 reg = <0xff7a0000 0x100>;
1183 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1184 clocks = <&cru PCLK_GPIO3>;
1189 interrupt-controller;
1190 #interrupt-cells = <2>;
1193 gpio4: gpio4@ff7b0000 {
1194 compatible = "rockchip,gpio-bank";
1195 reg = <0xff7b0000 0x100>;
1196 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1197 clocks = <&cru PCLK_GPIO4>;
1202 interrupt-controller;
1203 #interrupt-cells = <2>;
1206 gpio5: gpio5@ff7c0000 {
1207 compatible = "rockchip,gpio-bank";
1208 reg = <0xff7c0000 0x100>;
1209 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1210 clocks = <&cru PCLK_GPIO5>;
1215 interrupt-controller;
1216 #interrupt-cells = <2>;
1219 gpio6: gpio6@ff7d0000 {
1220 compatible = "rockchip,gpio-bank";
1221 reg = <0xff7d0000 0x100>;
1222 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1223 clocks = <&cru PCLK_GPIO6>;
1228 interrupt-controller;
1229 #interrupt-cells = <2>;
1232 gpio7: gpio7@ff7e0000 {
1233 compatible = "rockchip,gpio-bank";
1234 reg = <0xff7e0000 0x100>;
1235 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1236 clocks = <&cru PCLK_GPIO7>;
1241 interrupt-controller;
1242 #interrupt-cells = <2>;
1245 gpio8: gpio8@ff7f0000 {
1246 compatible = "rockchip,gpio-bank";
1247 reg = <0xff7f0000 0x100>;
1248 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1249 clocks = <&cru PCLK_GPIO8>;
1254 interrupt-controller;
1255 #interrupt-cells = <2>;
1259 hdmi_ddc: hdmi-ddc {
1260 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1261 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1265 pcfg_pull_up: pcfg-pull-up {
1269 pcfg_pull_down: pcfg-pull-down {
1273 pcfg_pull_none: pcfg-pull-none {
1277 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1279 drive-strength = <12>;
1283 global_pwroff: global-pwroff {
1284 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1287 ddrio_pwroff: ddrio-pwroff {
1288 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1291 ddr0_retention: ddr0-retention {
1292 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1295 ddr1_retention: ddr1-retention {
1296 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1302 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1307 i2c0_xfer: i2c0-xfer {
1308 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1309 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1314 i2c1_xfer: i2c1-xfer {
1315 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1316 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1321 i2c2_xfer: i2c2-xfer {
1322 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1323 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1328 i2c3_xfer: i2c3-xfer {
1329 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1330 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1335 i2c4_xfer: i2c4-xfer {
1336 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1337 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1342 i2c5_xfer: i2c5-xfer {
1343 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1344 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1349 i2s0_bus: i2s0-bus {
1350 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1351 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1352 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1353 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1354 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1355 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1360 sdmmc_clk: sdmmc-clk {
1361 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1364 sdmmc_cmd: sdmmc-cmd {
1365 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1368 sdmmc_cd: sdmmc-cd {
1369 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1372 sdmmc_bus1: sdmmc-bus1 {
1373 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1376 sdmmc_bus4: sdmmc-bus4 {
1377 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1378 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1379 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1380 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1385 sdio0_bus1: sdio0-bus1 {
1386 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1389 sdio0_bus4: sdio0-bus4 {
1390 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1391 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1392 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1393 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1396 sdio0_cmd: sdio0-cmd {
1397 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1400 sdio0_clk: sdio0-clk {
1401 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1404 sdio0_cd: sdio0-cd {
1405 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1408 sdio0_wp: sdio0-wp {
1409 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1412 sdio0_pwr: sdio0-pwr {
1413 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1416 sdio0_bkpwr: sdio0-bkpwr {
1417 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1420 sdio0_int: sdio0-int {
1421 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1426 sdio1_bus1: sdio1-bus1 {
1427 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1430 sdio1_bus4: sdio1-bus4 {
1431 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1432 <3 25 4 &pcfg_pull_up>,
1433 <3 26 4 &pcfg_pull_up>,
1434 <3 27 4 &pcfg_pull_up>;
1437 sdio1_cd: sdio1-cd {
1438 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1441 sdio1_wp: sdio1-wp {
1442 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1445 sdio1_bkpwr: sdio1-bkpwr {
1446 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1449 sdio1_int: sdio1-int {
1450 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1453 sdio1_cmd: sdio1-cmd {
1454 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1457 sdio1_clk: sdio1-clk {
1458 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1461 sdio1_pwr: sdio1-pwr {
1462 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1467 emmc_clk: emmc-clk {
1468 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1471 emmc_cmd: emmc-cmd {
1472 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1475 emmc_pwr: emmc-pwr {
1476 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1479 emmc_bus1: emmc-bus1 {
1480 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1483 emmc_bus4: emmc-bus4 {
1484 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1485 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1486 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1487 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1490 emmc_bus8: emmc-bus8 {
1491 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1492 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1493 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1494 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1495 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1496 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1497 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1498 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1503 spi0_clk: spi0-clk {
1504 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1506 spi0_cs0: spi0-cs0 {
1507 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1510 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1513 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1515 spi0_cs1: spi0-cs1 {
1516 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1520 spi1_clk: spi1-clk {
1521 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1523 spi1_cs0: spi1-cs0 {
1524 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1527 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1530 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1535 spi2_cs1: spi2-cs1 {
1536 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1538 spi2_clk: spi2-clk {
1539 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1541 spi2_cs0: spi2-cs0 {
1542 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1545 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1548 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1553 uart0_xfer: uart0-xfer {
1554 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1555 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1558 uart0_cts: uart0-cts {
1559 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1562 uart0_rts: uart0-rts {
1563 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1568 uart1_xfer: uart1-xfer {
1569 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1570 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1573 uart1_cts: uart1-cts {
1574 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1577 uart1_rts: uart1-rts {
1578 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1583 uart2_xfer: uart2-xfer {
1584 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1585 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1587 /* no rts / cts for uart2 */
1591 uart3_xfer: uart3-xfer {
1592 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1593 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1596 uart3_cts: uart3-cts {
1597 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1600 uart3_rts: uart3-rts {
1601 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1606 uart4_xfer: uart4-xfer {
1607 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1608 <5 13 3 &pcfg_pull_none>;
1611 uart4_cts: uart4-cts {
1612 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1615 uart4_rts: uart4-rts {
1616 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1621 otp_gpio: otp-gpio {
1622 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1626 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1631 pwm0_pin: pwm0-pin {
1632 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1637 pwm1_pin: pwm1-pin {
1638 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1643 pwm2_pin: pwm2-pin {
1644 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1649 pwm3_pin: pwm3-pin {
1650 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1655 rgmii_pins: rgmii-pins {
1656 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1657 <3 31 3 &pcfg_pull_none>,
1658 <3 26 3 &pcfg_pull_none>,
1659 <3 27 3 &pcfg_pull_none>,
1660 <3 28 3 &pcfg_pull_none_12ma>,
1661 <3 29 3 &pcfg_pull_none_12ma>,
1662 <3 24 3 &pcfg_pull_none_12ma>,
1663 <3 25 3 &pcfg_pull_none_12ma>,
1664 <4 0 3 &pcfg_pull_none>,
1665 <4 5 3 &pcfg_pull_none>,
1666 <4 6 3 &pcfg_pull_none>,
1667 <4 9 3 &pcfg_pull_none_12ma>,
1668 <4 4 3 &pcfg_pull_none_12ma>,
1669 <4 1 3 &pcfg_pull_none>,
1670 <4 3 3 &pcfg_pull_none>;
1673 rmii_pins: rmii-pins {
1674 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1675 <3 31 3 &pcfg_pull_none>,
1676 <3 28 3 &pcfg_pull_none>,
1677 <3 29 3 &pcfg_pull_none>,
1678 <4 0 3 &pcfg_pull_none>,
1679 <4 5 3 &pcfg_pull_none>,
1680 <4 4 3 &pcfg_pull_none>,
1681 <4 1 3 &pcfg_pull_none>,
1682 <4 2 3 &pcfg_pull_none>,
1683 <4 3 3 &pcfg_pull_none>;
1688 spdif_tx: spdif-tx {
1689 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;