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Merge remote-tracking branch 'ftrace/for-next'
[deliverable/linux.git] / arch / arm / boot / dts / rk3288.dtsi
1 /*
2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
5 * whole.
6 *
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
11 *
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * Or, alternatively,
18 *
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
26 * conditions:
27 *
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
30 *
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
39 */
40
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3288-cru.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/power/rk3288-power.h>
48 #include <dt-bindings/soc/rockchip,boot-mode.h>
49
50 / {
51 #address-cells = <1>;
52 #size-cells = <1>;
53
54 compatible = "rockchip,rk3288";
55
56 interrupt-parent = <&gic>;
57
58 aliases {
59 ethernet0 = &gmac;
60 i2c0 = &i2c0;
61 i2c1 = &i2c1;
62 i2c2 = &i2c2;
63 i2c3 = &i2c3;
64 i2c4 = &i2c4;
65 i2c5 = &i2c5;
66 mshc0 = &emmc;
67 mshc1 = &sdmmc;
68 mshc2 = &sdio0;
69 mshc3 = &sdio1;
70 serial0 = &uart0;
71 serial1 = &uart1;
72 serial2 = &uart2;
73 serial3 = &uart3;
74 serial4 = &uart4;
75 spi0 = &spi0;
76 spi1 = &spi1;
77 spi2 = &spi2;
78 };
79
80 arm-pmu {
81 compatible = "arm,cortex-a12-pmu";
82 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
86 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
87 };
88
89 cpus {
90 #address-cells = <1>;
91 #size-cells = <0>;
92 enable-method = "rockchip,rk3066-smp";
93 rockchip,pmu = <&pmu>;
94
95 cpu0: cpu@500 {
96 device_type = "cpu";
97 compatible = "arm,cortex-a12";
98 reg = <0x500>;
99 resets = <&cru SRST_CORE0>;
100 operating-points = <
101 /* KHz uV */
102 1608000 1350000
103 1512000 1300000
104 1416000 1200000
105 1200000 1100000
106 1008000 1050000
107 816000 1000000
108 696000 950000
109 600000 900000
110 408000 900000
111 312000 900000
112 216000 900000
113 126000 900000
114 >;
115 #cooling-cells = <2>; /* min followed by max */
116 clock-latency = <40000>;
117 clocks = <&cru ARMCLK>;
118 };
119 cpu1: cpu@501 {
120 device_type = "cpu";
121 compatible = "arm,cortex-a12";
122 reg = <0x501>;
123 resets = <&cru SRST_CORE1>;
124 };
125 cpu2: cpu@502 {
126 device_type = "cpu";
127 compatible = "arm,cortex-a12";
128 reg = <0x502>;
129 resets = <&cru SRST_CORE2>;
130 };
131 cpu3: cpu@503 {
132 device_type = "cpu";
133 compatible = "arm,cortex-a12";
134 reg = <0x503>;
135 resets = <&cru SRST_CORE3>;
136 };
137 };
138
139 amba {
140 compatible = "simple-bus";
141 #address-cells = <1>;
142 #size-cells = <1>;
143 ranges;
144
145 dmac_peri: dma-controller@ff250000 {
146 compatible = "arm,pl330", "arm,primecell";
147 reg = <0xff250000 0x4000>;
148 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
150 #dma-cells = <1>;
151 arm,pl330-broken-no-flushp;
152 clocks = <&cru ACLK_DMAC2>;
153 clock-names = "apb_pclk";
154 };
155
156 dmac_bus_ns: dma-controller@ff600000 {
157 compatible = "arm,pl330", "arm,primecell";
158 reg = <0xff600000 0x4000>;
159 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
161 #dma-cells = <1>;
162 arm,pl330-broken-no-flushp;
163 clocks = <&cru ACLK_DMAC1>;
164 clock-names = "apb_pclk";
165 status = "disabled";
166 };
167
168 dmac_bus_s: dma-controller@ffb20000 {
169 compatible = "arm,pl330", "arm,primecell";
170 reg = <0xffb20000 0x4000>;
171 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
173 #dma-cells = <1>;
174 arm,pl330-broken-no-flushp;
175 clocks = <&cru ACLK_DMAC1>;
176 clock-names = "apb_pclk";
177 };
178 };
179
180 reserved-memory {
181 #address-cells = <1>;
182 #size-cells = <1>;
183 ranges;
184
185 /*
186 * The rk3288 cannot use the memory area above 0xfe000000
187 * for dma operations for some reason. While there is
188 * probably a better solution available somewhere, we
189 * haven't found it yet and while devices with 2GB of ram
190 * are not affected, this issue prevents 4GB from booting.
191 * So to make these devices at least bootable, block
192 * this area for the time being until the real solution
193 * is found.
194 */
195 dma-unusable@fe000000 {
196 reg = <0xfe000000 0x1000000>;
197 };
198 };
199
200 xin24m: oscillator {
201 compatible = "fixed-clock";
202 clock-frequency = <24000000>;
203 clock-output-names = "xin24m";
204 #clock-cells = <0>;
205 };
206
207 timer {
208 compatible = "arm,armv7-timer";
209 arm,cpu-registers-not-fw-configured;
210 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
211 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
212 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
213 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
214 clock-frequency = <24000000>;
215 };
216
217 timer: timer@ff810000 {
218 compatible = "rockchip,rk3288-timer";
219 reg = <0xff810000 0x20>;
220 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&xin24m>, <&cru PCLK_TIMER>;
222 clock-names = "timer", "pclk";
223 };
224
225 display-subsystem {
226 compatible = "rockchip,display-subsystem";
227 ports = <&vopl_out>, <&vopb_out>;
228 };
229
230 sdmmc: dwmmc@ff0c0000 {
231 compatible = "rockchip,rk3288-dw-mshc";
232 clock-freq-min-max = <400000 150000000>;
233 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
234 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
235 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
236 fifo-depth = <0x100>;
237 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
238 reg = <0xff0c0000 0x4000>;
239 status = "disabled";
240 };
241
242 sdio0: dwmmc@ff0d0000 {
243 compatible = "rockchip,rk3288-dw-mshc";
244 clock-freq-min-max = <400000 150000000>;
245 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
246 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
247 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
248 fifo-depth = <0x100>;
249 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
250 reg = <0xff0d0000 0x4000>;
251 status = "disabled";
252 };
253
254 sdio1: dwmmc@ff0e0000 {
255 compatible = "rockchip,rk3288-dw-mshc";
256 clock-freq-min-max = <400000 150000000>;
257 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
258 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
259 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
260 fifo-depth = <0x100>;
261 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
262 reg = <0xff0e0000 0x4000>;
263 status = "disabled";
264 };
265
266 emmc: dwmmc@ff0f0000 {
267 compatible = "rockchip,rk3288-dw-mshc";
268 clock-freq-min-max = <400000 150000000>;
269 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
270 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
271 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
272 fifo-depth = <0x100>;
273 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
274 reg = <0xff0f0000 0x4000>;
275 status = "disabled";
276 };
277
278 saradc: saradc@ff100000 {
279 compatible = "rockchip,saradc";
280 reg = <0xff100000 0x100>;
281 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
282 #io-channel-cells = <1>;
283 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
284 clock-names = "saradc", "apb_pclk";
285 resets = <&cru SRST_SARADC>;
286 reset-names = "saradc-apb";
287 status = "disabled";
288 };
289
290 spi0: spi@ff110000 {
291 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
292 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
293 clock-names = "spiclk", "apb_pclk";
294 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
295 dma-names = "tx", "rx";
296 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
297 pinctrl-names = "default";
298 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
299 reg = <0xff110000 0x1000>;
300 #address-cells = <1>;
301 #size-cells = <0>;
302 status = "disabled";
303 };
304
305 spi1: spi@ff120000 {
306 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
307 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
308 clock-names = "spiclk", "apb_pclk";
309 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
310 dma-names = "tx", "rx";
311 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
312 pinctrl-names = "default";
313 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
314 reg = <0xff120000 0x1000>;
315 #address-cells = <1>;
316 #size-cells = <0>;
317 status = "disabled";
318 };
319
320 spi2: spi@ff130000 {
321 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
322 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
323 clock-names = "spiclk", "apb_pclk";
324 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
325 dma-names = "tx", "rx";
326 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
327 pinctrl-names = "default";
328 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
329 reg = <0xff130000 0x1000>;
330 #address-cells = <1>;
331 #size-cells = <0>;
332 status = "disabled";
333 };
334
335 i2c1: i2c@ff140000 {
336 compatible = "rockchip,rk3288-i2c";
337 reg = <0xff140000 0x1000>;
338 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
339 #address-cells = <1>;
340 #size-cells = <0>;
341 clock-names = "i2c";
342 clocks = <&cru PCLK_I2C1>;
343 pinctrl-names = "default";
344 pinctrl-0 = <&i2c1_xfer>;
345 status = "disabled";
346 };
347
348 i2c3: i2c@ff150000 {
349 compatible = "rockchip,rk3288-i2c";
350 reg = <0xff150000 0x1000>;
351 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
352 #address-cells = <1>;
353 #size-cells = <0>;
354 clock-names = "i2c";
355 clocks = <&cru PCLK_I2C3>;
356 pinctrl-names = "default";
357 pinctrl-0 = <&i2c3_xfer>;
358 status = "disabled";
359 };
360
361 i2c4: i2c@ff160000 {
362 compatible = "rockchip,rk3288-i2c";
363 reg = <0xff160000 0x1000>;
364 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
365 #address-cells = <1>;
366 #size-cells = <0>;
367 clock-names = "i2c";
368 clocks = <&cru PCLK_I2C4>;
369 pinctrl-names = "default";
370 pinctrl-0 = <&i2c4_xfer>;
371 status = "disabled";
372 };
373
374 i2c5: i2c@ff170000 {
375 compatible = "rockchip,rk3288-i2c";
376 reg = <0xff170000 0x1000>;
377 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
378 #address-cells = <1>;
379 #size-cells = <0>;
380 clock-names = "i2c";
381 clocks = <&cru PCLK_I2C5>;
382 pinctrl-names = "default";
383 pinctrl-0 = <&i2c5_xfer>;
384 status = "disabled";
385 };
386
387 uart0: serial@ff180000 {
388 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
389 reg = <0xff180000 0x100>;
390 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
391 reg-shift = <2>;
392 reg-io-width = <4>;
393 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
394 clock-names = "baudclk", "apb_pclk";
395 pinctrl-names = "default";
396 pinctrl-0 = <&uart0_xfer>;
397 status = "disabled";
398 };
399
400 uart1: serial@ff190000 {
401 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
402 reg = <0xff190000 0x100>;
403 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
404 reg-shift = <2>;
405 reg-io-width = <4>;
406 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
407 clock-names = "baudclk", "apb_pclk";
408 pinctrl-names = "default";
409 pinctrl-0 = <&uart1_xfer>;
410 status = "disabled";
411 };
412
413 uart2: serial@ff690000 {
414 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
415 reg = <0xff690000 0x100>;
416 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
417 reg-shift = <2>;
418 reg-io-width = <4>;
419 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
420 clock-names = "baudclk", "apb_pclk";
421 pinctrl-names = "default";
422 pinctrl-0 = <&uart2_xfer>;
423 status = "disabled";
424 };
425
426 uart3: serial@ff1b0000 {
427 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
428 reg = <0xff1b0000 0x100>;
429 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
430 reg-shift = <2>;
431 reg-io-width = <4>;
432 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
433 clock-names = "baudclk", "apb_pclk";
434 pinctrl-names = "default";
435 pinctrl-0 = <&uart3_xfer>;
436 status = "disabled";
437 };
438
439 uart4: serial@ff1c0000 {
440 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
441 reg = <0xff1c0000 0x100>;
442 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
443 reg-shift = <2>;
444 reg-io-width = <4>;
445 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
446 clock-names = "baudclk", "apb_pclk";
447 pinctrl-names = "default";
448 pinctrl-0 = <&uart4_xfer>;
449 status = "disabled";
450 };
451
452 thermal-zones {
453 reserve_thermal: reserve_thermal {
454 polling-delay-passive = <1000>; /* milliseconds */
455 polling-delay = <5000>; /* milliseconds */
456
457 thermal-sensors = <&tsadc 0>;
458 };
459
460 cpu_thermal: cpu_thermal {
461 polling-delay-passive = <100>; /* milliseconds */
462 polling-delay = <5000>; /* milliseconds */
463
464 thermal-sensors = <&tsadc 1>;
465
466 trips {
467 cpu_alert0: cpu_alert0 {
468 temperature = <70000>; /* millicelsius */
469 hysteresis = <2000>; /* millicelsius */
470 type = "passive";
471 };
472 cpu_alert1: cpu_alert1 {
473 temperature = <75000>; /* millicelsius */
474 hysteresis = <2000>; /* millicelsius */
475 type = "passive";
476 };
477 cpu_crit: cpu_crit {
478 temperature = <90000>; /* millicelsius */
479 hysteresis = <2000>; /* millicelsius */
480 type = "critical";
481 };
482 };
483
484 cooling-maps {
485 map0 {
486 trip = <&cpu_alert0>;
487 cooling-device =
488 <&cpu0 THERMAL_NO_LIMIT 6>;
489 };
490 map1 {
491 trip = <&cpu_alert1>;
492 cooling-device =
493 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
494 };
495 };
496 };
497
498 gpu_thermal: gpu_thermal {
499 polling-delay-passive = <100>; /* milliseconds */
500 polling-delay = <5000>; /* milliseconds */
501
502 thermal-sensors = <&tsadc 2>;
503
504 trips {
505 gpu_alert0: gpu_alert0 {
506 temperature = <70000>; /* millicelsius */
507 hysteresis = <2000>; /* millicelsius */
508 type = "passive";
509 };
510 gpu_crit: gpu_crit {
511 temperature = <90000>; /* millicelsius */
512 hysteresis = <2000>; /* millicelsius */
513 type = "critical";
514 };
515 };
516
517 cooling-maps {
518 map0 {
519 trip = <&gpu_alert0>;
520 cooling-device =
521 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
522 };
523 };
524 };
525 };
526
527 tsadc: tsadc@ff280000 {
528 compatible = "rockchip,rk3288-tsadc";
529 reg = <0xff280000 0x100>;
530 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
532 clock-names = "tsadc", "apb_pclk";
533 resets = <&cru SRST_TSADC>;
534 reset-names = "tsadc-apb";
535 pinctrl-names = "init", "default", "sleep";
536 pinctrl-0 = <&otp_gpio>;
537 pinctrl-1 = <&otp_out>;
538 pinctrl-2 = <&otp_gpio>;
539 #thermal-sensor-cells = <1>;
540 rockchip,hw-tshut-temp = <95000>;
541 status = "disabled";
542 };
543
544 gmac: ethernet@ff290000 {
545 compatible = "rockchip,rk3288-gmac";
546 reg = <0xff290000 0x10000>;
547 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
548 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
549 interrupt-names = "macirq", "eth_wake_irq";
550 rockchip,grf = <&grf>;
551 clocks = <&cru SCLK_MAC>,
552 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
553 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
554 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
555 clock-names = "stmmaceth",
556 "mac_clk_rx", "mac_clk_tx",
557 "clk_mac_ref", "clk_mac_refout",
558 "aclk_mac", "pclk_mac";
559 resets = <&cru SRST_MAC>;
560 reset-names = "stmmaceth";
561 status = "disabled";
562 };
563
564 usb_host0_ehci: usb@ff500000 {
565 compatible = "generic-ehci";
566 reg = <0xff500000 0x100>;
567 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
568 clocks = <&cru HCLK_USBHOST0>;
569 clock-names = "usbhost";
570 phys = <&usbphy1>;
571 phy-names = "usb";
572 status = "disabled";
573 };
574
575 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
576
577 usb_host1: usb@ff540000 {
578 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
579 "snps,dwc2";
580 reg = <0xff540000 0x40000>;
581 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&cru HCLK_USBHOST1>;
583 clock-names = "otg";
584 dr_mode = "host";
585 phys = <&usbphy2>;
586 phy-names = "usb2-phy";
587 status = "disabled";
588 };
589
590 usb_otg: usb@ff580000 {
591 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
592 "snps,dwc2";
593 reg = <0xff580000 0x40000>;
594 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&cru HCLK_OTG0>;
596 clock-names = "otg";
597 dr_mode = "otg";
598 g-np-tx-fifo-size = <16>;
599 g-rx-fifo-size = <275>;
600 g-tx-fifo-size = <256 128 128 64 64 32>;
601 g-use-dma;
602 phys = <&usbphy0>;
603 phy-names = "usb2-phy";
604 status = "disabled";
605 };
606
607 usb_hsic: usb@ff5c0000 {
608 compatible = "generic-ehci";
609 reg = <0xff5c0000 0x100>;
610 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
611 clocks = <&cru HCLK_HSIC>;
612 clock-names = "usbhost";
613 status = "disabled";
614 };
615
616 i2c0: i2c@ff650000 {
617 compatible = "rockchip,rk3288-i2c";
618 reg = <0xff650000 0x1000>;
619 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
620 #address-cells = <1>;
621 #size-cells = <0>;
622 clock-names = "i2c";
623 clocks = <&cru PCLK_I2C0>;
624 pinctrl-names = "default";
625 pinctrl-0 = <&i2c0_xfer>;
626 status = "disabled";
627 };
628
629 i2c2: i2c@ff660000 {
630 compatible = "rockchip,rk3288-i2c";
631 reg = <0xff660000 0x1000>;
632 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
633 #address-cells = <1>;
634 #size-cells = <0>;
635 clock-names = "i2c";
636 clocks = <&cru PCLK_I2C2>;
637 pinctrl-names = "default";
638 pinctrl-0 = <&i2c2_xfer>;
639 status = "disabled";
640 };
641
642 pwm0: pwm@ff680000 {
643 compatible = "rockchip,rk3288-pwm";
644 reg = <0xff680000 0x10>;
645 #pwm-cells = <3>;
646 pinctrl-names = "default";
647 pinctrl-0 = <&pwm0_pin>;
648 clocks = <&cru PCLK_PWM>;
649 clock-names = "pwm";
650 status = "disabled";
651 };
652
653 pwm1: pwm@ff680010 {
654 compatible = "rockchip,rk3288-pwm";
655 reg = <0xff680010 0x10>;
656 #pwm-cells = <3>;
657 pinctrl-names = "default";
658 pinctrl-0 = <&pwm1_pin>;
659 clocks = <&cru PCLK_PWM>;
660 clock-names = "pwm";
661 status = "disabled";
662 };
663
664 pwm2: pwm@ff680020 {
665 compatible = "rockchip,rk3288-pwm";
666 reg = <0xff680020 0x10>;
667 #pwm-cells = <3>;
668 pinctrl-names = "default";
669 pinctrl-0 = <&pwm2_pin>;
670 clocks = <&cru PCLK_PWM>;
671 clock-names = "pwm";
672 status = "disabled";
673 };
674
675 pwm3: pwm@ff680030 {
676 compatible = "rockchip,rk3288-pwm";
677 reg = <0xff680030 0x10>;
678 #pwm-cells = <2>;
679 pinctrl-names = "default";
680 pinctrl-0 = <&pwm3_pin>;
681 clocks = <&cru PCLK_PWM>;
682 clock-names = "pwm";
683 status = "disabled";
684 };
685
686 bus_intmem@ff700000 {
687 compatible = "mmio-sram";
688 reg = <0xff700000 0x18000>;
689 #address-cells = <1>;
690 #size-cells = <1>;
691 ranges = <0 0xff700000 0x18000>;
692 smp-sram@0 {
693 compatible = "rockchip,rk3066-smp-sram";
694 reg = <0x00 0x10>;
695 };
696 };
697
698 sram@ff720000 {
699 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
700 reg = <0xff720000 0x1000>;
701 };
702
703 pmu: power-management@ff730000 {
704 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
705 reg = <0xff730000 0x100>;
706
707 power: power-controller {
708 compatible = "rockchip,rk3288-power-controller";
709 #power-domain-cells = <1>;
710 #address-cells = <1>;
711 #size-cells = <0>;
712
713 assigned-clocks = <&cru SCLK_EDP_24M>;
714 assigned-clock-parents = <&xin24m>;
715
716 /*
717 * Note: Although SCLK_* are the working clocks
718 * of device without including on the NOC, needed for
719 * synchronous reset.
720 *
721 * The clocks on the which NOC:
722 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
723 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
724 * ACLK_RGA is on ACLK_RGA_NIU.
725 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
726 *
727 * Which clock are device clocks:
728 * clocks devices
729 * *_IEP IEP:Image Enhancement Processor
730 * *_ISP ISP:Image Signal Processing
731 * *_VIP VIP:Video Input Processor
732 * *_VOP* VOP:Visual Output Processor
733 * *_RGA RGA
734 * *_EDP* EDP
735 * *_LVDS_* LVDS
736 * *_HDMI HDMI
737 * *_MIPI_* MIPI
738 */
739 pd_vio@RK3288_PD_VIO {
740 reg = <RK3288_PD_VIO>;
741 clocks = <&cru ACLK_IEP>,
742 <&cru ACLK_ISP>,
743 <&cru ACLK_RGA>,
744 <&cru ACLK_VIP>,
745 <&cru ACLK_VOP0>,
746 <&cru ACLK_VOP1>,
747 <&cru DCLK_VOP0>,
748 <&cru DCLK_VOP1>,
749 <&cru HCLK_IEP>,
750 <&cru HCLK_ISP>,
751 <&cru HCLK_RGA>,
752 <&cru HCLK_VIP>,
753 <&cru HCLK_VOP0>,
754 <&cru HCLK_VOP1>,
755 <&cru PCLK_EDP_CTRL>,
756 <&cru PCLK_HDMI_CTRL>,
757 <&cru PCLK_LVDS_PHY>,
758 <&cru PCLK_MIPI_CSI>,
759 <&cru PCLK_MIPI_DSI0>,
760 <&cru PCLK_MIPI_DSI1>,
761 <&cru SCLK_EDP_24M>,
762 <&cru SCLK_EDP>,
763 <&cru SCLK_ISP_JPE>,
764 <&cru SCLK_ISP>,
765 <&cru SCLK_RGA>;
766 };
767
768 /*
769 * Note: The following 3 are HEVC(H.265) clocks,
770 * and on the ACLK_HEVC_NIU (NOC).
771 */
772 pd_hevc@RK3288_PD_HEVC {
773 reg = <RK3288_PD_HEVC>;
774 clocks = <&cru ACLK_HEVC>,
775 <&cru SCLK_HEVC_CABAC>,
776 <&cru SCLK_HEVC_CORE>;
777 };
778
779 /*
780 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
781 * (video endecoder & decoder) clocks that on the
782 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
783 */
784 pd_video@RK3288_PD_VIDEO {
785 reg = <RK3288_PD_VIDEO>;
786 clocks = <&cru ACLK_VCODEC>,
787 <&cru HCLK_VCODEC>;
788 };
789
790 /*
791 * Note: ACLK_GPU is the GPU clock,
792 * and on the ACLK_GPU_NIU (NOC).
793 */
794 pd_gpu@RK3288_PD_GPU {
795 reg = <RK3288_PD_GPU>;
796 clocks = <&cru ACLK_GPU>;
797 };
798 };
799
800 reboot-mode {
801 compatible = "syscon-reboot-mode";
802 offset = <0x94>;
803 mode-normal = <BOOT_NORMAL>;
804 mode-recovery = <BOOT_RECOVERY>;
805 mode-bootloader = <BOOT_FASTBOOT>;
806 mode-loader = <BOOT_BL_DOWNLOAD>;
807 };
808 };
809
810 sgrf: syscon@ff740000 {
811 compatible = "rockchip,rk3288-sgrf", "syscon";
812 reg = <0xff740000 0x1000>;
813 };
814
815 cru: clock-controller@ff760000 {
816 compatible = "rockchip,rk3288-cru";
817 reg = <0xff760000 0x1000>;
818 rockchip,grf = <&grf>;
819 #clock-cells = <1>;
820 #reset-cells = <1>;
821 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
822 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
823 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
824 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
825 <&cru PCLK_PERI>;
826 assigned-clock-rates = <594000000>, <400000000>,
827 <500000000>, <300000000>,
828 <150000000>, <75000000>,
829 <300000000>, <150000000>,
830 <75000000>;
831 };
832
833 grf: syscon@ff770000 {
834 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
835 reg = <0xff770000 0x1000>;
836
837 edp_phy: edp-phy {
838 compatible = "rockchip,rk3288-dp-phy";
839 clocks = <&cru SCLK_EDP_24M>;
840 clock-names = "24m";
841 #phy-cells = <0>;
842 status = "disabled";
843 };
844
845 io_domains: io-domains {
846 compatible = "rockchip,rk3288-io-voltage-domain";
847 status = "disabled";
848 };
849
850 usbphy: usbphy {
851 compatible = "rockchip,rk3288-usb-phy";
852 #address-cells = <1>;
853 #size-cells = <0>;
854 status = "disabled";
855
856 usbphy0: usb-phy@320 {
857 #phy-cells = <0>;
858 reg = <0x320>;
859 clocks = <&cru SCLK_OTGPHY0>;
860 clock-names = "phyclk";
861 #clock-cells = <0>;
862 };
863
864 usbphy1: usb-phy@334 {
865 #phy-cells = <0>;
866 reg = <0x334>;
867 clocks = <&cru SCLK_OTGPHY1>;
868 clock-names = "phyclk";
869 #clock-cells = <0>;
870 };
871
872 usbphy2: usb-phy@348 {
873 #phy-cells = <0>;
874 reg = <0x348>;
875 clocks = <&cru SCLK_OTGPHY2>;
876 clock-names = "phyclk";
877 #clock-cells = <0>;
878 };
879 };
880 };
881
882 wdt: watchdog@ff800000 {
883 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
884 reg = <0xff800000 0x100>;
885 clocks = <&cru PCLK_WDT>;
886 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
887 status = "disabled";
888 };
889
890 spdif: sound@ff88b0000 {
891 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
892 reg = <0xff8b0000 0x10000>;
893 #sound-dai-cells = <0>;
894 clock-names = "hclk", "mclk";
895 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
896 dmas = <&dmac_bus_s 3>;
897 dma-names = "tx";
898 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
899 pinctrl-names = "default";
900 pinctrl-0 = <&spdif_tx>;
901 rockchip,grf = <&grf>;
902 status = "disabled";
903 };
904
905 i2s: i2s@ff890000 {
906 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
907 reg = <0xff890000 0x10000>;
908 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
909 #address-cells = <1>;
910 #size-cells = <0>;
911 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
912 dma-names = "tx", "rx";
913 clock-names = "i2s_hclk", "i2s_clk";
914 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
915 pinctrl-names = "default";
916 pinctrl-0 = <&i2s0_bus>;
917 rockchip,playback-channels = <8>;
918 rockchip,capture-channels = <2>;
919 status = "disabled";
920 };
921
922 crypto: cypto-controller@ff8a0000 {
923 compatible = "rockchip,rk3288-crypto";
924 reg = <0xff8a0000 0x4000>;
925 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
926 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
927 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
928 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
929 resets = <&cru SRST_CRYPTO>;
930 reset-names = "crypto-rst";
931 status = "okay";
932 };
933
934 vopb: vop@ff930000 {
935 compatible = "rockchip,rk3288-vop";
936 reg = <0xff930000 0x19c>;
937 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
938 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
939 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
940 power-domains = <&power RK3288_PD_VIO>;
941 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
942 reset-names = "axi", "ahb", "dclk";
943 iommus = <&vopb_mmu>;
944 status = "disabled";
945
946 vopb_out: port {
947 #address-cells = <1>;
948 #size-cells = <0>;
949
950 vopb_out_hdmi: endpoint@0 {
951 reg = <0>;
952 remote-endpoint = <&hdmi_in_vopb>;
953 };
954
955 vopb_out_edp: endpoint@1 {
956 reg = <1>;
957 remote-endpoint = <&edp_in_vopb>;
958 };
959
960 vopb_out_mipi: endpoint@2 {
961 reg = <2>;
962 remote-endpoint = <&mipi_in_vopb>;
963 };
964 };
965 };
966
967 vopb_mmu: iommu@ff930300 {
968 compatible = "rockchip,iommu";
969 reg = <0xff930300 0x100>;
970 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
971 interrupt-names = "vopb_mmu";
972 power-domains = <&power RK3288_PD_VIO>;
973 #iommu-cells = <0>;
974 status = "disabled";
975 };
976
977 vopl: vop@ff940000 {
978 compatible = "rockchip,rk3288-vop";
979 reg = <0xff940000 0x19c>;
980 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
981 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
982 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
983 power-domains = <&power RK3288_PD_VIO>;
984 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
985 reset-names = "axi", "ahb", "dclk";
986 iommus = <&vopl_mmu>;
987 status = "disabled";
988
989 vopl_out: port {
990 #address-cells = <1>;
991 #size-cells = <0>;
992
993 vopl_out_hdmi: endpoint@0 {
994 reg = <0>;
995 remote-endpoint = <&hdmi_in_vopl>;
996 };
997
998 vopl_out_edp: endpoint@1 {
999 reg = <1>;
1000 remote-endpoint = <&edp_in_vopl>;
1001 };
1002
1003 vopl_out_mipi: endpoint@2 {
1004 reg = <2>;
1005 remote-endpoint = <&mipi_in_vopl>;
1006 };
1007 };
1008 };
1009
1010 vopl_mmu: iommu@ff940300 {
1011 compatible = "rockchip,iommu";
1012 reg = <0xff940300 0x100>;
1013 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1014 interrupt-names = "vopl_mmu";
1015 power-domains = <&power RK3288_PD_VIO>;
1016 #iommu-cells = <0>;
1017 status = "disabled";
1018 };
1019
1020 mipi_dsi: mipi@ff960000 {
1021 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1022 reg = <0xff960000 0x4000>;
1023 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1024 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1025 clock-names = "ref", "pclk";
1026 power-domains = <&power RK3288_PD_VIO>;
1027 rockchip,grf = <&grf>;
1028 #address-cells = <1>;
1029 #size-cells = <0>;
1030 status = "disabled";
1031
1032 ports {
1033 mipi_in: port {
1034 #address-cells = <1>;
1035 #size-cells = <0>;
1036 mipi_in_vopb: endpoint@0 {
1037 reg = <0>;
1038 remote-endpoint = <&vopb_out_mipi>;
1039 };
1040 mipi_in_vopl: endpoint@1 {
1041 reg = <1>;
1042 remote-endpoint = <&vopl_out_mipi>;
1043 };
1044 };
1045 };
1046 };
1047
1048 edp: dp@ff970000 {
1049 compatible = "rockchip,rk3288-dp";
1050 reg = <0xff970000 0x4000>;
1051 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1052 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1053 clock-names = "dp", "pclk";
1054 phys = <&edp_phy>;
1055 phy-names = "dp";
1056 resets = <&cru SRST_EDP>;
1057 reset-names = "dp";
1058 rockchip,grf = <&grf>;
1059 status = "disabled";
1060
1061 ports {
1062 #address-cells = <1>;
1063 #size-cells = <0>;
1064 edp_in: port@0 {
1065 reg = <0>;
1066 #address-cells = <1>;
1067 #size-cells = <0>;
1068 edp_in_vopb: endpoint@0 {
1069 reg = <0>;
1070 remote-endpoint = <&vopb_out_edp>;
1071 };
1072 edp_in_vopl: endpoint@1 {
1073 reg = <1>;
1074 remote-endpoint = <&vopl_out_edp>;
1075 };
1076 };
1077 };
1078 };
1079
1080 hdmi: hdmi@ff980000 {
1081 compatible = "rockchip,rk3288-dw-hdmi";
1082 reg = <0xff980000 0x20000>;
1083 reg-io-width = <4>;
1084 rockchip,grf = <&grf>;
1085 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1086 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1087 clock-names = "iahb", "isfr";
1088 power-domains = <&power RK3288_PD_VIO>;
1089 status = "disabled";
1090
1091 ports {
1092 hdmi_in: port {
1093 #address-cells = <1>;
1094 #size-cells = <0>;
1095 hdmi_in_vopb: endpoint@0 {
1096 reg = <0>;
1097 remote-endpoint = <&vopb_out_hdmi>;
1098 };
1099 hdmi_in_vopl: endpoint@1 {
1100 reg = <1>;
1101 remote-endpoint = <&vopl_out_hdmi>;
1102 };
1103 };
1104 };
1105 };
1106
1107 gic: interrupt-controller@ffc01000 {
1108 compatible = "arm,gic-400";
1109 interrupt-controller;
1110 #interrupt-cells = <3>;
1111 #address-cells = <0>;
1112
1113 reg = <0xffc01000 0x1000>,
1114 <0xffc02000 0x1000>,
1115 <0xffc04000 0x2000>,
1116 <0xffc06000 0x2000>;
1117 interrupts = <GIC_PPI 9 0xf04>;
1118 };
1119
1120 efuse: efuse@ffb40000 {
1121 compatible = "rockchip,rockchip-efuse";
1122 reg = <0xffb40000 0x20>;
1123 #address-cells = <1>;
1124 #size-cells = <1>;
1125 clocks = <&cru PCLK_EFUSE256>;
1126 clock-names = "pclk_efuse";
1127
1128 cpu_leakage: cpu_leakage@17 {
1129 reg = <0x17 0x1>;
1130 };
1131 };
1132
1133 pinctrl: pinctrl {
1134 compatible = "rockchip,rk3288-pinctrl";
1135 rockchip,grf = <&grf>;
1136 rockchip,pmu = <&pmu>;
1137 #address-cells = <1>;
1138 #size-cells = <1>;
1139 ranges;
1140
1141 gpio0: gpio0@ff750000 {
1142 compatible = "rockchip,gpio-bank";
1143 reg = <0xff750000 0x100>;
1144 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1145 clocks = <&cru PCLK_GPIO0>;
1146
1147 gpio-controller;
1148 #gpio-cells = <2>;
1149
1150 interrupt-controller;
1151 #interrupt-cells = <2>;
1152 };
1153
1154 gpio1: gpio1@ff780000 {
1155 compatible = "rockchip,gpio-bank";
1156 reg = <0xff780000 0x100>;
1157 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1158 clocks = <&cru PCLK_GPIO1>;
1159
1160 gpio-controller;
1161 #gpio-cells = <2>;
1162
1163 interrupt-controller;
1164 #interrupt-cells = <2>;
1165 };
1166
1167 gpio2: gpio2@ff790000 {
1168 compatible = "rockchip,gpio-bank";
1169 reg = <0xff790000 0x100>;
1170 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1171 clocks = <&cru PCLK_GPIO2>;
1172
1173 gpio-controller;
1174 #gpio-cells = <2>;
1175
1176 interrupt-controller;
1177 #interrupt-cells = <2>;
1178 };
1179
1180 gpio3: gpio3@ff7a0000 {
1181 compatible = "rockchip,gpio-bank";
1182 reg = <0xff7a0000 0x100>;
1183 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1184 clocks = <&cru PCLK_GPIO3>;
1185
1186 gpio-controller;
1187 #gpio-cells = <2>;
1188
1189 interrupt-controller;
1190 #interrupt-cells = <2>;
1191 };
1192
1193 gpio4: gpio4@ff7b0000 {
1194 compatible = "rockchip,gpio-bank";
1195 reg = <0xff7b0000 0x100>;
1196 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1197 clocks = <&cru PCLK_GPIO4>;
1198
1199 gpio-controller;
1200 #gpio-cells = <2>;
1201
1202 interrupt-controller;
1203 #interrupt-cells = <2>;
1204 };
1205
1206 gpio5: gpio5@ff7c0000 {
1207 compatible = "rockchip,gpio-bank";
1208 reg = <0xff7c0000 0x100>;
1209 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1210 clocks = <&cru PCLK_GPIO5>;
1211
1212 gpio-controller;
1213 #gpio-cells = <2>;
1214
1215 interrupt-controller;
1216 #interrupt-cells = <2>;
1217 };
1218
1219 gpio6: gpio6@ff7d0000 {
1220 compatible = "rockchip,gpio-bank";
1221 reg = <0xff7d0000 0x100>;
1222 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1223 clocks = <&cru PCLK_GPIO6>;
1224
1225 gpio-controller;
1226 #gpio-cells = <2>;
1227
1228 interrupt-controller;
1229 #interrupt-cells = <2>;
1230 };
1231
1232 gpio7: gpio7@ff7e0000 {
1233 compatible = "rockchip,gpio-bank";
1234 reg = <0xff7e0000 0x100>;
1235 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1236 clocks = <&cru PCLK_GPIO7>;
1237
1238 gpio-controller;
1239 #gpio-cells = <2>;
1240
1241 interrupt-controller;
1242 #interrupt-cells = <2>;
1243 };
1244
1245 gpio8: gpio8@ff7f0000 {
1246 compatible = "rockchip,gpio-bank";
1247 reg = <0xff7f0000 0x100>;
1248 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1249 clocks = <&cru PCLK_GPIO8>;
1250
1251 gpio-controller;
1252 #gpio-cells = <2>;
1253
1254 interrupt-controller;
1255 #interrupt-cells = <2>;
1256 };
1257
1258 hdmi {
1259 hdmi_ddc: hdmi-ddc {
1260 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1261 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1262 };
1263 };
1264
1265 pcfg_pull_up: pcfg-pull-up {
1266 bias-pull-up;
1267 };
1268
1269 pcfg_pull_down: pcfg-pull-down {
1270 bias-pull-down;
1271 };
1272
1273 pcfg_pull_none: pcfg-pull-none {
1274 bias-disable;
1275 };
1276
1277 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1278 bias-disable;
1279 drive-strength = <12>;
1280 };
1281
1282 sleep {
1283 global_pwroff: global-pwroff {
1284 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1285 };
1286
1287 ddrio_pwroff: ddrio-pwroff {
1288 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1289 };
1290
1291 ddr0_retention: ddr0-retention {
1292 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1293 };
1294
1295 ddr1_retention: ddr1-retention {
1296 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1297 };
1298 };
1299
1300 edp {
1301 edp_hpd: edp-hpd {
1302 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1303 };
1304 };
1305
1306 i2c0 {
1307 i2c0_xfer: i2c0-xfer {
1308 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1309 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1310 };
1311 };
1312
1313 i2c1 {
1314 i2c1_xfer: i2c1-xfer {
1315 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1316 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1317 };
1318 };
1319
1320 i2c2 {
1321 i2c2_xfer: i2c2-xfer {
1322 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1323 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1324 };
1325 };
1326
1327 i2c3 {
1328 i2c3_xfer: i2c3-xfer {
1329 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1330 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1331 };
1332 };
1333
1334 i2c4 {
1335 i2c4_xfer: i2c4-xfer {
1336 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1337 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1338 };
1339 };
1340
1341 i2c5 {
1342 i2c5_xfer: i2c5-xfer {
1343 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1344 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1345 };
1346 };
1347
1348 i2s0 {
1349 i2s0_bus: i2s0-bus {
1350 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1351 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1352 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1353 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1354 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1355 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1356 };
1357 };
1358
1359 sdmmc {
1360 sdmmc_clk: sdmmc-clk {
1361 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1362 };
1363
1364 sdmmc_cmd: sdmmc-cmd {
1365 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1366 };
1367
1368 sdmmc_cd: sdmmc-cd {
1369 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1370 };
1371
1372 sdmmc_bus1: sdmmc-bus1 {
1373 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1374 };
1375
1376 sdmmc_bus4: sdmmc-bus4 {
1377 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1378 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1379 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1380 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1381 };
1382 };
1383
1384 sdio0 {
1385 sdio0_bus1: sdio0-bus1 {
1386 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1387 };
1388
1389 sdio0_bus4: sdio0-bus4 {
1390 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1391 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1392 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1393 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1394 };
1395
1396 sdio0_cmd: sdio0-cmd {
1397 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1398 };
1399
1400 sdio0_clk: sdio0-clk {
1401 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1402 };
1403
1404 sdio0_cd: sdio0-cd {
1405 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1406 };
1407
1408 sdio0_wp: sdio0-wp {
1409 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1410 };
1411
1412 sdio0_pwr: sdio0-pwr {
1413 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1414 };
1415
1416 sdio0_bkpwr: sdio0-bkpwr {
1417 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1418 };
1419
1420 sdio0_int: sdio0-int {
1421 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1422 };
1423 };
1424
1425 sdio1 {
1426 sdio1_bus1: sdio1-bus1 {
1427 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1428 };
1429
1430 sdio1_bus4: sdio1-bus4 {
1431 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1432 <3 25 4 &pcfg_pull_up>,
1433 <3 26 4 &pcfg_pull_up>,
1434 <3 27 4 &pcfg_pull_up>;
1435 };
1436
1437 sdio1_cd: sdio1-cd {
1438 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1439 };
1440
1441 sdio1_wp: sdio1-wp {
1442 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1443 };
1444
1445 sdio1_bkpwr: sdio1-bkpwr {
1446 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1447 };
1448
1449 sdio1_int: sdio1-int {
1450 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1451 };
1452
1453 sdio1_cmd: sdio1-cmd {
1454 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1455 };
1456
1457 sdio1_clk: sdio1-clk {
1458 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1459 };
1460
1461 sdio1_pwr: sdio1-pwr {
1462 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1463 };
1464 };
1465
1466 emmc {
1467 emmc_clk: emmc-clk {
1468 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1469 };
1470
1471 emmc_cmd: emmc-cmd {
1472 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1473 };
1474
1475 emmc_pwr: emmc-pwr {
1476 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1477 };
1478
1479 emmc_bus1: emmc-bus1 {
1480 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1481 };
1482
1483 emmc_bus4: emmc-bus4 {
1484 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1485 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1486 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1487 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1488 };
1489
1490 emmc_bus8: emmc-bus8 {
1491 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1492 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1493 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1494 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1495 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1496 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1497 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1498 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1499 };
1500 };
1501
1502 spi0 {
1503 spi0_clk: spi0-clk {
1504 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1505 };
1506 spi0_cs0: spi0-cs0 {
1507 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1508 };
1509 spi0_tx: spi0-tx {
1510 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1511 };
1512 spi0_rx: spi0-rx {
1513 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1514 };
1515 spi0_cs1: spi0-cs1 {
1516 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1517 };
1518 };
1519 spi1 {
1520 spi1_clk: spi1-clk {
1521 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1522 };
1523 spi1_cs0: spi1-cs0 {
1524 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1525 };
1526 spi1_rx: spi1-rx {
1527 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1528 };
1529 spi1_tx: spi1-tx {
1530 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1531 };
1532 };
1533
1534 spi2 {
1535 spi2_cs1: spi2-cs1 {
1536 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1537 };
1538 spi2_clk: spi2-clk {
1539 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1540 };
1541 spi2_cs0: spi2-cs0 {
1542 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1543 };
1544 spi2_rx: spi2-rx {
1545 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1546 };
1547 spi2_tx: spi2-tx {
1548 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1549 };
1550 };
1551
1552 uart0 {
1553 uart0_xfer: uart0-xfer {
1554 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1555 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1556 };
1557
1558 uart0_cts: uart0-cts {
1559 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1560 };
1561
1562 uart0_rts: uart0-rts {
1563 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1564 };
1565 };
1566
1567 uart1 {
1568 uart1_xfer: uart1-xfer {
1569 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1570 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1571 };
1572
1573 uart1_cts: uart1-cts {
1574 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1575 };
1576
1577 uart1_rts: uart1-rts {
1578 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1579 };
1580 };
1581
1582 uart2 {
1583 uart2_xfer: uart2-xfer {
1584 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1585 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1586 };
1587 /* no rts / cts for uart2 */
1588 };
1589
1590 uart3 {
1591 uart3_xfer: uart3-xfer {
1592 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1593 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1594 };
1595
1596 uart3_cts: uart3-cts {
1597 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1598 };
1599
1600 uart3_rts: uart3-rts {
1601 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1602 };
1603 };
1604
1605 uart4 {
1606 uart4_xfer: uart4-xfer {
1607 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1608 <5 13 3 &pcfg_pull_none>;
1609 };
1610
1611 uart4_cts: uart4-cts {
1612 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1613 };
1614
1615 uart4_rts: uart4-rts {
1616 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1617 };
1618 };
1619
1620 tsadc {
1621 otp_gpio: otp-gpio {
1622 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1623 };
1624
1625 otp_out: otp-out {
1626 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1627 };
1628 };
1629
1630 pwm0 {
1631 pwm0_pin: pwm0-pin {
1632 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1633 };
1634 };
1635
1636 pwm1 {
1637 pwm1_pin: pwm1-pin {
1638 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1639 };
1640 };
1641
1642 pwm2 {
1643 pwm2_pin: pwm2-pin {
1644 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1645 };
1646 };
1647
1648 pwm3 {
1649 pwm3_pin: pwm3-pin {
1650 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1651 };
1652 };
1653
1654 gmac {
1655 rgmii_pins: rgmii-pins {
1656 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1657 <3 31 3 &pcfg_pull_none>,
1658 <3 26 3 &pcfg_pull_none>,
1659 <3 27 3 &pcfg_pull_none>,
1660 <3 28 3 &pcfg_pull_none_12ma>,
1661 <3 29 3 &pcfg_pull_none_12ma>,
1662 <3 24 3 &pcfg_pull_none_12ma>,
1663 <3 25 3 &pcfg_pull_none_12ma>,
1664 <4 0 3 &pcfg_pull_none>,
1665 <4 5 3 &pcfg_pull_none>,
1666 <4 6 3 &pcfg_pull_none>,
1667 <4 9 3 &pcfg_pull_none_12ma>,
1668 <4 4 3 &pcfg_pull_none_12ma>,
1669 <4 1 3 &pcfg_pull_none>,
1670 <4 3 3 &pcfg_pull_none>;
1671 };
1672
1673 rmii_pins: rmii-pins {
1674 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1675 <3 31 3 &pcfg_pull_none>,
1676 <3 28 3 &pcfg_pull_none>,
1677 <3 29 3 &pcfg_pull_none>,
1678 <4 0 3 &pcfg_pull_none>,
1679 <4 5 3 &pcfg_pull_none>,
1680 <4 4 3 &pcfg_pull_none>,
1681 <4 1 3 &pcfg_pull_none>,
1682 <4 2 3 &pcfg_pull_none>,
1683 <4 3 3 &pcfg_pull_none>;
1684 };
1685 };
1686
1687 spdif {
1688 spdif_tx: spdif-tx {
1689 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1690 };
1691 };
1692 };
1693 };
Linux kernel - Deliverables
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