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3aad41d873d3026ad922461f24325b0eca4295d8
[deliverable/linux.git] / arch / arm / boot / dts / rk3288.dtsi
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/pinctrl/rockchip.h>
17 #include <dt-bindings/clock/rk3288-cru.h>
18 #include <dt-bindings/thermal/thermal.h>
19 #include "skeleton.dtsi"
20
21 / {
22 compatible = "rockchip,rk3288";
23
24 interrupt-parent = <&gic>;
25
26 aliases {
27 i2c0 = &i2c0;
28 i2c1 = &i2c1;
29 i2c2 = &i2c2;
30 i2c3 = &i2c3;
31 i2c4 = &i2c4;
32 i2c5 = &i2c5;
33 mshc0 = &emmc;
34 mshc1 = &sdmmc;
35 mshc2 = &sdio0;
36 mshc3 = &sdio1;
37 serial0 = &uart0;
38 serial1 = &uart1;
39 serial2 = &uart2;
40 serial3 = &uart3;
41 serial4 = &uart4;
42 spi0 = &spi0;
43 spi1 = &spi1;
44 spi2 = &spi2;
45 };
46
47 cpus {
48 #address-cells = <1>;
49 #size-cells = <0>;
50 enable-method = "rockchip,rk3066-smp";
51 rockchip,pmu = <&pmu>;
52
53 cpu0: cpu@500 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a12";
56 reg = <0x500>;
57 resets = <&cru SRST_CORE0>;
58 operating-points = <
59 /* KHz uV */
60 1608000 1350000
61 1512000 1300000
62 1416000 1200000
63 1200000 1100000
64 1008000 1050000
65 816000 1000000
66 696000 950000
67 600000 900000
68 408000 900000
69 312000 900000
70 216000 900000
71 126000 900000
72 >;
73 #cooling-cells = <2>; /* min followed by max */
74 clock-latency = <40000>;
75 clocks = <&cru ARMCLK>;
76 };
77 cpu@501 {
78 device_type = "cpu";
79 compatible = "arm,cortex-a12";
80 reg = <0x501>;
81 resets = <&cru SRST_CORE1>;
82 };
83 cpu@502 {
84 device_type = "cpu";
85 compatible = "arm,cortex-a12";
86 reg = <0x502>;
87 resets = <&cru SRST_CORE2>;
88 };
89 cpu@503 {
90 device_type = "cpu";
91 compatible = "arm,cortex-a12";
92 reg = <0x503>;
93 resets = <&cru SRST_CORE3>;
94 };
95 };
96
97 amba {
98 compatible = "arm,amba-bus";
99 #address-cells = <1>;
100 #size-cells = <1>;
101 ranges;
102
103 dmac_peri: dma-controller@ff250000 {
104 compatible = "arm,pl330", "arm,primecell";
105 reg = <0xff250000 0x4000>;
106 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
108 #dma-cells = <1>;
109 clocks = <&cru ACLK_DMAC2>;
110 clock-names = "apb_pclk";
111 };
112
113 dmac_bus_ns: dma-controller@ff600000 {
114 compatible = "arm,pl330", "arm,primecell";
115 reg = <0xff600000 0x4000>;
116 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
117 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
118 #dma-cells = <1>;
119 clocks = <&cru ACLK_DMAC1>;
120 clock-names = "apb_pclk";
121 status = "disabled";
122 };
123
124 dmac_bus_s: dma-controller@ffb20000 {
125 compatible = "arm,pl330", "arm,primecell";
126 reg = <0xffb20000 0x4000>;
127 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
129 #dma-cells = <1>;
130 clocks = <&cru ACLK_DMAC1>;
131 clock-names = "apb_pclk";
132 };
133 };
134
135 xin24m: oscillator {
136 compatible = "fixed-clock";
137 clock-frequency = <24000000>;
138 clock-output-names = "xin24m";
139 #clock-cells = <0>;
140 };
141
142 timer {
143 compatible = "arm,armv7-timer";
144 arm,cpu-registers-not-fw-configured;
145 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
146 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
147 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
148 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
149 clock-frequency = <24000000>;
150 };
151
152 sdmmc: dwmmc@ff0c0000 {
153 compatible = "rockchip,rk3288-dw-mshc";
154 clock-freq-min-max = <400000 150000000>;
155 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
156 clock-names = "biu", "ciu";
157 fifo-depth = <0x100>;
158 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
159 reg = <0xff0c0000 0x4000>;
160 status = "disabled";
161 };
162
163 sdio0: dwmmc@ff0d0000 {
164 compatible = "rockchip,rk3288-dw-mshc";
165 clock-freq-min-max = <400000 150000000>;
166 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
167 clock-names = "biu", "ciu";
168 fifo-depth = <0x100>;
169 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
170 reg = <0xff0d0000 0x4000>;
171 status = "disabled";
172 };
173
174 sdio1: dwmmc@ff0e0000 {
175 compatible = "rockchip,rk3288-dw-mshc";
176 clock-freq-min-max = <400000 150000000>;
177 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
178 clock-names = "biu", "ciu";
179 fifo-depth = <0x100>;
180 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
181 reg = <0xff0e0000 0x4000>;
182 status = "disabled";
183 };
184
185 emmc: dwmmc@ff0f0000 {
186 compatible = "rockchip,rk3288-dw-mshc";
187 clock-freq-min-max = <400000 150000000>;
188 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
189 clock-names = "biu", "ciu";
190 fifo-depth = <0x100>;
191 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
192 reg = <0xff0f0000 0x4000>;
193 status = "disabled";
194 };
195
196 saradc: saradc@ff100000 {
197 compatible = "rockchip,saradc";
198 reg = <0xff100000 0x100>;
199 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
200 #io-channel-cells = <1>;
201 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
202 clock-names = "saradc", "apb_pclk";
203 status = "disabled";
204 };
205
206 spi0: spi@ff110000 {
207 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
208 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
209 clock-names = "spiclk", "apb_pclk";
210 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
211 dma-names = "tx", "rx";
212 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
213 pinctrl-names = "default";
214 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
215 reg = <0xff110000 0x1000>;
216 #address-cells = <1>;
217 #size-cells = <0>;
218 status = "disabled";
219 };
220
221 spi1: spi@ff120000 {
222 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
223 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
224 clock-names = "spiclk", "apb_pclk";
225 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
226 dma-names = "tx", "rx";
227 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
228 pinctrl-names = "default";
229 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
230 reg = <0xff120000 0x1000>;
231 #address-cells = <1>;
232 #size-cells = <0>;
233 status = "disabled";
234 };
235
236 spi2: spi@ff130000 {
237 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
238 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
239 clock-names = "spiclk", "apb_pclk";
240 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
241 dma-names = "tx", "rx";
242 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
243 pinctrl-names = "default";
244 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
245 reg = <0xff130000 0x1000>;
246 #address-cells = <1>;
247 #size-cells = <0>;
248 status = "disabled";
249 };
250
251 i2c1: i2c@ff140000 {
252 compatible = "rockchip,rk3288-i2c";
253 reg = <0xff140000 0x1000>;
254 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
255 #address-cells = <1>;
256 #size-cells = <0>;
257 clock-names = "i2c";
258 clocks = <&cru PCLK_I2C1>;
259 pinctrl-names = "default";
260 pinctrl-0 = <&i2c1_xfer>;
261 status = "disabled";
262 };
263
264 i2c3: i2c@ff150000 {
265 compatible = "rockchip,rk3288-i2c";
266 reg = <0xff150000 0x1000>;
267 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
268 #address-cells = <1>;
269 #size-cells = <0>;
270 clock-names = "i2c";
271 clocks = <&cru PCLK_I2C3>;
272 pinctrl-names = "default";
273 pinctrl-0 = <&i2c3_xfer>;
274 status = "disabled";
275 };
276
277 i2c4: i2c@ff160000 {
278 compatible = "rockchip,rk3288-i2c";
279 reg = <0xff160000 0x1000>;
280 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
281 #address-cells = <1>;
282 #size-cells = <0>;
283 clock-names = "i2c";
284 clocks = <&cru PCLK_I2C4>;
285 pinctrl-names = "default";
286 pinctrl-0 = <&i2c4_xfer>;
287 status = "disabled";
288 };
289
290 i2c5: i2c@ff170000 {
291 compatible = "rockchip,rk3288-i2c";
292 reg = <0xff170000 0x1000>;
293 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
294 #address-cells = <1>;
295 #size-cells = <0>;
296 clock-names = "i2c";
297 clocks = <&cru PCLK_I2C5>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&i2c5_xfer>;
300 status = "disabled";
301 };
302
303 uart0: serial@ff180000 {
304 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
305 reg = <0xff180000 0x100>;
306 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
307 reg-shift = <2>;
308 reg-io-width = <4>;
309 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
310 clock-names = "baudclk", "apb_pclk";
311 pinctrl-names = "default";
312 pinctrl-0 = <&uart0_xfer>;
313 status = "disabled";
314 };
315
316 uart1: serial@ff190000 {
317 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
318 reg = <0xff190000 0x100>;
319 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
320 reg-shift = <2>;
321 reg-io-width = <4>;
322 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
323 clock-names = "baudclk", "apb_pclk";
324 pinctrl-names = "default";
325 pinctrl-0 = <&uart1_xfer>;
326 status = "disabled";
327 };
328
329 uart2: serial@ff690000 {
330 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
331 reg = <0xff690000 0x100>;
332 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
333 reg-shift = <2>;
334 reg-io-width = <4>;
335 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
336 clock-names = "baudclk", "apb_pclk";
337 pinctrl-names = "default";
338 pinctrl-0 = <&uart2_xfer>;
339 status = "disabled";
340 };
341
342 uart3: serial@ff1b0000 {
343 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
344 reg = <0xff1b0000 0x100>;
345 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
346 reg-shift = <2>;
347 reg-io-width = <4>;
348 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
349 clock-names = "baudclk", "apb_pclk";
350 pinctrl-names = "default";
351 pinctrl-0 = <&uart3_xfer>;
352 status = "disabled";
353 };
354
355 uart4: serial@ff1c0000 {
356 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
357 reg = <0xff1c0000 0x100>;
358 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
359 reg-shift = <2>;
360 reg-io-width = <4>;
361 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
362 clock-names = "baudclk", "apb_pclk";
363 pinctrl-names = "default";
364 pinctrl-0 = <&uart4_xfer>;
365 status = "disabled";
366 };
367
368 thermal-zones {
369 #include "rk3288-thermal.dtsi"
370 };
371
372 tsadc: tsadc@ff280000 {
373 compatible = "rockchip,rk3288-tsadc";
374 reg = <0xff280000 0x100>;
375 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
377 clock-names = "tsadc", "apb_pclk";
378 resets = <&cru SRST_TSADC>;
379 reset-names = "tsadc-apb";
380 pinctrl-names = "default";
381 pinctrl-0 = <&otp_out>;
382 #thermal-sensor-cells = <1>;
383 rockchip,hw-tshut-temp = <95000>;
384 status = "disabled";
385 };
386
387 usb_host0_ehci: usb@ff500000 {
388 compatible = "generic-ehci";
389 reg = <0xff500000 0x100>;
390 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&cru HCLK_USBHOST0>;
392 clock-names = "usbhost";
393 status = "disabled";
394 };
395
396 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
397
398 usb_host1: usb@ff540000 {
399 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
400 "snps,dwc2";
401 reg = <0xff540000 0x40000>;
402 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&cru HCLK_USBHOST1>;
404 clock-names = "otg";
405 status = "disabled";
406 };
407
408 usb_otg: usb@ff580000 {
409 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
410 "snps,dwc2";
411 reg = <0xff580000 0x40000>;
412 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&cru HCLK_OTG0>;
414 clock-names = "otg";
415 status = "disabled";
416 };
417
418 usb_hsic: usb@ff5c0000 {
419 compatible = "generic-ehci";
420 reg = <0xff5c0000 0x100>;
421 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&cru HCLK_HSIC>;
423 clock-names = "usbhost";
424 status = "disabled";
425 };
426
427 i2c0: i2c@ff650000 {
428 compatible = "rockchip,rk3288-i2c";
429 reg = <0xff650000 0x1000>;
430 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
431 #address-cells = <1>;
432 #size-cells = <0>;
433 clock-names = "i2c";
434 clocks = <&cru PCLK_I2C0>;
435 pinctrl-names = "default";
436 pinctrl-0 = <&i2c0_xfer>;
437 status = "disabled";
438 };
439
440 i2c2: i2c@ff660000 {
441 compatible = "rockchip,rk3288-i2c";
442 reg = <0xff660000 0x1000>;
443 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
444 #address-cells = <1>;
445 #size-cells = <0>;
446 clock-names = "i2c";
447 clocks = <&cru PCLK_I2C2>;
448 pinctrl-names = "default";
449 pinctrl-0 = <&i2c2_xfer>;
450 status = "disabled";
451 };
452
453 pwm0: pwm@ff680000 {
454 compatible = "rockchip,rk3288-pwm";
455 reg = <0xff680000 0x10>;
456 #pwm-cells = <3>;
457 pinctrl-names = "default";
458 pinctrl-0 = <&pwm0_pin>;
459 clocks = <&cru PCLK_PWM>;
460 clock-names = "pwm";
461 status = "disabled";
462 };
463
464 pwm1: pwm@ff680010 {
465 compatible = "rockchip,rk3288-pwm";
466 reg = <0xff680010 0x10>;
467 #pwm-cells = <3>;
468 pinctrl-names = "default";
469 pinctrl-0 = <&pwm1_pin>;
470 clocks = <&cru PCLK_PWM>;
471 clock-names = "pwm";
472 status = "disabled";
473 };
474
475 pwm2: pwm@ff680020 {
476 compatible = "rockchip,rk3288-pwm";
477 reg = <0xff680020 0x10>;
478 #pwm-cells = <3>;
479 pinctrl-names = "default";
480 pinctrl-0 = <&pwm2_pin>;
481 clocks = <&cru PCLK_PWM>;
482 clock-names = "pwm";
483 status = "disabled";
484 };
485
486 pwm3: pwm@ff680030 {
487 compatible = "rockchip,rk3288-pwm";
488 reg = <0xff680030 0x10>;
489 #pwm-cells = <2>;
490 pinctrl-names = "default";
491 pinctrl-0 = <&pwm3_pin>;
492 clocks = <&cru PCLK_PWM>;
493 clock-names = "pwm";
494 status = "disabled";
495 };
496
497 bus_intmem@ff700000 {
498 compatible = "mmio-sram";
499 reg = <0xff700000 0x18000>;
500 #address-cells = <1>;
501 #size-cells = <1>;
502 ranges = <0 0xff700000 0x18000>;
503 smp-sram@0 {
504 compatible = "rockchip,rk3066-smp-sram";
505 reg = <0x00 0x10>;
506 };
507 };
508
509 pmu: power-management@ff730000 {
510 compatible = "rockchip,rk3288-pmu", "syscon";
511 reg = <0xff730000 0x100>;
512 };
513
514 sgrf: syscon@ff740000 {
515 compatible = "rockchip,rk3288-sgrf", "syscon";
516 reg = <0xff740000 0x1000>;
517 };
518
519 cru: clock-controller@ff760000 {
520 compatible = "rockchip,rk3288-cru";
521 reg = <0xff760000 0x1000>;
522 rockchip,grf = <&grf>;
523 #clock-cells = <1>;
524 #reset-cells = <1>;
525 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
526 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
527 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
528 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
529 <&cru PCLK_PERI>;
530 assigned-clock-rates = <594000000>, <400000000>,
531 <500000000>, <300000000>,
532 <150000000>, <75000000>,
533 <300000000>, <150000000>,
534 <75000000>;
535 };
536
537 grf: syscon@ff770000 {
538 compatible = "rockchip,rk3288-grf", "syscon";
539 reg = <0xff770000 0x1000>;
540 };
541
542 wdt: watchdog@ff800000 {
543 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
544 reg = <0xff800000 0x100>;
545 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
546 status = "disabled";
547 };
548
549 i2s: i2s@ff890000 {
550 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
551 reg = <0xff890000 0x10000>;
552 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
553 #address-cells = <1>;
554 #size-cells = <0>;
555 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
556 dma-names = "tx", "rx";
557 clock-names = "i2s_hclk", "i2s_clk";
558 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&i2s0_bus>;
561 status = "disabled";
562 };
563
564 vopb_mmu: iommu@ff930300 {
565 compatible = "rockchip,iommu";
566 reg = <0xff930300 0x100>;
567 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
568 interrupt-names = "vopb_mmu";
569 #iommu-cells = <0>;
570 status = "disabled";
571 };
572
573 vopl_mmu: iommu@ff940300 {
574 compatible = "rockchip,iommu";
575 reg = <0xff940300 0x100>;
576 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
577 interrupt-names = "vopl_mmu";
578 #iommu-cells = <0>;
579 status = "disabled";
580 };
581
582 gic: interrupt-controller@ffc01000 {
583 compatible = "arm,gic-400";
584 interrupt-controller;
585 #interrupt-cells = <3>;
586 #address-cells = <0>;
587
588 reg = <0xffc01000 0x1000>,
589 <0xffc02000 0x1000>,
590 <0xffc04000 0x2000>,
591 <0xffc06000 0x2000>;
592 interrupts = <GIC_PPI 9 0xf04>;
593 };
594
595 pinctrl: pinctrl {
596 compatible = "rockchip,rk3288-pinctrl";
597 rockchip,grf = <&grf>;
598 rockchip,pmu = <&pmu>;
599 #address-cells = <1>;
600 #size-cells = <1>;
601 ranges;
602
603 gpio0: gpio0@ff750000 {
604 compatible = "rockchip,gpio-bank";
605 reg = <0xff750000 0x100>;
606 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&cru PCLK_GPIO0>;
608
609 gpio-controller;
610 #gpio-cells = <2>;
611
612 interrupt-controller;
613 #interrupt-cells = <2>;
614 };
615
616 gpio1: gpio1@ff780000 {
617 compatible = "rockchip,gpio-bank";
618 reg = <0xff780000 0x100>;
619 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&cru PCLK_GPIO1>;
621
622 gpio-controller;
623 #gpio-cells = <2>;
624
625 interrupt-controller;
626 #interrupt-cells = <2>;
627 };
628
629 gpio2: gpio2@ff790000 {
630 compatible = "rockchip,gpio-bank";
631 reg = <0xff790000 0x100>;
632 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
633 clocks = <&cru PCLK_GPIO2>;
634
635 gpio-controller;
636 #gpio-cells = <2>;
637
638 interrupt-controller;
639 #interrupt-cells = <2>;
640 };
641
642 gpio3: gpio3@ff7a0000 {
643 compatible = "rockchip,gpio-bank";
644 reg = <0xff7a0000 0x100>;
645 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&cru PCLK_GPIO3>;
647
648 gpio-controller;
649 #gpio-cells = <2>;
650
651 interrupt-controller;
652 #interrupt-cells = <2>;
653 };
654
655 gpio4: gpio4@ff7b0000 {
656 compatible = "rockchip,gpio-bank";
657 reg = <0xff7b0000 0x100>;
658 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&cru PCLK_GPIO4>;
660
661 gpio-controller;
662 #gpio-cells = <2>;
663
664 interrupt-controller;
665 #interrupt-cells = <2>;
666 };
667
668 gpio5: gpio5@ff7c0000 {
669 compatible = "rockchip,gpio-bank";
670 reg = <0xff7c0000 0x100>;
671 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
672 clocks = <&cru PCLK_GPIO5>;
673
674 gpio-controller;
675 #gpio-cells = <2>;
676
677 interrupt-controller;
678 #interrupt-cells = <2>;
679 };
680
681 gpio6: gpio6@ff7d0000 {
682 compatible = "rockchip,gpio-bank";
683 reg = <0xff7d0000 0x100>;
684 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&cru PCLK_GPIO6>;
686
687 gpio-controller;
688 #gpio-cells = <2>;
689
690 interrupt-controller;
691 #interrupt-cells = <2>;
692 };
693
694 gpio7: gpio7@ff7e0000 {
695 compatible = "rockchip,gpio-bank";
696 reg = <0xff7e0000 0x100>;
697 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&cru PCLK_GPIO7>;
699
700 gpio-controller;
701 #gpio-cells = <2>;
702
703 interrupt-controller;
704 #interrupt-cells = <2>;
705 };
706
707 gpio8: gpio8@ff7f0000 {
708 compatible = "rockchip,gpio-bank";
709 reg = <0xff7f0000 0x100>;
710 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&cru PCLK_GPIO8>;
712
713 gpio-controller;
714 #gpio-cells = <2>;
715
716 interrupt-controller;
717 #interrupt-cells = <2>;
718 };
719
720 pcfg_pull_up: pcfg-pull-up {
721 bias-pull-up;
722 };
723
724 pcfg_pull_down: pcfg-pull-down {
725 bias-pull-down;
726 };
727
728 pcfg_pull_none: pcfg-pull-none {
729 bias-disable;
730 };
731
732 i2c0 {
733 i2c0_xfer: i2c0-xfer {
734 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
735 <0 16 RK_FUNC_1 &pcfg_pull_none>;
736 };
737 };
738
739 i2c1 {
740 i2c1_xfer: i2c1-xfer {
741 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
742 <8 5 RK_FUNC_1 &pcfg_pull_none>;
743 };
744 };
745
746 i2c2 {
747 i2c2_xfer: i2c2-xfer {
748 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
749 <6 10 RK_FUNC_1 &pcfg_pull_none>;
750 };
751 };
752
753 i2c3 {
754 i2c3_xfer: i2c3-xfer {
755 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
756 <2 17 RK_FUNC_1 &pcfg_pull_none>;
757 };
758 };
759
760 i2c4 {
761 i2c4_xfer: i2c4-xfer {
762 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
763 <7 18 RK_FUNC_1 &pcfg_pull_none>;
764 };
765 };
766
767 i2c5 {
768 i2c5_xfer: i2c5-xfer {
769 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
770 <7 20 RK_FUNC_1 &pcfg_pull_none>;
771 };
772 };
773
774 i2s0 {
775 i2s0_bus: i2s0-bus {
776 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
777 <6 1 RK_FUNC_1 &pcfg_pull_none>,
778 <6 2 RK_FUNC_1 &pcfg_pull_none>,
779 <6 3 RK_FUNC_1 &pcfg_pull_none>,
780 <6 4 RK_FUNC_1 &pcfg_pull_none>,
781 <6 8 RK_FUNC_1 &pcfg_pull_none>;
782 };
783 };
784
785 sdmmc {
786 sdmmc_clk: sdmmc-clk {
787 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
788 };
789
790 sdmmc_cmd: sdmmc-cmd {
791 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
792 };
793
794 sdmmc_cd: sdmcc-cd {
795 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
796 };
797
798 sdmmc_bus1: sdmmc-bus1 {
799 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
800 };
801
802 sdmmc_bus4: sdmmc-bus4 {
803 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
804 <6 17 RK_FUNC_1 &pcfg_pull_up>,
805 <6 18 RK_FUNC_1 &pcfg_pull_up>,
806 <6 19 RK_FUNC_1 &pcfg_pull_up>;
807 };
808 };
809
810 sdio0 {
811 sdio0_bus1: sdio0-bus1 {
812 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
813 };
814
815 sdio0_bus4: sdio0-bus4 {
816 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
817 <4 21 RK_FUNC_1 &pcfg_pull_up>,
818 <4 22 RK_FUNC_1 &pcfg_pull_up>,
819 <4 23 RK_FUNC_1 &pcfg_pull_up>;
820 };
821
822 sdio0_cmd: sdio0-cmd {
823 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
824 };
825
826 sdio0_clk: sdio0-clk {
827 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
828 };
829
830 sdio0_cd: sdio0-cd {
831 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
832 };
833
834 sdio0_wp: sdio0-wp {
835 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
836 };
837
838 sdio0_pwr: sdio0-pwr {
839 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
840 };
841
842 sdio0_bkpwr: sdio0-bkpwr {
843 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
844 };
845
846 sdio0_int: sdio0-int {
847 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
848 };
849 };
850
851 sdio1 {
852 sdio1_bus1: sdio1-bus1 {
853 rockchip,pins = <3 24 4 &pcfg_pull_up>;
854 };
855
856 sdio1_bus4: sdio1-bus4 {
857 rockchip,pins = <3 24 4 &pcfg_pull_up>,
858 <3 25 4 &pcfg_pull_up>,
859 <3 26 4 &pcfg_pull_up>,
860 <3 27 4 &pcfg_pull_up>;
861 };
862
863 sdio1_cd: sdio1-cd {
864 rockchip,pins = <3 28 4 &pcfg_pull_up>;
865 };
866
867 sdio1_wp: sdio1-wp {
868 rockchip,pins = <3 29 4 &pcfg_pull_up>;
869 };
870
871 sdio1_bkpwr: sdio1-bkpwr {
872 rockchip,pins = <3 30 4 &pcfg_pull_up>;
873 };
874
875 sdio1_int: sdio1-int {
876 rockchip,pins = <3 31 4 &pcfg_pull_up>;
877 };
878
879 sdio1_cmd: sdio1-cmd {
880 rockchip,pins = <4 6 4 &pcfg_pull_up>;
881 };
882
883 sdio1_clk: sdio1-clk {
884 rockchip,pins = <4 7 4 &pcfg_pull_none>;
885 };
886
887 sdio1_pwr: sdio1-pwr {
888 rockchip,pins = <4 9 4 &pcfg_pull_up>;
889 };
890 };
891
892 emmc {
893 emmc_clk: emmc-clk {
894 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
895 };
896
897 emmc_cmd: emmc-cmd {
898 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
899 };
900
901 emmc_pwr: emmc-pwr {
902 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
903 };
904
905 emmc_bus1: emmc-bus1 {
906 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
907 };
908
909 emmc_bus4: emmc-bus4 {
910 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
911 <3 1 RK_FUNC_2 &pcfg_pull_up>,
912 <3 2 RK_FUNC_2 &pcfg_pull_up>,
913 <3 3 RK_FUNC_2 &pcfg_pull_up>;
914 };
915
916 emmc_bus8: emmc-bus8 {
917 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
918 <3 1 RK_FUNC_2 &pcfg_pull_up>,
919 <3 2 RK_FUNC_2 &pcfg_pull_up>,
920 <3 3 RK_FUNC_2 &pcfg_pull_up>,
921 <3 4 RK_FUNC_2 &pcfg_pull_up>,
922 <3 5 RK_FUNC_2 &pcfg_pull_up>,
923 <3 6 RK_FUNC_2 &pcfg_pull_up>,
924 <3 7 RK_FUNC_2 &pcfg_pull_up>;
925 };
926 };
927
928 spi0 {
929 spi0_clk: spi0-clk {
930 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
931 };
932 spi0_cs0: spi0-cs0 {
933 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
934 };
935 spi0_tx: spi0-tx {
936 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
937 };
938 spi0_rx: spi0-rx {
939 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
940 };
941 spi0_cs1: spi0-cs1 {
942 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
943 };
944 };
945 spi1 {
946 spi1_clk: spi1-clk {
947 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
948 };
949 spi1_cs0: spi1-cs0 {
950 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
951 };
952 spi1_rx: spi1-rx {
953 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
954 };
955 spi1_tx: spi1-tx {
956 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
957 };
958 };
959
960 spi2 {
961 spi2_cs1: spi2-cs1 {
962 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
963 };
964 spi2_clk: spi2-clk {
965 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
966 };
967 spi2_cs0: spi2-cs0 {
968 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
969 };
970 spi2_rx: spi2-rx {
971 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
972 };
973 spi2_tx: spi2-tx {
974 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
975 };
976 };
977
978 uart0 {
979 uart0_xfer: uart0-xfer {
980 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
981 <4 17 RK_FUNC_1 &pcfg_pull_none>;
982 };
983
984 uart0_cts: uart0-cts {
985 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
986 };
987
988 uart0_rts: uart0-rts {
989 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
990 };
991 };
992
993 uart1 {
994 uart1_xfer: uart1-xfer {
995 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
996 <5 9 RK_FUNC_1 &pcfg_pull_none>;
997 };
998
999 uart1_cts: uart1-cts {
1000 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1001 };
1002
1003 uart1_rts: uart1-rts {
1004 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1005 };
1006 };
1007
1008 uart2 {
1009 uart2_xfer: uart2-xfer {
1010 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1011 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1012 };
1013 /* no rts / cts for uart2 */
1014 };
1015
1016 uart3 {
1017 uart3_xfer: uart3-xfer {
1018 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1019 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1020 };
1021
1022 uart3_cts: uart3-cts {
1023 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1024 };
1025
1026 uart3_rts: uart3-rts {
1027 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1028 };
1029 };
1030
1031 uart4 {
1032 uart4_xfer: uart4-xfer {
1033 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1034 <5 13 3 &pcfg_pull_none>;
1035 };
1036
1037 uart4_cts: uart4-cts {
1038 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1039 };
1040
1041 uart4_rts: uart4-rts {
1042 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1043 };
1044 };
1045
1046 tsadc {
1047 otp_out: otp-out {
1048 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1049 };
1050 };
1051
1052 pwm0 {
1053 pwm0_pin: pwm0-pin {
1054 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1055 };
1056 };
1057
1058 pwm1 {
1059 pwm1_pin: pwm1-pin {
1060 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1061 };
1062 };
1063
1064 pwm2 {
1065 pwm2_pin: pwm2-pin {
1066 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1067 };
1068 };
1069
1070 pwm3 {
1071 pwm3_pin: pwm3-pin {
1072 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1073 };
1074 };
1075 };
1076 };
Linux kernel - Deliverables
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