arch/arm/boot/dts/socfpga.dtsi

   1 /*
   2  *  Copyright (C) 2012 Altera <www.altera.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 /include/ "skeleton.dtsi"
  19
  20 / {
  21         #address-cells = <1>;
  22         #size-cells = <1>;
  23
  24         aliases {
  25                 ethernet0 = &gmac0;
  26                 serial0 = &uart0;
  27                 serial1 = &uart1;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 cpu@0 {
  35                         compatible = "arm,cortex-a9";
  36                         device_type = "cpu";
  37                         reg = <0>;
  38                         next-level-cache = <&L2>;
  39                 };
  40                 cpu@1 {
  41                         compatible = "arm,cortex-a9";
  42                         device_type = "cpu";
  43                         reg = <1>;
  44                         next-level-cache = <&L2>;
  45                 };
  46         };
  47
  48         intc: intc@fffed000 {
  49                 compatible = "arm,cortex-a9-gic";
  50                 #interrupt-cells = <3>;
  51                 interrupt-controller;
  52                 reg = <0xfffed000 0x1000>,
  53                       <0xfffec100 0x100>;
  54         };
  55
  56         soc {
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59                 compatible = "simple-bus";
  60                 device_type = "soc";
  61                 interrupt-parent = <&intc>;
  62                 ranges;
  63
  64                 amba {
  65                         compatible = "arm,amba-bus";
  66                         #address-cells = <1>;
  67                         #size-cells = <1>;
  68                         ranges;
  69
  70                         pdma: pdma@ffe01000 {
  71                                 compatible = "arm,pl330", "arm,primecell";
  72                                 reg = <0xffe01000 0x1000>;
  73                                 interrupts = <0 180 4>;
  74                         };
  75                 };
  76
  77                 gmac0: stmmac@ff700000 {
  78                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
  79                         reg = <0xff700000 0x2000>;
  80                         interrupts = <0 115 4>;
  81                         interrupt-names = "macirq";
  82                         mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
  83                         phy-mode = "gmii";
  84                 };
  85
  86                 L2: l2-cache@fffef000 {
  87                         compatible = "arm,pl310-cache";
  88                         reg = <0xfffef000 0x1000>;
  89                         interrupts = <0 38 0x04>;
  90                         cache-unified;
  91                         cache-level = <2>;
  92                 };
  93
  94                 /* Local timer */
  95                 timer@fffec600 {
  96                         compatible = "arm,cortex-a9-twd-timer";
  97                         reg = <0xfffec600 0x100>;
  98                         interrupts = <1 13 0xf04>;
  99                 };
 100
 101                 timer0: timer@ffc08000 {
 102                         compatible = "snps,dw-apb-timer-sp";
 103                         interrupts = <0 167 4>;
 104                         clock-frequency = <200000000>;
 105                         reg = <0xffc08000 0x1000>;
 106                 };
 107
 108                 timer1: timer@ffc09000 {
 109                         compatible = "snps,dw-apb-timer-sp";
 110                         interrupts = <0 168 4>;
 111                         clock-frequency = <200000000>;
 112                         reg = <0xffc09000 0x1000>;
 113                 };
 114
 115                 timer2: timer@ffd00000 {
 116                         compatible = "snps,dw-apb-timer-osc";
 117                         interrupts = <0 169 4>;
 118                         clock-frequency = <200000000>;
 119                         reg = <0xffd00000 0x1000>;
 120                 };
 121
 122                 timer3: timer@ffd01000 {
 123                         compatible = "snps,dw-apb-timer-osc";
 124                         interrupts = <0 170 4>;
 125                         clock-frequency = <200000000>;
 126                         reg = <0xffd01000 0x1000>;
 127                 };
 128
 129                 uart0: uart@ffc02000 {
 130                         compatible = "snps,dw-apb-uart";
 131                         reg = <0xffc02000 0x1000>;
 132                         clock-frequency = <7372800>;
 133                         interrupts = <0 162 4>;
 134                         reg-shift = <2>;
 135                         reg-io-width = <4>;
 136                 };
 137
 138                 uart1: uart@ffc03000 {
 139                         compatible = "snps,dw-apb-uart";
 140                         reg = <0xffc03000 0x1000>;
 141                         clock-frequency = <7372800>;
 142                         interrupts = <0 163 4>;
 143                         reg-shift = <2>;
 144                         reg-io-width = <4>;
 145                 };
 146         };
 147 };