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ARM: dts: sun7i: Add NFC node to Allwinner A20 SoC
[deliverable/linux.git] / arch / arm / boot / dts / sun7i-a20.dtsi
1 /*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45 #include "skeleton.dtsi"
46
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
49
50 #include <dt-bindings/clock/sun4i-a10-pll2.h>
51 #include <dt-bindings/dma/sun4i-a10.h>
52 #include <dt-bindings/pinctrl/sun4i-a10.h>
53
54 / {
55 interrupt-parent = <&gic>;
56
57 aliases {
58 ethernet0 = &gmac;
59 };
60
61 chosen {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 ranges;
65
66 framebuffer@0 {
67 compatible = "allwinner,simple-framebuffer",
68 "simple-framebuffer";
69 allwinner,pipeline = "de_be0-lcd0-hdmi";
70 clocks = <&ahb_gates 36>, <&ahb_gates 43>,
71 <&ahb_gates 44>, <&de_be0_clk>,
72 <&tcon0_ch1_clk>, <&dram_gates 26>;
73 status = "disabled";
74 };
75
76 framebuffer@1 {
77 compatible = "allwinner,simple-framebuffer",
78 "simple-framebuffer";
79 allwinner,pipeline = "de_be0-lcd0";
80 clocks = <&ahb_gates 36>, <&ahb_gates 44>,
81 <&de_be0_clk>, <&tcon0_ch0_clk>,
82 <&dram_gates 26>;
83 status = "disabled";
84 };
85
86 framebuffer@2 {
87 compatible = "allwinner,simple-framebuffer",
88 "simple-framebuffer";
89 allwinner,pipeline = "de_be0-lcd0-tve0";
90 clocks = <&ahb_gates 34>, <&ahb_gates 36>,
91 <&ahb_gates 44>,
92 <&de_be0_clk>, <&tcon0_ch1_clk>,
93 <&dram_gates 5>, <&dram_gates 26>;
94 status = "disabled";
95 };
96 };
97
98 cpus {
99 #address-cells = <1>;
100 #size-cells = <0>;
101
102 cpu0: cpu@0 {
103 compatible = "arm,cortex-a7";
104 device_type = "cpu";
105 reg = <0>;
106 clocks = <&cpu>;
107 clock-latency = <244144>; /* 8 32k periods */
108 operating-points = <
109 /* kHz uV */
110 960000 1400000
111 912000 1400000
112 864000 1300000
113 720000 1200000
114 528000 1100000
115 312000 1000000
116 144000 1000000
117 >;
118 #cooling-cells = <2>;
119 cooling-min-level = <0>;
120 cooling-max-level = <6>;
121 };
122
123 cpu@1 {
124 compatible = "arm,cortex-a7";
125 device_type = "cpu";
126 reg = <1>;
127 };
128 };
129
130 thermal-zones {
131 cpu_thermal {
132 /* milliseconds */
133 polling-delay-passive = <250>;
134 polling-delay = <1000>;
135 thermal-sensors = <&rtp>;
136
137 cooling-maps {
138 map0 {
139 trip = <&cpu_alert0>;
140 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
141 };
142 };
143
144 trips {
145 cpu_alert0: cpu_alert0 {
146 /* milliCelsius */
147 temperature = <75000>;
148 hysteresis = <2000>;
149 type = "passive";
150 };
151
152 cpu_crit: cpu_crit {
153 /* milliCelsius */
154 temperature = <100000>;
155 hysteresis = <2000>;
156 type = "critical";
157 };
158 };
159 };
160 };
161
162 memory {
163 reg = <0x40000000 0x80000000>;
164 };
165
166 timer {
167 compatible = "arm,armv7-timer";
168 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
169 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
170 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
171 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
172 };
173
174 pmu {
175 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
176 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
178 };
179
180 clocks {
181 #address-cells = <1>;
182 #size-cells = <1>;
183 ranges;
184
185 osc24M: clk@01c20050 {
186 #clock-cells = <0>;
187 compatible = "allwinner,sun4i-a10-osc-clk";
188 reg = <0x01c20050 0x4>;
189 clock-frequency = <24000000>;
190 clock-output-names = "osc24M";
191 };
192
193 osc3M: osc3M_clk {
194 #clock-cells = <0>;
195 compatible = "fixed-factor-clock";
196 clock-div = <8>;
197 clock-mult = <1>;
198 clocks = <&osc24M>;
199 clock-output-names = "osc3M";
200 };
201
202 osc32k: clk@0 {
203 #clock-cells = <0>;
204 compatible = "fixed-clock";
205 clock-frequency = <32768>;
206 clock-output-names = "osc32k";
207 };
208
209 pll1: clk@01c20000 {
210 #clock-cells = <0>;
211 compatible = "allwinner,sun4i-a10-pll1-clk";
212 reg = <0x01c20000 0x4>;
213 clocks = <&osc24M>;
214 clock-output-names = "pll1";
215 };
216
217 pll2: clk@01c20008 {
218 #clock-cells = <1>;
219 compatible = "allwinner,sun4i-a10-pll2-clk";
220 reg = <0x01c20008 0x8>;
221 clocks = <&osc24M>;
222 clock-output-names = "pll2-1x", "pll2-2x",
223 "pll2-4x", "pll2-8x";
224 };
225
226 pll3: clk@01c20010 {
227 #clock-cells = <0>;
228 compatible = "allwinner,sun4i-a10-pll3-clk";
229 reg = <0x01c20010 0x4>;
230 clocks = <&osc3M>;
231 clock-output-names = "pll3";
232 };
233
234 pll3x2: pll3x2_clk {
235 #clock-cells = <0>;
236 compatible = "fixed-factor-clock";
237 clocks = <&pll3>;
238 clock-div = <1>;
239 clock-mult = <2>;
240 clock-output-names = "pll3-2x";
241 };
242
243 pll4: clk@01c20018 {
244 #clock-cells = <0>;
245 compatible = "allwinner,sun7i-a20-pll4-clk";
246 reg = <0x01c20018 0x4>;
247 clocks = <&osc24M>;
248 clock-output-names = "pll4";
249 };
250
251 pll5: clk@01c20020 {
252 #clock-cells = <1>;
253 compatible = "allwinner,sun4i-a10-pll5-clk";
254 reg = <0x01c20020 0x4>;
255 clocks = <&osc24M>;
256 clock-output-names = "pll5_ddr", "pll5_other";
257 };
258
259 pll6: clk@01c20028 {
260 #clock-cells = <1>;
261 compatible = "allwinner,sun4i-a10-pll6-clk";
262 reg = <0x01c20028 0x4>;
263 clocks = <&osc24M>;
264 clock-output-names = "pll6_sata", "pll6_other", "pll6",
265 "pll6_div_4";
266 };
267
268 pll7: clk@01c20030 {
269 #clock-cells = <0>;
270 compatible = "allwinner,sun4i-a10-pll3-clk";
271 reg = <0x01c20030 0x4>;
272 clocks = <&osc3M>;
273 clock-output-names = "pll7";
274 };
275
276 pll7x2: pll7x2_clk {
277 #clock-cells = <0>;
278 compatible = "fixed-factor-clock";
279 clocks = <&pll7>;
280 clock-div = <1>;
281 clock-mult = <2>;
282 clock-output-names = "pll7-2x";
283 };
284
285 pll8: clk@01c20040 {
286 #clock-cells = <0>;
287 compatible = "allwinner,sun7i-a20-pll4-clk";
288 reg = <0x01c20040 0x4>;
289 clocks = <&osc24M>;
290 clock-output-names = "pll8";
291 };
292
293 cpu: cpu@01c20054 {
294 #clock-cells = <0>;
295 compatible = "allwinner,sun4i-a10-cpu-clk";
296 reg = <0x01c20054 0x4>;
297 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
298 clock-output-names = "cpu";
299 };
300
301 axi: axi@01c20054 {
302 #clock-cells = <0>;
303 compatible = "allwinner,sun4i-a10-axi-clk";
304 reg = <0x01c20054 0x4>;
305 clocks = <&cpu>;
306 clock-output-names = "axi";
307 };
308
309 ahb: ahb@01c20054 {
310 #clock-cells = <0>;
311 compatible = "allwinner,sun5i-a13-ahb-clk";
312 reg = <0x01c20054 0x4>;
313 clocks = <&axi>, <&pll6 3>, <&pll6 1>;
314 clock-output-names = "ahb";
315 /*
316 * Use PLL6 as parent, instead of CPU/AXI
317 * which has rate changes due to cpufreq
318 */
319 assigned-clocks = <&ahb>;
320 assigned-clock-parents = <&pll6 3>;
321 };
322
323 ahb_gates: clk@01c20060 {
324 #clock-cells = <1>;
325 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
326 reg = <0x01c20060 0x8>;
327 clocks = <&ahb>;
328 clock-indices = <0>, <1>,
329 <2>, <3>, <4>,
330 <5>, <6>, <7>, <8>,
331 <9>, <10>, <11>, <12>,
332 <13>, <14>, <16>,
333 <17>, <18>, <20>, <21>,
334 <22>, <23>, <25>,
335 <28>, <32>, <33>, <34>,
336 <35>, <36>, <37>, <40>,
337 <41>, <42>, <43>,
338 <44>, <45>, <46>,
339 <47>, <49>, <50>,
340 <52>;
341 clock-output-names = "ahb_usb0", "ahb_ehci0",
342 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
343 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
344 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
345 "ahb_nand", "ahb_sdram", "ahb_ace",
346 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
347 "ahb_spi2", "ahb_spi3", "ahb_sata",
348 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
349 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
350 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
351 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
352 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
353 "ahb_mali";
354 };
355
356 apb0: apb0@01c20054 {
357 #clock-cells = <0>;
358 compatible = "allwinner,sun4i-a10-apb0-clk";
359 reg = <0x01c20054 0x4>;
360 clocks = <&ahb>;
361 clock-output-names = "apb0";
362 };
363
364 apb0_gates: clk@01c20068 {
365 #clock-cells = <1>;
366 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
367 reg = <0x01c20068 0x4>;
368 clocks = <&apb0>;
369 clock-indices = <0>, <1>,
370 <2>, <3>, <4>,
371 <5>, <6>, <7>,
372 <8>, <10>;
373 clock-output-names = "apb0_codec", "apb0_spdif",
374 "apb0_ac97", "apb0_iis0", "apb0_iis1",
375 "apb0_pio", "apb0_ir0", "apb0_ir1",
376 "apb0_iis2", "apb0_keypad";
377 };
378
379 apb1: clk@01c20058 {
380 #clock-cells = <0>;
381 compatible = "allwinner,sun4i-a10-apb1-clk";
382 reg = <0x01c20058 0x4>;
383 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
384 clock-output-names = "apb1";
385 };
386
387 apb1_gates: clk@01c2006c {
388 #clock-cells = <1>;
389 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
390 reg = <0x01c2006c 0x4>;
391 clocks = <&apb1>;
392 clock-indices = <0>, <1>,
393 <2>, <3>, <4>,
394 <5>, <6>, <7>,
395 <15>, <16>, <17>,
396 <18>, <19>, <20>,
397 <21>, <22>, <23>;
398 clock-output-names = "apb1_i2c0", "apb1_i2c1",
399 "apb1_i2c2", "apb1_i2c3", "apb1_can",
400 "apb1_scr", "apb1_ps20", "apb1_ps21",
401 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
402 "apb1_uart2", "apb1_uart3", "apb1_uart4",
403 "apb1_uart5", "apb1_uart6", "apb1_uart7";
404 };
405
406 nand_clk: clk@01c20080 {
407 #clock-cells = <0>;
408 compatible = "allwinner,sun4i-a10-mod0-clk";
409 reg = <0x01c20080 0x4>;
410 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
411 clock-output-names = "nand";
412 };
413
414 ms_clk: clk@01c20084 {
415 #clock-cells = <0>;
416 compatible = "allwinner,sun4i-a10-mod0-clk";
417 reg = <0x01c20084 0x4>;
418 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
419 clock-output-names = "ms";
420 };
421
422 mmc0_clk: clk@01c20088 {
423 #clock-cells = <1>;
424 compatible = "allwinner,sun4i-a10-mmc-clk";
425 reg = <0x01c20088 0x4>;
426 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
427 clock-output-names = "mmc0",
428 "mmc0_output",
429 "mmc0_sample";
430 };
431
432 mmc1_clk: clk@01c2008c {
433 #clock-cells = <1>;
434 compatible = "allwinner,sun4i-a10-mmc-clk";
435 reg = <0x01c2008c 0x4>;
436 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
437 clock-output-names = "mmc1",
438 "mmc1_output",
439 "mmc1_sample";
440 };
441
442 mmc2_clk: clk@01c20090 {
443 #clock-cells = <1>;
444 compatible = "allwinner,sun4i-a10-mmc-clk";
445 reg = <0x01c20090 0x4>;
446 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
447 clock-output-names = "mmc2",
448 "mmc2_output",
449 "mmc2_sample";
450 };
451
452 mmc3_clk: clk@01c20094 {
453 #clock-cells = <1>;
454 compatible = "allwinner,sun4i-a10-mmc-clk";
455 reg = <0x01c20094 0x4>;
456 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
457 clock-output-names = "mmc3",
458 "mmc3_output",
459 "mmc3_sample";
460 };
461
462 ts_clk: clk@01c20098 {
463 #clock-cells = <0>;
464 compatible = "allwinner,sun4i-a10-mod0-clk";
465 reg = <0x01c20098 0x4>;
466 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
467 clock-output-names = "ts";
468 };
469
470 ss_clk: clk@01c2009c {
471 #clock-cells = <0>;
472 compatible = "allwinner,sun4i-a10-mod0-clk";
473 reg = <0x01c2009c 0x4>;
474 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
475 clock-output-names = "ss";
476 };
477
478 spi0_clk: clk@01c200a0 {
479 #clock-cells = <0>;
480 compatible = "allwinner,sun4i-a10-mod0-clk";
481 reg = <0x01c200a0 0x4>;
482 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
483 clock-output-names = "spi0";
484 };
485
486 spi1_clk: clk@01c200a4 {
487 #clock-cells = <0>;
488 compatible = "allwinner,sun4i-a10-mod0-clk";
489 reg = <0x01c200a4 0x4>;
490 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
491 clock-output-names = "spi1";
492 };
493
494 spi2_clk: clk@01c200a8 {
495 #clock-cells = <0>;
496 compatible = "allwinner,sun4i-a10-mod0-clk";
497 reg = <0x01c200a8 0x4>;
498 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
499 clock-output-names = "spi2";
500 };
501
502 pata_clk: clk@01c200ac {
503 #clock-cells = <0>;
504 compatible = "allwinner,sun4i-a10-mod0-clk";
505 reg = <0x01c200ac 0x4>;
506 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
507 clock-output-names = "pata";
508 };
509
510 ir0_clk: clk@01c200b0 {
511 #clock-cells = <0>;
512 compatible = "allwinner,sun4i-a10-mod0-clk";
513 reg = <0x01c200b0 0x4>;
514 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
515 clock-output-names = "ir0";
516 };
517
518 ir1_clk: clk@01c200b4 {
519 #clock-cells = <0>;
520 compatible = "allwinner,sun4i-a10-mod0-clk";
521 reg = <0x01c200b4 0x4>;
522 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
523 clock-output-names = "ir1";
524 };
525
526 spdif_clk: clk@01c200c0 {
527 #clock-cells = <0>;
528 compatible = "allwinner,sun4i-a10-mod1-clk";
529 reg = <0x01c200c0 0x4>;
530 clocks = <&pll2 SUN4I_A10_PLL2_8X>,
531 <&pll2 SUN4I_A10_PLL2_4X>,
532 <&pll2 SUN4I_A10_PLL2_2X>,
533 <&pll2 SUN4I_A10_PLL2_1X>;
534 clock-output-names = "spdif";
535 };
536
537 keypad_clk: clk@01c200c4 {
538 #clock-cells = <0>;
539 compatible = "allwinner,sun4i-a10-mod0-clk";
540 reg = <0x01c200c4 0x4>;
541 clocks = <&osc24M>;
542 clock-output-names = "keypad";
543 };
544
545 usb_clk: clk@01c200cc {
546 #clock-cells = <1>;
547 #reset-cells = <1>;
548 compatible = "allwinner,sun4i-a10-usb-clk";
549 reg = <0x01c200cc 0x4>;
550 clocks = <&pll6 1>;
551 clock-output-names = "usb_ohci0", "usb_ohci1",
552 "usb_phy";
553 };
554
555 spi3_clk: clk@01c200d4 {
556 #clock-cells = <0>;
557 compatible = "allwinner,sun4i-a10-mod0-clk";
558 reg = <0x01c200d4 0x4>;
559 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
560 clock-output-names = "spi3";
561 };
562
563 dram_gates: clk@01c20100 {
564 #clock-cells = <1>;
565 compatible = "allwinner,sun4i-a10-dram-gates-clk";
566 reg = <0x01c20100 0x4>;
567 clocks = <&pll5 0>;
568 clock-indices = <0>,
569 <1>, <2>,
570 <3>,
571 <4>,
572 <5>, <6>,
573 <15>,
574 <24>, <25>,
575 <26>, <27>,
576 <28>, <29>;
577 clock-output-names = "dram_ve",
578 "dram_csi0", "dram_csi1",
579 "dram_ts",
580 "dram_tvd",
581 "dram_tve0", "dram_tve1",
582 "dram_output",
583 "dram_de_fe1", "dram_de_fe0",
584 "dram_de_be0", "dram_de_be1",
585 "dram_de_mp", "dram_ace";
586 };
587
588 de_be0_clk: clk@01c20104 {
589 #clock-cells = <0>;
590 #reset-cells = <0>;
591 compatible = "allwinner,sun4i-a10-display-clk";
592 reg = <0x01c20104 0x4>;
593 clocks = <&pll3>, <&pll7>, <&pll5 1>;
594 clock-output-names = "de-be0";
595 };
596
597 de_be1_clk: clk@01c20108 {
598 #clock-cells = <0>;
599 #reset-cells = <0>;
600 compatible = "allwinner,sun4i-a10-display-clk";
601 reg = <0x01c20108 0x4>;
602 clocks = <&pll3>, <&pll7>, <&pll5 1>;
603 clock-output-names = "de-be1";
604 };
605
606 de_fe0_clk: clk@01c2010c {
607 #clock-cells = <0>;
608 #reset-cells = <0>;
609 compatible = "allwinner,sun4i-a10-display-clk";
610 reg = <0x01c2010c 0x4>;
611 clocks = <&pll3>, <&pll7>, <&pll5 1>;
612 clock-output-names = "de-fe0";
613 };
614
615 de_fe1_clk: clk@01c20110 {
616 #clock-cells = <0>;
617 #reset-cells = <0>;
618 compatible = "allwinner,sun4i-a10-display-clk";
619 reg = <0x01c20110 0x4>;
620 clocks = <&pll3>, <&pll7>, <&pll5 1>;
621 clock-output-names = "de-fe1";
622 };
623
624 tcon0_ch0_clk: clk@01c20118 {
625 #clock-cells = <0>;
626 #reset-cells = <1>;
627 compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
628 reg = <0x01c20118 0x4>;
629 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
630 clock-output-names = "tcon0-ch0-sclk";
631
632 };
633
634 tcon1_ch0_clk: clk@01c2011c {
635 #clock-cells = <0>;
636 #reset-cells = <1>;
637 compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
638 reg = <0x01c2011c 0x4>;
639 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
640 clock-output-names = "tcon1-ch0-sclk";
641
642 };
643
644 tcon0_ch1_clk: clk@01c2012c {
645 #clock-cells = <0>;
646 compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
647 reg = <0x01c2012c 0x4>;
648 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
649 clock-output-names = "tcon0-ch1-sclk";
650
651 };
652
653 tcon1_ch1_clk: clk@01c20130 {
654 #clock-cells = <0>;
655 compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
656 reg = <0x01c20130 0x4>;
657 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
658 clock-output-names = "tcon1-ch1-sclk";
659
660 };
661
662 ve_clk: clk@01c2013c {
663 #clock-cells = <0>;
664 #reset-cells = <0>;
665 compatible = "allwinner,sun4i-a10-ve-clk";
666 reg = <0x01c2013c 0x4>;
667 clocks = <&pll4>;
668 clock-output-names = "ve";
669 };
670
671 codec_clk: clk@01c20140 {
672 #clock-cells = <0>;
673 compatible = "allwinner,sun4i-a10-codec-clk";
674 reg = <0x01c20140 0x4>;
675 clocks = <&pll2 SUN4I_A10_PLL2_1X>;
676 clock-output-names = "codec";
677 };
678
679 mbus_clk: clk@01c2015c {
680 #clock-cells = <0>;
681 compatible = "allwinner,sun5i-a13-mbus-clk";
682 reg = <0x01c2015c 0x4>;
683 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
684 clock-output-names = "mbus";
685 };
686
687 /*
688 * The following two are dummy clocks, placeholders
689 * used in the gmac_tx clock. The gmac driver will
690 * choose one parent depending on the PHY interface
691 * mode, using clk_set_rate auto-reparenting.
692 *
693 * The actual TX clock rate is not controlled by the
694 * gmac_tx clock.
695 */
696 mii_phy_tx_clk: clk@2 {
697 #clock-cells = <0>;
698 compatible = "fixed-clock";
699 clock-frequency = <25000000>;
700 clock-output-names = "mii_phy_tx";
701 };
702
703 gmac_int_tx_clk: clk@3 {
704 #clock-cells = <0>;
705 compatible = "fixed-clock";
706 clock-frequency = <125000000>;
707 clock-output-names = "gmac_int_tx";
708 };
709
710 gmac_tx_clk: clk@01c20164 {
711 #clock-cells = <0>;
712 compatible = "allwinner,sun7i-a20-gmac-clk";
713 reg = <0x01c20164 0x4>;
714 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
715 clock-output-names = "gmac_tx";
716 };
717
718 /*
719 * Dummy clock used by output clocks
720 */
721 osc24M_32k: clk@1 {
722 #clock-cells = <0>;
723 compatible = "fixed-factor-clock";
724 clock-div = <750>;
725 clock-mult = <1>;
726 clocks = <&osc24M>;
727 clock-output-names = "osc24M_32k";
728 };
729
730 clk_out_a: clk@01c201f0 {
731 #clock-cells = <0>;
732 compatible = "allwinner,sun7i-a20-out-clk";
733 reg = <0x01c201f0 0x4>;
734 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
735 clock-output-names = "clk_out_a";
736 };
737
738 clk_out_b: clk@01c201f4 {
739 #clock-cells = <0>;
740 compatible = "allwinner,sun7i-a20-out-clk";
741 reg = <0x01c201f4 0x4>;
742 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
743 clock-output-names = "clk_out_b";
744 };
745 };
746
747 soc@01c00000 {
748 compatible = "simple-bus";
749 #address-cells = <1>;
750 #size-cells = <1>;
751 ranges;
752
753 sram-controller@01c00000 {
754 compatible = "allwinner,sun4i-a10-sram-controller";
755 reg = <0x01c00000 0x30>;
756 #address-cells = <1>;
757 #size-cells = <1>;
758 ranges;
759
760 sram_a: sram@00000000 {
761 compatible = "mmio-sram";
762 reg = <0x00000000 0xc000>;
763 #address-cells = <1>;
764 #size-cells = <1>;
765 ranges = <0 0x00000000 0xc000>;
766
767 emac_sram: sram-section@8000 {
768 compatible = "allwinner,sun4i-a10-sram-a3-a4";
769 reg = <0x8000 0x4000>;
770 status = "disabled";
771 };
772 };
773
774 sram_d: sram@00010000 {
775 compatible = "mmio-sram";
776 reg = <0x00010000 0x1000>;
777 #address-cells = <1>;
778 #size-cells = <1>;
779 ranges = <0 0x00010000 0x1000>;
780
781 otg_sram: sram-section@0000 {
782 compatible = "allwinner,sun4i-a10-sram-d";
783 reg = <0x0000 0x1000>;
784 status = "disabled";
785 };
786 };
787 };
788
789 nmi_intc: interrupt-controller@01c00030 {
790 compatible = "allwinner,sun7i-a20-sc-nmi";
791 interrupt-controller;
792 #interrupt-cells = <2>;
793 reg = <0x01c00030 0x0c>;
794 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
795 };
796
797 dma: dma-controller@01c02000 {
798 compatible = "allwinner,sun4i-a10-dma";
799 reg = <0x01c02000 0x1000>;
800 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
801 clocks = <&ahb_gates 6>;
802 #dma-cells = <2>;
803 };
804
805 nfc: nand@01c03000 {
806 compatible = "allwinner,sun4i-a10-nand";
807 reg = <0x01c03000 0x1000>;
808 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
809 clocks = <&ahb_gates 13>, <&nand_clk>;
810 clock-names = "ahb", "mod";
811 dmas = <&dma SUN4I_DMA_DEDICATED 3>;
812 dma-names = "rxtx";
813 status = "disabled";
814 #address-cells = <1>;
815 #size-cells = <0>;
816 };
817
818 spi0: spi@01c05000 {
819 compatible = "allwinner,sun4i-a10-spi";
820 reg = <0x01c05000 0x1000>;
821 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
822 clocks = <&ahb_gates 20>, <&spi0_clk>;
823 clock-names = "ahb", "mod";
824 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
825 <&dma SUN4I_DMA_DEDICATED 26>;
826 dma-names = "rx", "tx";
827 status = "disabled";
828 #address-cells = <1>;
829 #size-cells = <0>;
830 };
831
832 spi1: spi@01c06000 {
833 compatible = "allwinner,sun4i-a10-spi";
834 reg = <0x01c06000 0x1000>;
835 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
836 clocks = <&ahb_gates 21>, <&spi1_clk>;
837 clock-names = "ahb", "mod";
838 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
839 <&dma SUN4I_DMA_DEDICATED 8>;
840 dma-names = "rx", "tx";
841 status = "disabled";
842 #address-cells = <1>;
843 #size-cells = <0>;
844 };
845
846 emac: ethernet@01c0b000 {
847 compatible = "allwinner,sun4i-a10-emac";
848 reg = <0x01c0b000 0x1000>;
849 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&ahb_gates 17>;
851 allwinner,sram = <&emac_sram 1>;
852 status = "disabled";
853 };
854
855 mdio: mdio@01c0b080 {
856 compatible = "allwinner,sun4i-a10-mdio";
857 reg = <0x01c0b080 0x14>;
858 status = "disabled";
859 #address-cells = <1>;
860 #size-cells = <0>;
861 };
862
863 mmc0: mmc@01c0f000 {
864 compatible = "allwinner,sun5i-a13-mmc";
865 reg = <0x01c0f000 0x1000>;
866 clocks = <&ahb_gates 8>,
867 <&mmc0_clk 0>,
868 <&mmc0_clk 1>,
869 <&mmc0_clk 2>;
870 clock-names = "ahb",
871 "mmc",
872 "output",
873 "sample";
874 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
875 status = "disabled";
876 #address-cells = <1>;
877 #size-cells = <0>;
878 };
879
880 mmc1: mmc@01c10000 {
881 compatible = "allwinner,sun5i-a13-mmc";
882 reg = <0x01c10000 0x1000>;
883 clocks = <&ahb_gates 9>,
884 <&mmc1_clk 0>,
885 <&mmc1_clk 1>,
886 <&mmc1_clk 2>;
887 clock-names = "ahb",
888 "mmc",
889 "output",
890 "sample";
891 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
892 status = "disabled";
893 #address-cells = <1>;
894 #size-cells = <0>;
895 };
896
897 mmc2: mmc@01c11000 {
898 compatible = "allwinner,sun5i-a13-mmc";
899 reg = <0x01c11000 0x1000>;
900 clocks = <&ahb_gates 10>,
901 <&mmc2_clk 0>,
902 <&mmc2_clk 1>,
903 <&mmc2_clk 2>;
904 clock-names = "ahb",
905 "mmc",
906 "output",
907 "sample";
908 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
909 status = "disabled";
910 #address-cells = <1>;
911 #size-cells = <0>;
912 };
913
914 mmc3: mmc@01c12000 {
915 compatible = "allwinner,sun5i-a13-mmc";
916 reg = <0x01c12000 0x1000>;
917 clocks = <&ahb_gates 11>,
918 <&mmc3_clk 0>,
919 <&mmc3_clk 1>,
920 <&mmc3_clk 2>;
921 clock-names = "ahb",
922 "mmc",
923 "output",
924 "sample";
925 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
926 status = "disabled";
927 #address-cells = <1>;
928 #size-cells = <0>;
929 };
930
931 usb_otg: usb@01c13000 {
932 compatible = "allwinner,sun4i-a10-musb";
933 reg = <0x01c13000 0x0400>;
934 clocks = <&ahb_gates 0>;
935 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
936 interrupt-names = "mc";
937 phys = <&usbphy 0>;
938 phy-names = "usb";
939 extcon = <&usbphy 0>;
940 allwinner,sram = <&otg_sram 1>;
941 status = "disabled";
942 };
943
944 usbphy: phy@01c13400 {
945 #phy-cells = <1>;
946 compatible = "allwinner,sun7i-a20-usb-phy";
947 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
948 reg-names = "phy_ctrl", "pmu1", "pmu2";
949 clocks = <&usb_clk 8>;
950 clock-names = "usb_phy";
951 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
952 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
953 status = "disabled";
954 };
955
956 ehci0: usb@01c14000 {
957 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
958 reg = <0x01c14000 0x100>;
959 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
960 clocks = <&ahb_gates 1>;
961 phys = <&usbphy 1>;
962 phy-names = "usb";
963 status = "disabled";
964 };
965
966 ohci0: usb@01c14400 {
967 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
968 reg = <0x01c14400 0x100>;
969 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
970 clocks = <&usb_clk 6>, <&ahb_gates 2>;
971 phys = <&usbphy 1>;
972 phy-names = "usb";
973 status = "disabled";
974 };
975
976 crypto: crypto-engine@01c15000 {
977 compatible = "allwinner,sun4i-a10-crypto";
978 reg = <0x01c15000 0x1000>;
979 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
980 clocks = <&ahb_gates 5>, <&ss_clk>;
981 clock-names = "ahb", "mod";
982 };
983
984 spi2: spi@01c17000 {
985 compatible = "allwinner,sun4i-a10-spi";
986 reg = <0x01c17000 0x1000>;
987 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
988 clocks = <&ahb_gates 22>, <&spi2_clk>;
989 clock-names = "ahb", "mod";
990 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
991 <&dma SUN4I_DMA_DEDICATED 28>;
992 dma-names = "rx", "tx";
993 status = "disabled";
994 #address-cells = <1>;
995 #size-cells = <0>;
996 };
997
998 ahci: sata@01c18000 {
999 compatible = "allwinner,sun4i-a10-ahci";
1000 reg = <0x01c18000 0x1000>;
1001 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1002 clocks = <&pll6 0>, <&ahb_gates 25>;
1003 status = "disabled";
1004 };
1005
1006 ehci1: usb@01c1c000 {
1007 compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
1008 reg = <0x01c1c000 0x100>;
1009 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1010 clocks = <&ahb_gates 3>;
1011 phys = <&usbphy 2>;
1012 phy-names = "usb";
1013 status = "disabled";
1014 };
1015
1016 ohci1: usb@01c1c400 {
1017 compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
1018 reg = <0x01c1c400 0x100>;
1019 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1020 clocks = <&usb_clk 7>, <&ahb_gates 4>;
1021 phys = <&usbphy 2>;
1022 phy-names = "usb";
1023 status = "disabled";
1024 };
1025
1026 spi3: spi@01c1f000 {
1027 compatible = "allwinner,sun4i-a10-spi";
1028 reg = <0x01c1f000 0x1000>;
1029 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1030 clocks = <&ahb_gates 23>, <&spi3_clk>;
1031 clock-names = "ahb", "mod";
1032 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
1033 <&dma SUN4I_DMA_DEDICATED 30>;
1034 dma-names = "rx", "tx";
1035 status = "disabled";
1036 #address-cells = <1>;
1037 #size-cells = <0>;
1038 };
1039
1040 pio: pinctrl@01c20800 {
1041 compatible = "allwinner,sun7i-a20-pinctrl";
1042 reg = <0x01c20800 0x400>;
1043 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1044 clocks = <&apb0_gates 5>;
1045 gpio-controller;
1046 interrupt-controller;
1047 #interrupt-cells = <3>;
1048 #gpio-cells = <3>;
1049
1050 clk_out_a_pins_a: clk_out_a@0 {
1051 allwinner,pins = "PI12";
1052 allwinner,function = "clk_out_a";
1053 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1054 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1055 };
1056
1057 clk_out_b_pins_a: clk_out_b@0 {
1058 allwinner,pins = "PI13";
1059 allwinner,function = "clk_out_b";
1060 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1061 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1062 };
1063
1064 emac_pins_a: emac0@0 {
1065 allwinner,pins = "PA0", "PA1", "PA2",
1066 "PA3", "PA4", "PA5", "PA6",
1067 "PA7", "PA8", "PA9", "PA10",
1068 "PA11", "PA12", "PA13", "PA14",
1069 "PA15", "PA16";
1070 allwinner,function = "emac";
1071 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1072 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1073 };
1074
1075 gmac_pins_mii_a: gmac_mii@0 {
1076 allwinner,pins = "PA0", "PA1", "PA2",
1077 "PA3", "PA4", "PA5", "PA6",
1078 "PA7", "PA8", "PA9", "PA10",
1079 "PA11", "PA12", "PA13", "PA14",
1080 "PA15", "PA16";
1081 allwinner,function = "gmac";
1082 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1083 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1084 };
1085
1086 gmac_pins_rgmii_a: gmac_rgmii@0 {
1087 allwinner,pins = "PA0", "PA1", "PA2",
1088 "PA3", "PA4", "PA5", "PA6",
1089 "PA7", "PA8", "PA10",
1090 "PA11", "PA12", "PA13",
1091 "PA15", "PA16";
1092 allwinner,function = "gmac";
1093 /*
1094 * data lines in RGMII mode use DDR mode
1095 * and need a higher signal drive strength
1096 */
1097 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
1098 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1099 };
1100
1101 i2c0_pins_a: i2c0@0 {
1102 allwinner,pins = "PB0", "PB1";
1103 allwinner,function = "i2c0";
1104 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1105 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1106 };
1107
1108 i2c1_pins_a: i2c1@0 {
1109 allwinner,pins = "PB18", "PB19";
1110 allwinner,function = "i2c1";
1111 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1112 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1113 };
1114
1115 i2c2_pins_a: i2c2@0 {
1116 allwinner,pins = "PB20", "PB21";
1117 allwinner,function = "i2c2";
1118 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1119 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1120 };
1121
1122 i2c3_pins_a: i2c3@0 {
1123 allwinner,pins = "PI0", "PI1";
1124 allwinner,function = "i2c3";
1125 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1126 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1127 };
1128
1129 ir0_rx_pins_a: ir0@0 {
1130 allwinner,pins = "PB4";
1131 allwinner,function = "ir0";
1132 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1133 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1134 };
1135
1136 ir0_tx_pins_a: ir0@1 {
1137 allwinner,pins = "PB3";
1138 allwinner,function = "ir0";
1139 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1140 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1141 };
1142
1143 ir1_rx_pins_a: ir1@0 {
1144 allwinner,pins = "PB23";
1145 allwinner,function = "ir1";
1146 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1147 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1148 };
1149
1150 ir1_tx_pins_a: ir1@1 {
1151 allwinner,pins = "PB22";
1152 allwinner,function = "ir1";
1153 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1154 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1155 };
1156
1157 mmc0_pins_a: mmc0@0 {
1158 allwinner,pins = "PF0", "PF1", "PF2",
1159 "PF3", "PF4", "PF5";
1160 allwinner,function = "mmc0";
1161 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1162 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1163 };
1164
1165 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
1166 allwinner,pins = "PH1";
1167 allwinner,function = "gpio_in";
1168 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1169 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1170 };
1171
1172 mmc2_pins_a: mmc2@0 {
1173 allwinner,pins = "PC6", "PC7", "PC8",
1174 "PC9", "PC10", "PC11";
1175 allwinner,function = "mmc2";
1176 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1177 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1178 };
1179
1180 mmc3_pins_a: mmc3@0 {
1181 allwinner,pins = "PI4", "PI5", "PI6",
1182 "PI7", "PI8", "PI9";
1183 allwinner,function = "mmc3";
1184 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1185 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1186 };
1187
1188 ps20_pins_a: ps20@0 {
1189 allwinner,pins = "PI20", "PI21";
1190 allwinner,function = "ps2";
1191 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1192 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1193 };
1194
1195 ps21_pins_a: ps21@0 {
1196 allwinner,pins = "PH12", "PH13";
1197 allwinner,function = "ps2";
1198 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1199 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1200 };
1201
1202 pwm0_pins_a: pwm0@0 {
1203 allwinner,pins = "PB2";
1204 allwinner,function = "pwm";
1205 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1206 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1207 };
1208
1209 pwm1_pins_a: pwm1@0 {
1210 allwinner,pins = "PI3";
1211 allwinner,function = "pwm";
1212 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1213 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1214 };
1215
1216 spdif_tx_pins_a: spdif@0 {
1217 allwinner,pins = "PB13";
1218 allwinner,function = "spdif";
1219 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1220 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1221 };
1222
1223 spi0_pins_a: spi0@0 {
1224 allwinner,pins = "PI11", "PI12", "PI13";
1225 allwinner,function = "spi0";
1226 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1227 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1228 };
1229
1230 spi0_cs0_pins_a: spi0_cs0@0 {
1231 allwinner,pins = "PI10";
1232 allwinner,function = "spi0";
1233 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1234 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1235 };
1236
1237 spi0_cs1_pins_a: spi0_cs1@0 {
1238 allwinner,pins = "PI14";
1239 allwinner,function = "spi0";
1240 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1241 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1242 };
1243
1244 spi1_pins_a: spi1@0 {
1245 allwinner,pins = "PI17", "PI18", "PI19";
1246 allwinner,function = "spi1";
1247 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1248 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1249 };
1250
1251 spi1_cs0_pins_a: spi1_cs0@0 {
1252 allwinner,pins = "PI16";
1253 allwinner,function = "spi1";
1254 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1255 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1256 };
1257
1258 spi2_pins_a: spi2@0 {
1259 allwinner,pins = "PC20", "PC21", "PC22";
1260 allwinner,function = "spi2";
1261 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1262 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1263 };
1264
1265 spi2_pins_b: spi2@1 {
1266 allwinner,pins = "PB15", "PB16", "PB17";
1267 allwinner,function = "spi2";
1268 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1269 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1270 };
1271
1272 spi2_cs0_pins_a: spi2_cs0@0 {
1273 allwinner,pins = "PC19";
1274 allwinner,function = "spi2";
1275 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1276 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1277 };
1278
1279 spi2_cs0_pins_b: spi2_cs0@1 {
1280 allwinner,pins = "PB14";
1281 allwinner,function = "spi2";
1282 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1283 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1284 };
1285
1286 uart0_pins_a: uart0@0 {
1287 allwinner,pins = "PB22", "PB23";
1288 allwinner,function = "uart0";
1289 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1290 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1291 };
1292
1293 uart2_pins_a: uart2@0 {
1294 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
1295 allwinner,function = "uart2";
1296 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1297 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1298 };
1299
1300 uart3_pins_a: uart3@0 {
1301 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
1302 allwinner,function = "uart3";
1303 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1304 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1305 };
1306
1307 uart3_pins_b: uart3@1 {
1308 allwinner,pins = "PH0", "PH1";
1309 allwinner,function = "uart3";
1310 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1311 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1312 };
1313
1314 uart4_pins_a: uart4@0 {
1315 allwinner,pins = "PG10", "PG11";
1316 allwinner,function = "uart4";
1317 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1318 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1319 };
1320
1321 uart4_pins_b: uart4@1 {
1322 allwinner,pins = "PH4", "PH5";
1323 allwinner,function = "uart4";
1324 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1325 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1326 };
1327
1328 uart5_pins_a: uart5@0 {
1329 allwinner,pins = "PI10", "PI11";
1330 allwinner,function = "uart5";
1331 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1332 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1333 };
1334
1335 uart6_pins_a: uart6@0 {
1336 allwinner,pins = "PI12", "PI13";
1337 allwinner,function = "uart6";
1338 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1339 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1340 };
1341
1342 uart7_pins_a: uart7@0 {
1343 allwinner,pins = "PI20", "PI21";
1344 allwinner,function = "uart7";
1345 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1346 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1347 };
1348 };
1349
1350 timer@01c20c00 {
1351 compatible = "allwinner,sun4i-a10-timer";
1352 reg = <0x01c20c00 0x90>;
1353 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
1354 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
1355 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1356 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1357 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1358 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1359 clocks = <&osc24M>;
1360 };
1361
1362 wdt: watchdog@01c20c90 {
1363 compatible = "allwinner,sun4i-a10-wdt";
1364 reg = <0x01c20c90 0x10>;
1365 };
1366
1367 rtc: rtc@01c20d00 {
1368 compatible = "allwinner,sun7i-a20-rtc";
1369 reg = <0x01c20d00 0x20>;
1370 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1371 };
1372
1373 pwm: pwm@01c20e00 {
1374 compatible = "allwinner,sun7i-a20-pwm";
1375 reg = <0x01c20e00 0xc>;
1376 clocks = <&osc24M>;
1377 #pwm-cells = <3>;
1378 status = "disabled";
1379 };
1380
1381 spdif: spdif@01c21000 {
1382 #sound-dai-cells = <0>;
1383 compatible = "allwinner,sun4i-a10-spdif";
1384 reg = <0x01c21000 0x400>;
1385 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1386 clocks = <&apb0_gates 1>, <&spdif_clk>;
1387 clock-names = "apb", "spdif";
1388 dmas = <&dma SUN4I_DMA_NORMAL 2>,
1389 <&dma SUN4I_DMA_NORMAL 2>;
1390 dma-names = "rx", "tx";
1391 status = "disabled";
1392 };
1393
1394 ir0: ir@01c21800 {
1395 compatible = "allwinner,sun4i-a10-ir";
1396 clocks = <&apb0_gates 6>, <&ir0_clk>;
1397 clock-names = "apb", "ir";
1398 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1399 reg = <0x01c21800 0x40>;
1400 status = "disabled";
1401 };
1402
1403 ir1: ir@01c21c00 {
1404 compatible = "allwinner,sun4i-a10-ir";
1405 clocks = <&apb0_gates 7>, <&ir1_clk>;
1406 clock-names = "apb", "ir";
1407 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1408 reg = <0x01c21c00 0x40>;
1409 status = "disabled";
1410 };
1411
1412 lradc: lradc@01c22800 {
1413 compatible = "allwinner,sun4i-a10-lradc-keys";
1414 reg = <0x01c22800 0x100>;
1415 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1416 status = "disabled";
1417 };
1418
1419 codec: codec@01c22c00 {
1420 #sound-dai-cells = <0>;
1421 compatible = "allwinner,sun7i-a20-codec";
1422 reg = <0x01c22c00 0x40>;
1423 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1424 clocks = <&apb0_gates 0>, <&codec_clk>;
1425 clock-names = "apb", "codec";
1426 dmas = <&dma SUN4I_DMA_NORMAL 19>,
1427 <&dma SUN4I_DMA_NORMAL 19>;
1428 dma-names = "rx", "tx";
1429 status = "disabled";
1430 };
1431
1432 sid: eeprom@01c23800 {
1433 compatible = "allwinner,sun7i-a20-sid";
1434 reg = <0x01c23800 0x200>;
1435 };
1436
1437 rtp: rtp@01c25000 {
1438 compatible = "allwinner,sun5i-a13-ts";
1439 reg = <0x01c25000 0x100>;
1440 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1441 #thermal-sensor-cells = <0>;
1442 };
1443
1444 uart0: serial@01c28000 {
1445 compatible = "snps,dw-apb-uart";
1446 reg = <0x01c28000 0x400>;
1447 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1448 reg-shift = <2>;
1449 reg-io-width = <4>;
1450 clocks = <&apb1_gates 16>;
1451 status = "disabled";
1452 };
1453
1454 uart1: serial@01c28400 {
1455 compatible = "snps,dw-apb-uart";
1456 reg = <0x01c28400 0x400>;
1457 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1458 reg-shift = <2>;
1459 reg-io-width = <4>;
1460 clocks = <&apb1_gates 17>;
1461 status = "disabled";
1462 };
1463
1464 uart2: serial@01c28800 {
1465 compatible = "snps,dw-apb-uart";
1466 reg = <0x01c28800 0x400>;
1467 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1468 reg-shift = <2>;
1469 reg-io-width = <4>;
1470 clocks = <&apb1_gates 18>;
1471 status = "disabled";
1472 };
1473
1474 uart3: serial@01c28c00 {
1475 compatible = "snps,dw-apb-uart";
1476 reg = <0x01c28c00 0x400>;
1477 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1478 reg-shift = <2>;
1479 reg-io-width = <4>;
1480 clocks = <&apb1_gates 19>;
1481 status = "disabled";
1482 };
1483
1484 uart4: serial@01c29000 {
1485 compatible = "snps,dw-apb-uart";
1486 reg = <0x01c29000 0x400>;
1487 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1488 reg-shift = <2>;
1489 reg-io-width = <4>;
1490 clocks = <&apb1_gates 20>;
1491 status = "disabled";
1492 };
1493
1494 uart5: serial@01c29400 {
1495 compatible = "snps,dw-apb-uart";
1496 reg = <0x01c29400 0x400>;
1497 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1498 reg-shift = <2>;
1499 reg-io-width = <4>;
1500 clocks = <&apb1_gates 21>;
1501 status = "disabled";
1502 };
1503
1504 uart6: serial@01c29800 {
1505 compatible = "snps,dw-apb-uart";
1506 reg = <0x01c29800 0x400>;
1507 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1508 reg-shift = <2>;
1509 reg-io-width = <4>;
1510 clocks = <&apb1_gates 22>;
1511 status = "disabled";
1512 };
1513
1514 uart7: serial@01c29c00 {
1515 compatible = "snps,dw-apb-uart";
1516 reg = <0x01c29c00 0x400>;
1517 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1518 reg-shift = <2>;
1519 reg-io-width = <4>;
1520 clocks = <&apb1_gates 23>;
1521 status = "disabled";
1522 };
1523
1524 i2c0: i2c@01c2ac00 {
1525 compatible = "allwinner,sun7i-a20-i2c",
1526 "allwinner,sun4i-a10-i2c";
1527 reg = <0x01c2ac00 0x400>;
1528 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1529 clocks = <&apb1_gates 0>;
1530 status = "disabled";
1531 #address-cells = <1>;
1532 #size-cells = <0>;
1533 };
1534
1535 i2c1: i2c@01c2b000 {
1536 compatible = "allwinner,sun7i-a20-i2c",
1537 "allwinner,sun4i-a10-i2c";
1538 reg = <0x01c2b000 0x400>;
1539 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1540 clocks = <&apb1_gates 1>;
1541 status = "disabled";
1542 #address-cells = <1>;
1543 #size-cells = <0>;
1544 };
1545
1546 i2c2: i2c@01c2b400 {
1547 compatible = "allwinner,sun7i-a20-i2c",
1548 "allwinner,sun4i-a10-i2c";
1549 reg = <0x01c2b400 0x400>;
1550 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1551 clocks = <&apb1_gates 2>;
1552 status = "disabled";
1553 #address-cells = <1>;
1554 #size-cells = <0>;
1555 };
1556
1557 i2c3: i2c@01c2b800 {
1558 compatible = "allwinner,sun7i-a20-i2c",
1559 "allwinner,sun4i-a10-i2c";
1560 reg = <0x01c2b800 0x400>;
1561 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1562 clocks = <&apb1_gates 3>;
1563 status = "disabled";
1564 #address-cells = <1>;
1565 #size-cells = <0>;
1566 };
1567
1568 i2c4: i2c@01c2c000 {
1569 compatible = "allwinner,sun7i-a20-i2c",
1570 "allwinner,sun4i-a10-i2c";
1571 reg = <0x01c2c000 0x400>;
1572 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1573 clocks = <&apb1_gates 15>;
1574 status = "disabled";
1575 #address-cells = <1>;
1576 #size-cells = <0>;
1577 };
1578
1579 gmac: ethernet@01c50000 {
1580 compatible = "allwinner,sun7i-a20-gmac";
1581 reg = <0x01c50000 0x10000>;
1582 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1583 interrupt-names = "macirq";
1584 clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
1585 clock-names = "stmmaceth", "allwinner_gmac_tx";
1586 snps,pbl = <2>;
1587 snps,fixed-burst;
1588 snps,force_sf_dma_mode;
1589 status = "disabled";
1590 #address-cells = <1>;
1591 #size-cells = <0>;
1592 };
1593
1594 hstimer@01c60000 {
1595 compatible = "allwinner,sun7i-a20-hstimer";
1596 reg = <0x01c60000 0x1000>;
1597 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1598 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1599 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1600 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1601 clocks = <&ahb_gates 28>;
1602 };
1603
1604 gic: interrupt-controller@01c81000 {
1605 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1606 reg = <0x01c81000 0x1000>,
1607 <0x01c82000 0x1000>,
1608 <0x01c84000 0x2000>,
1609 <0x01c86000 0x2000>;
1610 interrupt-controller;
1611 #interrupt-cells = <3>;
1612 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1613 };
1614
1615 ps20: ps2@01c2a000 {
1616 compatible = "allwinner,sun4i-a10-ps2";
1617 reg = <0x01c2a000 0x400>;
1618 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1619 clocks = <&apb1_gates 6>;
1620 status = "disabled";
1621 };
1622
1623 ps21: ps2@01c2a400 {
1624 compatible = "allwinner,sun4i-a10-ps2";
1625 reg = <0x01c2a400 0x400>;
1626 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1627 clocks = <&apb1_gates 7>;
1628 status = "disabled";
1629 };
1630 };
1631 };
Linux kernel - Deliverables
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