arch/arm/include/asm/cachetype.h

   1 #ifndef __ASM_ARM_CACHETYPE_H
   2 #define __ASM_ARM_CACHETYPE_H
   3
   4 #define CACHEID_VIVT                    (1 << 0)
   5 #define CACHEID_VIPT_NONALIASING        (1 << 1)
   6 #define CACHEID_VIPT_ALIASING           (1 << 2)
   7 #define CACHEID_VIPT                    (CACHEID_VIPT_ALIASING|CACHEID_VIPT_NONALIASING)
   8 #define CACHEID_ASID_TAGGED             (1 << 3)
   9 #define CACHEID_VIPT_I_ALIASING         (1 << 4)
  10 #define CACHEID_PIPT                    (1 << 5)
  11
  12 extern unsigned int cacheid;
  13
  14 #define cache_is_vivt()                 cacheid_is(CACHEID_VIVT)
  15 #define cache_is_vipt()                 cacheid_is(CACHEID_VIPT)
  16 #define cache_is_vipt_nonaliasing()     cacheid_is(CACHEID_VIPT_NONALIASING)
  17 #define cache_is_vipt_aliasing()        cacheid_is(CACHEID_VIPT_ALIASING)
  18 #define icache_is_vivt_asid_tagged()    cacheid_is(CACHEID_ASID_TAGGED)
  19 #define icache_is_vipt_aliasing()       cacheid_is(CACHEID_VIPT_I_ALIASING)
  20 #define icache_is_pipt()                cacheid_is(CACHEID_PIPT)
  21
  22 /*
  23  * __LINUX_ARM_ARCH__ is the minimum supported CPU architecture
  24  * Mask out support which will never be present on newer CPUs.
  25  * - v6+ is never VIVT
  26  * - v7+ VIPT never aliases on D-side
  27  */
  28 #if __LINUX_ARM_ARCH__ >= 7
  29 #define __CACHEID_ARCH_MIN      (CACHEID_VIPT_NONALIASING |\
  30                                  CACHEID_ASID_TAGGED |\
  31                                  CACHEID_VIPT_I_ALIASING |\
  32                                  CACHEID_PIPT)
  33 #elif __LINUX_ARM_ARCH__ >= 6
  34 #define __CACHEID_ARCH_MIN      (~CACHEID_VIVT)
  35 #else
  36 #define __CACHEID_ARCH_MIN      (~0)
  37 #endif
  38
  39 /*
  40  * Mask out support which isn't configured
  41  */
  42 #if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
  43 #define __CACHEID_ALWAYS        (CACHEID_VIVT)
  44 #define __CACHEID_NEVER         (~CACHEID_VIVT)
  45 #elif !defined(CONFIG_CPU_CACHE_VIVT) && defined(CONFIG_CPU_CACHE_VIPT)
  46 #define __CACHEID_ALWAYS        (0)
  47 #define __CACHEID_NEVER         (CACHEID_VIVT)
  48 #else
  49 #define __CACHEID_ALWAYS        (0)
  50 #define __CACHEID_NEVER         (0)
  51 #endif
  52
  53 static inline unsigned int __attribute__((pure)) cacheid_is(unsigned int mask)
  54 {
  55         return (__CACHEID_ALWAYS & mask) |
  56                (~__CACHEID_NEVER & __CACHEID_ARCH_MIN & mask & cacheid);
  57 }
  58
  59 #define CSSELR_ICACHE   1
  60 #define CSSELR_DCACHE   0
  61
  62 #define CSSELR_L1       (0 << 1)
  63 #define CSSELR_L2       (1 << 1)
  64 #define CSSELR_L3       (2 << 1)
  65 #define CSSELR_L4       (3 << 1)
  66 #define CSSELR_L5       (4 << 1)
  67 #define CSSELR_L6       (5 << 1)
  68 #define CSSELR_L7       (6 << 1)
  69
  70 #ifndef CONFIG_CPU_V7M
  71 static inline void set_csselr(unsigned int cache_selector)
  72 {
  73         asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (cache_selector));
  74 }
  75
  76 static inline unsigned int read_ccsidr(void)
  77 {
  78         unsigned int val;
  79
  80         asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (val));
  81         return val;
  82 }
  83 #else /* CONFIG_CPU_V7M */
  84 #include <linux/io.h>
  85 #include "asm/v7m.h"
  86
  87 static inline void set_csselr(unsigned int cache_selector)
  88 {
  89         writel(cache_selector, BASEADDR_V7M_SCB + V7M_SCB_CTR);
  90 }
  91
  92 static inline unsigned int read_ccsidr(void)
  93 {
  94         return readl(BASEADDR_V7M_SCB + V7M_SCB_CCSIDR);
  95 }
  96 #endif
  97
  98 #endif