arch/arm/include/asm/cputype.h

   1 #ifndef __ASM_ARM_CPUTYPE_H
   2 #define __ASM_ARM_CPUTYPE_H
   3
   4 #include <linux/stringify.h>
   5 #include <linux/kernel.h>
   6
   7 #define CPUID_ID        0
   8 #define CPUID_CACHETYPE 1
   9 #define CPUID_TCM       2
  10 #define CPUID_TLBTYPE   3
  11 #define CPUID_MPUIR     4
  12 #define CPUID_MPIDR     5
  13 #define CPUID_REVIDR    6
  14
  15 #ifdef CONFIG_CPU_V7M
  16 #define CPUID_EXT_PFR0  0x40
  17 #define CPUID_EXT_PFR1  0x44
  18 #define CPUID_EXT_DFR0  0x48
  19 #define CPUID_EXT_AFR0  0x4c
  20 #define CPUID_EXT_MMFR0 0x50
  21 #define CPUID_EXT_MMFR1 0x54
  22 #define CPUID_EXT_MMFR2 0x58
  23 #define CPUID_EXT_MMFR3 0x5c
  24 #define CPUID_EXT_ISAR0 0x60
  25 #define CPUID_EXT_ISAR1 0x64
  26 #define CPUID_EXT_ISAR2 0x68
  27 #define CPUID_EXT_ISAR3 0x6c
  28 #define CPUID_EXT_ISAR4 0x70
  29 #define CPUID_EXT_ISAR5 0x74
  30 #else
  31 #define CPUID_EXT_PFR0  "c1, 0"
  32 #define CPUID_EXT_PFR1  "c1, 1"
  33 #define CPUID_EXT_DFR0  "c1, 2"
  34 #define CPUID_EXT_AFR0  "c1, 3"
  35 #define CPUID_EXT_MMFR0 "c1, 4"
  36 #define CPUID_EXT_MMFR1 "c1, 5"
  37 #define CPUID_EXT_MMFR2 "c1, 6"
  38 #define CPUID_EXT_MMFR3 "c1, 7"
  39 #define CPUID_EXT_ISAR0 "c2, 0"
  40 #define CPUID_EXT_ISAR1 "c2, 1"
  41 #define CPUID_EXT_ISAR2 "c2, 2"
  42 #define CPUID_EXT_ISAR3 "c2, 3"
  43 #define CPUID_EXT_ISAR4 "c2, 4"
  44 #define CPUID_EXT_ISAR5 "c2, 5"
  45 #endif
  46
  47 #define MPIDR_SMP_BITMASK (0x3 << 30)
  48 #define MPIDR_SMP_VALUE (0x2 << 30)
  49
  50 #define MPIDR_MT_BITMASK (0x1 << 24)
  51
  52 #define MPIDR_HWID_BITMASK 0xFFFFFF
  53
  54 #define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
  55
  56 #define MPIDR_LEVEL_BITS 8
  57 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
  58
  59 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
  60         ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
  61
  62 #define ARM_CPU_IMP_ARM                 0x41
  63 #define ARM_CPU_IMP_DEC                 0x44
  64 #define ARM_CPU_IMP_INTEL               0x69
  65
  66 /* ARM implemented processors */
  67 #define ARM_CPU_PART_ARM1136            0x4100b360
  68 #define ARM_CPU_PART_ARM1156            0x4100b560
  69 #define ARM_CPU_PART_ARM1176            0x4100b760
  70 #define ARM_CPU_PART_ARM11MPCORE        0x4100b020
  71 #define ARM_CPU_PART_CORTEX_A8          0x4100c080
  72 #define ARM_CPU_PART_CORTEX_A9          0x4100c090
  73 #define ARM_CPU_PART_CORTEX_A5          0x4100c050
  74 #define ARM_CPU_PART_CORTEX_A7          0x4100c070
  75 #define ARM_CPU_PART_CORTEX_A12         0x4100c0d0
  76 #define ARM_CPU_PART_CORTEX_A17         0x4100c0e0
  77 #define ARM_CPU_PART_CORTEX_A15         0x4100c0f0
  78 #define ARM_CPU_PART_MASK               0xff00fff0
  79
  80 /* DEC implemented cores */
  81 #define ARM_CPU_PART_SA1100             0x4400a110
  82
  83 /* Intel implemented cores */
  84 #define ARM_CPU_PART_SA1110             0x6900b110
  85 #define ARM_CPU_REV_SA1110_A0           0
  86 #define ARM_CPU_REV_SA1110_B0           4
  87 #define ARM_CPU_REV_SA1110_B1           5
  88 #define ARM_CPU_REV_SA1110_B2           6
  89 #define ARM_CPU_REV_SA1110_B4           8
  90
  91 #define ARM_CPU_XSCALE_ARCH_MASK        0xe000
  92 #define ARM_CPU_XSCALE_ARCH_V1          0x2000
  93 #define ARM_CPU_XSCALE_ARCH_V2          0x4000
  94 #define ARM_CPU_XSCALE_ARCH_V3          0x6000
  95
  96 extern unsigned int processor_id;
  97
  98 #ifdef CONFIG_CPU_CP15
  99 #define read_cpuid(reg)                                                 \
 100         ({                                                              \
 101                 unsigned int __val;                                     \
 102                 asm("mrc        p15, 0, %0, c0, c0, " __stringify(reg)  \
 103                     : "=r" (__val)                                      \
 104                     :                                                   \
 105                     : "cc");                                            \
 106                 __val;                                                  \
 107         })
 108
 109 /*
 110  * The memory clobber prevents gcc 4.5 from reordering the mrc before
 111  * any is_smp() tests, which can cause undefined instruction aborts on
 112  * ARM1136 r0 due to the missing extended CP15 registers.
 113  */
 114 #define read_cpuid_ext(ext_reg)                                         \
 115         ({                                                              \
 116                 unsigned int __val;                                     \
 117                 asm("mrc        p15, 0, %0, c0, " ext_reg               \
 118                     : "=r" (__val)                                      \
 119                     :                                                   \
 120                     : "memory");                                        \
 121                 __val;                                                  \
 122         })
 123
 124 #elif defined(CONFIG_CPU_V7M)
 125
 126 #include <asm/io.h>
 127 #include <asm/v7m.h>
 128
 129 #define read_cpuid(reg)                                                 \
 130         ({                                                              \
 131                 WARN_ON_ONCE(1);                                        \
 132                 0;                                                      \
 133         })
 134
 135 static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
 136 {
 137         return readl(BASEADDR_V7M_SCB + offset);
 138 }
 139
 140 #else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
 141
 142 /*
 143  * read_cpuid and read_cpuid_ext should only ever be called on machines that
 144  * have cp15 so warn on other usages.
 145  */
 146 #define read_cpuid(reg)                                                 \
 147         ({                                                              \
 148                 WARN_ON_ONCE(1);                                        \
 149                 0;                                                      \
 150         })
 151
 152 #define read_cpuid_ext(reg) read_cpuid(reg)
 153
 154 #endif /* ifdef CONFIG_CPU_CP15 / else */
 155
 156 #ifdef CONFIG_CPU_CP15
 157 /*
 158  * The CPU ID never changes at run time, so we might as well tell the
 159  * compiler that it's constant.  Use this function to read the CPU ID
 160  * rather than directly reading processor_id or read_cpuid() directly.
 161  */
 162 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 163 {
 164         return read_cpuid(CPUID_ID);
 165 }
 166
 167 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
 168 {
 169         return read_cpuid(CPUID_CACHETYPE);
 170 }
 171
 172 #elif defined(CONFIG_CPU_V7M)
 173
 174 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 175 {
 176         return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
 177 }
 178
 179 static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
 180 {
 181         return readl(BASEADDR_V7M_SCB + V7M_SCB_CTR);
 182 }
 183
 184 #else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
 185
 186 static inline unsigned int __attribute_const__ read_cpuid_id(void)
 187 {
 188         return processor_id;
 189 }
 190
 191 #endif /* ifdef CONFIG_CPU_CP15 / else */
 192
 193 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
 194 {
 195         return (read_cpuid_id() & 0xFF000000) >> 24;
 196 }
 197
 198 static inline unsigned int __attribute_const__ read_cpuid_revision(void)
 199 {
 200         return read_cpuid_id() & 0x0000000f;
 201 }
 202
 203 /*
 204  * The CPU part number is meaningless without referring to the CPU
 205  * implementer: implementers are free to define their own part numbers
 206  * which are permitted to clash with other implementer part numbers.
 207  */
 208 static inline unsigned int __attribute_const__ read_cpuid_part(void)
 209 {
 210         return read_cpuid_id() & ARM_CPU_PART_MASK;
 211 }
 212
 213 static inline unsigned int __attribute_const__ __deprecated read_cpuid_part_number(void)
 214 {
 215         return read_cpuid_id() & 0xFFF0;
 216 }
 217
 218 static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
 219 {
 220         return read_cpuid_id() & ARM_CPU_XSCALE_ARCH_MASK;
 221 }
 222
 223 static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
 224 {
 225         return read_cpuid(CPUID_TCM);
 226 }
 227
 228 static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
 229 {
 230         return read_cpuid(CPUID_MPIDR);
 231 }
 232
 233 /* StrongARM-11x0 CPUs */
 234 #define cpu_is_sa1100() (read_cpuid_part() == ARM_CPU_PART_SA1100)
 235 #define cpu_is_sa1110() (read_cpuid_part() == ARM_CPU_PART_SA1110)
 236
 237 /*
 238  * Intel's XScale3 core supports some v6 features (supersections, L2)
 239  * but advertises itself as v5 as it does not support the v6 ISA.  For
 240  * this reason, we need a way to explicitly test for this type of CPU.
 241  */
 242 #ifndef CONFIG_CPU_XSC3
 243 #define cpu_is_xsc3()   0
 244 #else
 245 static inline int cpu_is_xsc3(void)
 246 {
 247         unsigned int id;
 248         id = read_cpuid_id() & 0xffffe000;
 249         /* It covers both Intel ID and Marvell ID */
 250         if ((id == 0x69056000) || (id == 0x56056000))
 251                 return 1;
 252
 253         return 0;
 254 }
 255 #endif
 256
 257 #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) && \
 258     !defined(CONFIG_CPU_MOHAWK)
 259 #define cpu_is_xscale_family() 0
 260 #else
 261 static inline int cpu_is_xscale_family(void)
 262 {
 263         unsigned int id;
 264         id = read_cpuid_id() & 0xffffe000;
 265
 266         switch (id) {
 267         case 0x69052000: /* Intel XScale 1 */
 268         case 0x69054000: /* Intel XScale 2 */
 269         case 0x69056000: /* Intel XScale 3 */
 270         case 0x56056000: /* Marvell XScale 3 */
 271         case 0x56158000: /* Marvell Mohawk */
 272                 return 1;
 273         }
 274
 275         return 0;
 276 }
 277 #endif
 278
 279 /*
 280  * Marvell's PJ4 and PJ4B cores are based on V7 version,
 281  * but require a specical sequence for enabling coprocessors.
 282  * For this reason, we need a way to distinguish them.
 283  */
 284 #if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
 285 static inline int cpu_is_pj4(void)
 286 {
 287         unsigned int id;
 288
 289         id = read_cpuid_id();
 290         if ((id & 0xff0fff00) == 0x560f5800)
 291                 return 1;
 292
 293         return 0;
 294 }
 295 #else
 296 #define cpu_is_pj4()    0
 297 #endif
 298
 299 static inline int __attribute_const__ cpuid_feature_extract_field(u32 features,
 300                                                                   int field)
 301 {
 302         int feature = (features >> field) & 15;
 303
 304         /* feature registers are signed values */
 305         if (feature > 7)
 306                 feature -= 16;
 307
 308         return feature;
 309 }
 310
 311 #define cpuid_feature_extract(reg, field) \
 312         cpuid_feature_extract_field(read_cpuid_ext(reg), field)
 313
 314 #endif