arch/arm/mach-ux500/cache-l2x0.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2011
   3  *
   4  * License terms: GNU General Public License (GPL) version 2
   5  */
   6
   7 #include <linux/io.h>
   8 #include <linux/of.h>
   9 #include <linux/of_address.h>
  10
  11 #include <asm/outercache.h>
  12 #include <asm/hardware/cache-l2x0.h>
  13
  14 #include "db8500-regs.h"
  15
  16 static int __init ux500_l2x0_unlock(void)
  17 {
  18         int i;
  19         struct device_node *np;
  20         void __iomem *l2x0_base;
  21
  22         np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
  23         l2x0_base = of_iomap(np, 0);
  24         of_node_put(np);
  25         if (!l2x0_base)
  26                 return -ENODEV;
  27
  28         /*
  29          * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions
  30          * apparently locks both caches before jumping to the kernel. The
  31          * l2x0 core will not touch the unlock registers if the l2x0 is
  32          * already enabled, so we do it right here instead. The PL310 has
  33          * 8 sets of registers, one per possible CPU.
  34          */
  35         for (i = 0; i < 8; i++) {
  36                 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
  37                                i * L2X0_LOCKDOWN_STRIDE);
  38                 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
  39                                i * L2X0_LOCKDOWN_STRIDE);
  40         }
  41         iounmap(l2x0_base);
  42         return 0;
  43 }
  44
  45 static void ux500_l2c310_write_sec(unsigned long val, unsigned reg)
  46 {
  47         /*
  48          * We can't write to secure registers as we are in non-secure
  49          * mode, until we have some SMI service available.
  50          */
  51 }
  52
  53 void __init ux500_l2x0_init(void)
  54 {
  55         /* Unlock before init */
  56         ux500_l2x0_unlock();
  57         outer_cache.write_sec = ux500_l2c310_write_sec;
  58
  59         return 0;
  60 }