arch/arm/mm/proc-v7m.S

   1 /*
   2  *  linux/arch/arm/mm/proc-v7m.S
   3  *
   4  *  Copyright (C) 2008 ARM Ltd.
   5  *  Copyright (C) 2001 Deep Blue Solutions Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  *  This is the "shell" of the ARMv7-M processor support.
  12  */
  13 #include <linux/linkage.h>
  14 #include <asm/assembler.h>
  15 #include <asm/memory.h>
  16 #include <asm/v7m.h>
  17 #include "proc-macros.S"
  18
  19 ENTRY(cpu_v7m_proc_init)
  20         ret     lr
  21 ENDPROC(cpu_v7m_proc_init)
  22
  23 ENTRY(cpu_v7m_proc_fin)
  24         ret     lr
  25 ENDPROC(cpu_v7m_proc_fin)
  26
  27 /*
  28  *      cpu_v7m_reset(loc)
  29  *
  30  *      Perform a soft reset of the system.  Put the CPU into the
  31  *      same state as it would be if it had been reset, and branch
  32  *      to what would be the reset vector.
  33  *
  34  *      - loc   - location to jump to for soft reset
  35  */
  36         .align  5
  37 ENTRY(cpu_v7m_reset)
  38         ret     r0
  39 ENDPROC(cpu_v7m_reset)
  40
  41 /*
  42  *      cpu_v7m_do_idle()
  43  *
  44  *      Idle the processor (eg, wait for interrupt).
  45  *
  46  *      IRQs are already disabled.
  47  */
  48 ENTRY(cpu_v7m_do_idle)
  49         wfi
  50         ret     lr
  51 ENDPROC(cpu_v7m_do_idle)
  52
  53 ENTRY(cpu_v7m_dcache_clean_area)
  54         ret     lr
  55 ENDPROC(cpu_v7m_dcache_clean_area)
  56
  57 /*
  58  * There is no MMU, so here is nothing to do.
  59  */
  60 ENTRY(cpu_v7m_switch_mm)
  61         ret     lr
  62 ENDPROC(cpu_v7m_switch_mm)
  63
  64 .globl  cpu_v7m_suspend_size
  65 .equ    cpu_v7m_suspend_size, 0
  66
  67 #ifdef CONFIG_ARM_CPU_SUSPEND
  68 ENTRY(cpu_v7m_do_suspend)
  69         ret     lr
  70 ENDPROC(cpu_v7m_do_suspend)
  71
  72 ENTRY(cpu_v7m_do_resume)
  73         ret     lr
  74 ENDPROC(cpu_v7m_do_resume)
  75 #endif
  76
  77         .section ".text.init", #alloc, #execinstr
  78
  79 /*
  80  *      __v7m_setup
  81  *
  82  *      This should be able to cover all ARMv7-M cores.
  83  */
  84 __v7m_setup:
  85         @ Configure the vector table base address
  86         ldr     r0, =BASEADDR_V7M_SCB
  87         ldr     r12, =vector_table
  88         str     r12, [r0, V7M_SCB_VTOR]
  89
  90         @ enable UsageFault, BusFault and MemManage fault.
  91         ldr     r5, [r0, #V7M_SCB_SHCSR]
  92         orr     r5, #(V7M_SCB_SHCSR_USGFAULTENA | V7M_SCB_SHCSR_BUSFAULTENA | V7M_SCB_SHCSR_MEMFAULTENA)
  93         str     r5, [r0, #V7M_SCB_SHCSR]
  94
  95         @ Lower the priority of the SVC and PendSV exceptions
  96         mov     r5, #0x80000000
  97         str     r5, [r0, V7M_SCB_SHPR2] @ set SVC priority
  98         mov     r5, #0x00800000
  99         str     r5, [r0, V7M_SCB_SHPR3] @ set PendSV priority
 100
 101         @ SVC to switch to handler mode. Notice that this requires sp to
 102         @ point to writeable memory because the processor saves
 103         @ some registers to the stack.
 104         badr    r1, 1f
 105         ldr     r5, [r12, #11 * 4]      @ read the SVC vector entry
 106         str     r1, [r12, #11 * 4]      @ write the temporary SVC vector entry
 107         mov     r6, lr                  @ save LR
 108         ldr     sp, =init_thread_union + THREAD_START_SP
 109         cpsie   i
 110         svc     #0
 111 1:      cpsid   i
 112         str     r5, [r12, #11 * 4]      @ restore the original SVC vector entry
 113         mov     lr, r6                  @ restore LR
 114
 115         @ Special-purpose control register
 116         mov     r1, #1
 117         msr     control, r1             @ Thread mode has unpriviledged access
 118
 119         @ Configure the System Control Register to ensure 8-byte stack alignment
 120         @ Note the STKALIGN bit is either RW or RAO.
 121         ldr     r12, [r0, V7M_SCB_CCR]  @ system control register
 122         orr     r12, #V7M_SCB_CCR_STKALIGN
 123         str     r12, [r0, V7M_SCB_CCR]
 124         ret     lr
 125 ENDPROC(__v7m_setup)
 126
 127         define_processor_functions v7m, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
 128
 129         .section ".rodata"
 130         string cpu_arch_name, "armv7m"
 131         string cpu_elf_name "v7m"
 132         string cpu_v7m_name "ARMv7-M"
 133
 134         .section ".proc.info.init", #alloc
 135
 136         /*
 137          * Match any ARMv7-M processor core.
 138          */
 139         .type   __v7m_proc_info, #object
 140 __v7m_proc_info:
 141         .long   0x000f0000              @ Required ID value
 142         .long   0x000f0000              @ Mask for ID
 143         .long   0                       @ proc_info_list.__cpu_mm_mmu_flags
 144         .long   0                       @ proc_info_list.__cpu_io_mmu_flags
 145         initfn  __v7m_setup, __v7m_proc_info    @ proc_info_list.__cpu_flush
 146         .long   cpu_arch_name
 147         .long   cpu_elf_name
 148         .long   HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT
 149         .long   cpu_v7m_name
 150         .long   v7m_processor_functions @ proc_info_list.proc
 151         .long   0                       @ proc_info_list.tlb
 152         .long   0                       @ proc_info_list.user
 153         .long   nop_cache_fns           @ proc_info_list.cache
 154         .size   __v7m_proc_info, . - __v7m_proc_info
 155