arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi

   1 /*
   2  * Copyright (c) 2016 Andreas Färber
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/gpio/gpio.h>
  44 #include <dt-bindings/interrupt-controller/irq.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/gpio/meson-gxbb-gpio.h>
  47 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
  48 #include <dt-bindings/clock/gxbb-clkc.h>
  49 #include <dt-bindings/clock/gxbb-aoclkc.h>
  50 #include <dt-bindings/reset/gxbb-aoclkc.h>
  51
  52 / {
  53         compatible = "amlogic,meson-gxbb";
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         cpus {
  59                 #address-cells = <0x2>;
  60                 #size-cells = <0x0>;
  61
  62                 cpu0: cpu@0 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a53", "arm,armv8";
  65                         reg = <0x0 0x0>;
  66                         enable-method = "psci";
  67                 };
  68
  69                 cpu1: cpu@1 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a53", "arm,armv8";
  72                         reg = <0x0 0x1>;
  73                         enable-method = "psci";
  74                 };
  75
  76                 cpu2: cpu@2 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a53", "arm,armv8";
  79                         reg = <0x0 0x2>;
  80                         enable-method = "psci";
  81                 };
  82
  83                 cpu3: cpu@3 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a53", "arm,armv8";
  86                         reg = <0x0 0x3>;
  87                         enable-method = "psci";
  88                 };
  89         };
  90
  91         arm-pmu {
  92                 compatible = "arm,cortex-a53-pmu";
  93                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
  94                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
  95                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  96                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  97                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  98         };
  99
 100         psci {
 101                 compatible = "arm,psci-0.2";
 102                 method = "smc";
 103         };
 104
 105         firmware {
 106                 sm: secure-monitor {
 107                         compatible = "amlogic,meson-gxbb-sm";
 108                 };
 109         };
 110
 111         efuse: efuse {
 112                 compatible = "amlogic,meson-gxbb-efuse";
 113                 #address-cells = <1>;
 114                 #size-cells = <1>;
 115
 116                 sn: sn@14 {
 117                         reg = <0x14 0x10>;
 118                 };
 119
 120                 eth_mac: eth_mac@34 {
 121                         reg = <0x34 0x10>;
 122                 };
 123
 124                 bid: bid@46 {
 125                         reg = <0x46 0x30>;
 126                 };
 127         };
 128
 129         timer {
 130                 compatible = "arm,armv8-timer";
 131                 interrupts = <GIC_PPI 13
 132                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
 133                              <GIC_PPI 14
 134                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
 135                              <GIC_PPI 11
 136                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
 137                              <GIC_PPI 10
 138                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
 139         };
 140
 141         xtal: xtal-clk {
 142                 compatible = "fixed-clock";
 143                 clock-frequency = <24000000>;
 144                 clock-output-names = "xtal";
 145                 #clock-cells = <0>;
 146         };
 147
 148         soc {
 149                 compatible = "simple-bus";
 150                 #address-cells = <2>;
 151                 #size-cells = <2>;
 152                 ranges;
 153
 154                 cbus: cbus@c1100000 {
 155                         compatible = "simple-bus";
 156                         reg = <0x0 0xc1100000 0x0 0x100000>;
 157                         #address-cells = <2>;
 158                         #size-cells = <2>;
 159                         ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
 160
 161                         reset: reset-controller@4404 {
 162                                 compatible = "amlogic,meson-gxbb-reset";
 163                                 reg = <0x0 0x04404 0x0 0x20>;
 164                                 #reset-cells = <1>;
 165                         };
 166
 167                         uart_A: serial@84c0 {
 168                                 compatible = "amlogic,meson-uart";
 169                                 reg = <0x0 0x84c0 0x0 0x14>;
 170                                 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
 171                                 clocks = <&xtal>;
 172                                 status = "disabled";
 173                         };
 174
 175                         uart_B: serial@84dc {
 176                                 compatible = "amlogic,meson-uart";
 177                                 reg = <0x0 0x84dc 0x0 0x14>;
 178                                 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
 179                                 clocks = <&xtal>;
 180                                 status = "disabled";
 181                         };
 182
 183                         uart_C: serial@8700 {
 184                                 compatible = "amlogic,meson-uart";
 185                                 reg = <0x0 0x8700 0x0 0x14>;
 186                                 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
 187                                 clocks = <&xtal>;
 188                                 status = "disabled";
 189                         };
 190
 191                         watchdog@98d0 {
 192                                 compatible = "amlogic,meson-gxbb-wdt";
 193                                 reg = <0x0 0x098d0 0x0 0x10>;
 194                                 clocks = <&xtal>;
 195                         };
 196                 };
 197
 198                 gic: interrupt-controller@c4301000 {
 199                         compatible = "arm,gic-400";
 200                         reg = <0x0 0xc4301000 0 0x1000>,
 201                               <0x0 0xc4302000 0 0x2000>,
 202                               <0x0 0xc4304000 0 0x2000>,
 203                               <0x0 0xc4306000 0 0x2000>;
 204                         interrupt-controller;
 205                         interrupts = <GIC_PPI 9
 206                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 207                         #interrupt-cells = <3>;
 208                         #address-cells = <0>;
 209                 };
 210
 211                 aobus: aobus@c8100000 {
 212                         compatible = "simple-bus";
 213                         reg = <0x0 0xc8100000 0x0 0x100000>;
 214                         #address-cells = <2>;
 215                         #size-cells = <2>;
 216                         ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
 217
 218                         pinctrl_aobus: pinctrl@14 {
 219                                 compatible = "amlogic,meson-gxbb-aobus-pinctrl";
 220                                 #address-cells = <2>;
 221                                 #size-cells = <2>;
 222                                 ranges;
 223
 224                                 gpio_ao: bank@14 {
 225                                         reg = <0x0 0x00014 0x0 0x8>,
 226                                               <0x0 0x0002c 0x0 0x4>,
 227                                               <0x0 0x00024 0x0 0x8>;
 228                                         reg-names = "mux", "pull", "gpio";
 229                                         gpio-controller;
 230                                         #gpio-cells = <2>;
 231                                 };
 232
 233                                 uart_ao_a_pins: uart_ao_a {
 234                                         mux {
 235                                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
 236                                                 function = "uart_ao";
 237                                         };
 238                                 };
 239
 240                                 remote_input_ao_pins: remote_input_ao {
 241                                         mux {
 242                                                 groups = "remote_input_ao";
 243                                                 function = "remote_input_ao";
 244                                         };
 245                                 };
 246
 247                                 pwm_ao_a_3_pins: pwm_ao_a_3 {
 248                                         mux {
 249                                                 groups = "pwm_ao_a_3";
 250                                                 function = "pwm_ao_a_3";
 251                                         };
 252                                 };
 253
 254                                 pwm_ao_a_6_pins: pwm_ao_a_6 {
 255                                         mux {
 256                                                 groups = "pwm_ao_a_6";
 257                                                 function = "pwm_ao_a_6";
 258                                         };
 259                                 };
 260
 261                                 pwm_ao_a_12_pins: pwm_ao_a_12 {
 262                                         mux {
 263                                                 groups = "pwm_ao_a_12";
 264                                                 function = "pwm_ao_a_12";
 265                                         };
 266                                 };
 267
 268                                 pwm_ao_b_pins: pwm_ao_b {
 269                                         mux {
 270                                                 groups = "pwm_ao_b";
 271                                                 function = "pwm_ao_b";
 272                                         };
 273                                 };
 274                         };
 275
 276                         clkc_AO: clock-controller@040 {
 277                                 compatible = "amlogic,gxbb-aoclkc";
 278                                 reg = <0x0 0x00040 0x0 0x4>;
 279                                 #clock-cells = <1>;
 280                                 #reset-cells = <1>;
 281                         };
 282
 283                         uart_AO: serial@4c0 {
 284                                 compatible = "amlogic,meson-uart";
 285                                 reg = <0x0 0x004c0 0x0 0x14>;
 286                                 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
 287                                 clocks = <&xtal>;
 288                                 status = "disabled";
 289                         };
 290
 291                         ir: ir@580 {
 292                                 compatible = "amlogic,meson-gxbb-ir";
 293                                 reg = <0x0 0x00580 0x0 0x40>;
 294                                 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
 295                                 status = "disabled";
 296                         };
 297                 };
 298
 299                 periphs: periphs@c8834000 {
 300                         compatible = "simple-bus";
 301                         reg = <0x0 0xc8834000 0x0 0x2000>;
 302                         #address-cells = <2>;
 303                         #size-cells = <2>;
 304                         ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
 305
 306                         rng {
 307                                 compatible = "amlogic,meson-rng";
 308                                 reg = <0x0 0x0 0x0 0x4>;
 309                         };
 310
 311                         pinctrl_periphs: pinctrl@4b0 {
 312                                 compatible = "amlogic,meson-gxbb-periphs-pinctrl";
 313                                 #address-cells = <2>;
 314                                 #size-cells = <2>;
 315                                 ranges;
 316
 317                                 gpio: bank@4b0 {
 318                                         reg = <0x0 0x004b0 0x0 0x28>,
 319                                               <0x0 0x004e8 0x0 0x14>,
 320                                               <0x0 0x00120 0x0 0x14>,
 321                                               <0x0 0x00430 0x0 0x40>;
 322                                         reg-names = "mux", "pull", "pull-enable", "gpio";
 323                                         gpio-controller;
 324                                         #gpio-cells = <2>;
 325                                 };
 326
 327                                 emmc_pins: emmc {
 328                                         mux {
 329                                                 groups = "emmc_nand_d07",
 330                                                        "emmc_cmd",
 331                                                        "emmc_clk",
 332                                                        "emmc_ds";
 333                                                 function = "emmc";
 334                                         };
 335                                 };
 336
 337                                 sdcard_pins: sdcard {
 338                                         mux {
 339                                                 groups = "sdcard_d0",
 340                                                        "sdcard_d1",
 341                                                        "sdcard_d2",
 342                                                        "sdcard_d3",
 343                                                        "sdcard_cmd",
 344                                                        "sdcard_clk";
 345                                                 function = "sdcard";
 346                                         };
 347                                 };
 348
 349                                 uart_a_pins: uart_a {
 350                                         mux {
 351                                                 groups = "uart_tx_a",
 352                                                        "uart_rx_a";
 353                                                 function = "uart_a";
 354                                         };
 355                                 };
 356
 357                                 uart_b_pins: uart_b {
 358                                         mux {
 359                                                 groups = "uart_tx_b",
 360                                                        "uart_rx_b";
 361                                                 function = "uart_b";
 362                                         };
 363                                 };
 364
 365                                 uart_c_pins: uart_c {
 366                                         mux {
 367                                                 groups = "uart_tx_c",
 368                                                        "uart_rx_c";
 369                                                 function = "uart_c";
 370                                         };
 371                                 };
 372
 373                                 eth_pins: eth_c {
 374                                         mux {
 375                                                 groups = "eth_mdio",
 376                                                        "eth_mdc",
 377                                                        "eth_clk_rx_clk",
 378                                                        "eth_rx_dv",
 379                                                        "eth_rxd0",
 380                                                        "eth_rxd1",
 381                                                        "eth_rxd2",
 382                                                        "eth_rxd3",
 383                                                        "eth_rgmii_tx_clk",
 384                                                        "eth_tx_en",
 385                                                        "eth_txd0",
 386                                                        "eth_txd1",
 387                                                        "eth_txd2",
 388                                                        "eth_txd3";
 389                                                 function = "eth";
 390                                         };
 391                                 };
 392
 393                                 pwm_a_x_pins: pwm_a_x {
 394                                         mux {
 395                                                 groups = "pwm_a_x";
 396                                                 function = "pwm_a_x";
 397                                         };
 398                                 };
 399
 400                                 pwm_a_y_pins: pwm_a_y {
 401                                         mux {
 402                                                 groups = "pwm_a_y";
 403                                                 function = "pwm_a_y";
 404                                         };
 405                                 };
 406
 407                                 pwm_b_pins: pwm_b {
 408                                         mux {
 409                                                 groups = "pwm_b";
 410                                                 function = "pwm_b";
 411                                         };
 412                                 };
 413
 414                                 pwm_d_pins: pwm_d {
 415                                         mux {
 416                                                 groups = "pwm_d";
 417                                                 function = "pwm_d";
 418                                         };
 419                                 };
 420
 421                                 pwm_e_pins: pwm_e {
 422                                         mux {
 423                                                 groups = "pwm_e";
 424                                                 function = "pwm_e";
 425                                         };
 426                                 };
 427
 428                                 pwm_f_x_pins: pwm_f_x {
 429                                         mux {
 430                                                 groups = "pwm_f_x";
 431                                                 function = "pwm_f_x";
 432                                         };
 433                                 };
 434
 435                                 pwm_f_y_pins: pwm_f_y {
 436                                         mux {
 437                                                 groups = "pwm_f_y";
 438                                                 function = "pwm_f_y";
 439                                         };
 440                                 };
 441                         };
 442                 };
 443
 444                 hiubus: hiubus@c883c000 {
 445                         compatible = "simple-bus";
 446                         reg = <0x0 0xc883c000 0x0 0x2000>;
 447                         #address-cells = <2>;
 448                         #size-cells = <2>;
 449                         ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
 450
 451                         clkc: clock-controller@0 {
 452                                 compatible = "amlogic,gxbb-clkc";
 453                                 #clock-cells = <1>;
 454                                 reg = <0x0 0x0 0x0 0x3db>;
 455                         };
 456                 };
 457
 458                 apb: apb@d0000000 {
 459                         compatible = "simple-bus";
 460                         reg = <0x0 0xd0000000 0x0 0x200000>;
 461                         #address-cells = <2>;
 462                         #size-cells = <2>;
 463                         ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
 464
 465                         sd_emmc_a: mmc@70000 {
 466                                 compatible = "amlogic,meson-gxbb-mmc";
 467                                 reg = <0x0 0x70000 0x0 0x2000>;
 468                                 interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
 469                                 clocks = <&clkc CLKID_SD_EMMC_A>,
 470                                          <&xtal>,
 471                                          <&clkc CLKID_FCLK_DIV2>;
 472                                 clock-names = "core", "clkin0", "clkin1";
 473                                 status = "disabled";
 474                         };
 475
 476                         sd_emmc_b: mmc@72000 {
 477                                 compatible = "amlogic,meson-gxbb-mmc";
 478                                 reg = <0x0 0x72000 0x0 0x2000>;
 479                                 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
 480                                 clocks = <&clkc CLKID_SD_EMMC_B>,
 481                                          <&xtal>,
 482                                          <&clkc CLKID_FCLK_DIV2>;
 483                                 clock-names = "core", "clkin0", "clkin1";
 484                                 status = "disabled";
 485                         };
 486
 487                         sd_emmc_c: mmc@74000 {
 488                                 compatible = "amlogic,meson-gxbb-mmc";
 489                                 reg = <0x0 0x74000 0x0 0x2000>;
 490                                 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
 491                                 clocks = <&clkc CLKID_SD_EMMC_C>,
 492                                          <&xtal>,
 493                                          <&clkc CLKID_FCLK_DIV2>;
 494                                 clock-names = "core", "clkin0", "clkin1";
 495                                 status = "disabled";
 496                         };
 497                 };
 498
 499                 ethmac: ethernet@c9410000 {
 500                         compatible = "amlogic,meson6-dwmac", "snps,dwmac";
 501                         reg = <0x0 0xc9410000 0x0 0x10000
 502                                0x0 0xc8834540 0x0 0x4>;
 503                         interrupts = <0 8 1>;
 504                         interrupt-names = "macirq";
 505                         clocks = <&clkc CLKID_ETH>;
 506                         clock-names = "stmmaceth";
 507                         phy-mode = "rgmii";
 508                         status = "disabled";
 509                 };
 510         };
 511 };