arch/arm64/boot/dts/marvell/berlin4ct.dtsi

   1 /*
   2  * Copyright (C) 2015 Marvell Technology Group Ltd.
   3  *
   4  * Author: Jisheng Zhang <jszhang@marvell.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPLv2 or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This library is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This library is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46
  47 / {
  48         compatible = "marvell,berlin4ct", "marvell,berlin";
  49         interrupt-parent = <&gic>;
  50         #address-cells = <2>;
  51         #size-cells = <2>;
  52
  53         aliases {
  54                 serial0 = &uart0;
  55         };
  56
  57         psci {
  58                 compatible = "arm,psci-1.0", "arm,psci-0.2";
  59                 method = "smc";
  60         };
  61
  62         cpus {
  63                 #address-cells = <1>;
  64                 #size-cells = <0>;
  65
  66                 cpu0: cpu@0 {
  67                         compatible = "arm,cortex-a53", "arm,armv8";
  68                         device_type = "cpu";
  69                         reg = <0x0>;
  70                         enable-method = "psci";
  71                         cpu-idle-states = <&CPU_SLEEP_0>;
  72                 };
  73
  74                 cpu1: cpu@1 {
  75                         compatible = "arm,cortex-a53", "arm,armv8";
  76                         device_type = "cpu";
  77                         reg = <0x1>;
  78                         enable-method = "psci";
  79                         cpu-idle-states = <&CPU_SLEEP_0>;
  80                 };
  81
  82                 cpu2: cpu@2 {
  83                         compatible = "arm,cortex-a53", "arm,armv8";
  84                         device_type = "cpu";
  85                         reg = <0x2>;
  86                         enable-method = "psci";
  87                         cpu-idle-states = <&CPU_SLEEP_0>;
  88                 };
  89
  90                 cpu3: cpu@3 {
  91                         compatible = "arm,cortex-a53", "arm,armv8";
  92                         device_type = "cpu";
  93                         reg = <0x3>;
  94                         enable-method = "psci";
  95                         cpu-idle-states = <&CPU_SLEEP_0>;
  96                 };
  97
  98                 idle-states {
  99                         entry-method = "psci";
 100                         CPU_SLEEP_0: cpu-sleep-0 {
 101                                 compatible = "arm,idle-state";
 102                                 local-timer-stop;
 103                                 arm,psci-suspend-param = <0x0010000>;
 104                                 entry-latency-us = <75>;
 105                                 exit-latency-us = <155>;
 106                                 min-residency-us = <1000>;
 107                         };
 108                 };
 109         };
 110
 111         osc: osc {
 112                 compatible = "fixed-clock";
 113                 #clock-cells = <0>;
 114                 clock-frequency = <25000000>;
 115         };
 116
 117         pmu {
 118                 compatible = "arm,armv8-pmuv3";
 119                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
 120                              <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
 121                              <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
 122                              <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 123                 interrupt-affinity = <&cpu0>,
 124                                      <&cpu1>,
 125                                      <&cpu2>,
 126                                      <&cpu3>;
 127         };
 128
 129         timer {
 130                 compatible = "arm,armv8-timer";
 131                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 132                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 133                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 134                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 135         };
 136
 137         soc {
 138                 compatible = "simple-bus";
 139                 #address-cells = <1>;
 140                 #size-cells = <1>;
 141                 ranges = <0 0 0xf7000000 0x1000000>;
 142
 143                 gic: interrupt-controller@901000 {
 144                         compatible = "arm,gic-400";
 145                         #interrupt-cells = <3>;
 146                         interrupt-controller;
 147                         reg = <0x901000 0x1000>,
 148                               <0x902000 0x2000>,
 149                               <0x904000 0x2000>,
 150                               <0x906000 0x2000>;
 151                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 152                 };
 153
 154                 apb@e80000 {
 155                         compatible = "simple-bus";
 156                         #address-cells = <1>;
 157                         #size-cells = <1>;
 158
 159                         ranges = <0 0xe80000 0x10000>;
 160                         interrupt-parent = <&aic>;
 161
 162                         gpio0: gpio@0400 {
 163                                 compatible = "snps,dw-apb-gpio";
 164                                 reg = <0x0400 0x400>;
 165                                 #address-cells = <1>;
 166                                 #size-cells = <0>;
 167
 168                                 porta: gpio-port@0 {
 169                                         compatible = "snps,dw-apb-gpio-port";
 170                                         gpio-controller;
 171                                         #gpio-cells = <2>;
 172                                         snps,nr-gpios = <32>;
 173                                         reg = <0>;
 174                                         interrupt-controller;
 175                                         #interrupt-cells = <2>;
 176                                         interrupts = <0>;
 177                                 };
 178                         };
 179
 180                         gpio1: gpio@0800 {
 181                                 compatible = "snps,dw-apb-gpio";
 182                                 reg = <0x0800 0x400>;
 183                                 #address-cells = <1>;
 184                                 #size-cells = <0>;
 185
 186                                 portb: gpio-port@1 {
 187                                         compatible = "snps,dw-apb-gpio-port";
 188                                         gpio-controller;
 189                                         #gpio-cells = <2>;
 190                                         snps,nr-gpios = <32>;
 191                                         reg = <0>;
 192                                         interrupt-controller;
 193                                         #interrupt-cells = <2>;
 194                                         interrupts = <1>;
 195                                 };
 196                         };
 197
 198                         gpio2: gpio@0c00 {
 199                                 compatible = "snps,dw-apb-gpio";
 200                                 reg = <0x0c00 0x400>;
 201                                 #address-cells = <1>;
 202                                 #size-cells = <0>;
 203
 204                                 portc: gpio-port@2 {
 205                                         compatible = "snps,dw-apb-gpio-port";
 206                                         gpio-controller;
 207                                         #gpio-cells = <2>;
 208                                         snps,nr-gpios = <32>;
 209                                         reg = <0>;
 210                                         interrupt-controller;
 211                                         #interrupt-cells = <2>;
 212                                         interrupts = <2>;
 213                                 };
 214                         };
 215
 216                         gpio3: gpio@1000 {
 217                                 compatible = "snps,dw-apb-gpio";
 218                                 reg = <0x1000 0x400>;
 219                                 #address-cells = <1>;
 220                                 #size-cells = <0>;
 221
 222                                 portd: gpio-port@3 {
 223                                         compatible = "snps,dw-apb-gpio-port";
 224                                         gpio-controller;
 225                                         #gpio-cells = <2>;
 226                                         snps,nr-gpios = <32>;
 227                                         reg = <0>;
 228                                         interrupt-controller;
 229                                         #interrupt-cells = <2>;
 230                                         interrupts = <3>;
 231                                 };
 232                         };
 233
 234                         aic: interrupt-controller@3800 {
 235                                 compatible = "snps,dw-apb-ictl";
 236                                 reg = <0x3800 0x30>;
 237                                 interrupt-controller;
 238                                 #interrupt-cells = <1>;
 239                                 interrupt-parent = <&gic>;
 240                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 241                         };
 242                 };
 243
 244                 soc_pinctrl: pin-controller@ea8000 {
 245                         compatible = "marvell,berlin4ct-soc-pinctrl";
 246                         reg = <0xea8000 0x14>;
 247                 };
 248
 249                 avio_pinctrl: pin-controller@ea8400 {
 250                         compatible = "marvell,berlin4ct-avio-pinctrl";
 251                         reg = <0xea8400 0x8>;
 252                 };
 253
 254                 apb@fc0000 {
 255                         compatible = "simple-bus";
 256                         #address-cells = <1>;
 257                         #size-cells = <1>;
 258                         ranges = <0 0xfc0000 0x10000>;
 259                         interrupt-parent = <&sic>;
 260
 261                         sic: interrupt-controller@1000 {
 262                                 compatible = "snps,dw-apb-ictl";
 263                                 reg = <0x1000 0x30>;
 264                                 interrupt-controller;
 265                                 #interrupt-cells = <1>;
 266                                 interrupt-parent = <&gic>;
 267                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 268                         };
 269
 270                         wdt0: watchdog@3000 {
 271                                 compatible = "snps,dw-wdt";
 272                                 reg = <0x3000 0x100>;
 273                                 clocks = <&osc>;
 274                                 interrupts = <0>;
 275                         };
 276
 277                         wdt1: watchdog@4000 {
 278                                 compatible = "snps,dw-wdt";
 279                                 reg = <0x4000 0x100>;
 280                                 clocks = <&osc>;
 281                                 interrupts = <1>;
 282                                 status = "disabled";
 283                         };
 284
 285                         wdt2: watchdog@5000 {
 286                                 compatible = "snps,dw-wdt";
 287                                 reg = <0x5000 0x100>;
 288                                 clocks = <&osc>;
 289                                 interrupts = <2>;
 290                                 status = "disabled";
 291                         };
 292
 293                         sm_gpio0: gpio@8000 {
 294                                 compatible = "snps,dw-apb-gpio";
 295                                 reg = <0x8000 0x400>;
 296                                 #address-cells = <1>;
 297                                 #size-cells = <0>;
 298
 299                                 porte: gpio-port@4 {
 300                                         compatible = "snps,dw-apb-gpio-port";
 301                                         gpio-controller;
 302                                         #gpio-cells = <2>;
 303                                         snps,nr-gpios = <32>;
 304                                         reg = <0>;
 305                                 };
 306                         };
 307
 308                         sm_gpio1: gpio@9000 {
 309                                 compatible = "snps,dw-apb-gpio";
 310                                 reg = <0x9000 0x400>;
 311                                 #address-cells = <1>;
 312                                 #size-cells = <0>;
 313
 314                                 portf: gpio-port@5 {
 315                                         compatible = "snps,dw-apb-gpio-port";
 316                                         gpio-controller;
 317                                         #gpio-cells = <2>;
 318                                         snps,nr-gpios = <32>;
 319                                         reg = <0>;
 320                                 };
 321                         };
 322
 323                         uart0: uart@d000 {
 324                                 compatible = "snps,dw-apb-uart";
 325                                 reg = <0xd000 0x100>;
 326                                 interrupts = <8>;
 327                                 clocks = <&osc>;
 328                                 reg-shift = <2>;
 329                                 status = "disabled";
 330                                 pinctrl-0 = <&uart0_pmux>;
 331                                 pinctrl-names = "default";
 332                         };
 333                 };
 334
 335                 system_pinctrl: pin-controller@fe2200 {
 336                         compatible = "marvell,berlin4ct-system-pinctrl";
 337                         reg = <0xfe2200 0xc>;
 338
 339                         uart0_pmux: uart0-pmux {
 340                                 groups = "SM_URT0_TXD", "SM_URT0_RXD";
 341                                 function = "uart0";
 342                         };
 343                 };
 344         };
 345 };