arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts

   1 /*
   2  * Device Tree Source for the H3ULCB board
   3  *
   4  * Copyright (C) 2016 Renesas Electronics Corp.
   5  * Copyright (C) 2016 Cogent Embedded, Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 /dts-v1/;
  13 #include "r8a7795.dtsi"
  14 #include <dt-bindings/gpio/gpio.h>
  15 #include <dt-bindings/input/input.h>
  16
  17 / {
  18         model = "Renesas H3ULCB board based on r8a7795";
  19         compatible = "renesas,h3ulcb", "renesas,r8a7795";
  20
  21         aliases {
  22                 serial0 = &scif2;
  23                 ethernet0 = &avb;
  24         };
  25
  26         chosen {
  27                 stdout-path = "serial0:115200n8";
  28         };
  29
  30         memory@48000000 {
  31                 device_type = "memory";
  32                 /* first 128MB is reserved for secure area. */
  33                 reg = <0x0 0x48000000 0x0 0x38000000>;
  34         };
  35
  36         leds {
  37                 compatible = "gpio-leds";
  38
  39                 led5 {
  40                         gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
  41                 };
  42                 led6 {
  43                         gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
  44                 };
  45         };
  46
  47         keyboard {
  48                 compatible = "gpio-keys";
  49
  50                 key-1 {
  51                         linux,code = <KEY_1>;
  52                         label = "SW3";
  53                         wakeup-source;
  54                         debounce-interval = <20>;
  55                         gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
  56                 };
  57         };
  58
  59         x12_clk: x12 {
  60                 compatible = "fixed-clock";
  61                 #clock-cells = <0>;
  62                 clock-frequency = <24576000>;
  63         };
  64
  65         vcc_sdhi0: regulator-vcc-sdhi0 {
  66                 compatible = "regulator-fixed";
  67
  68                 regulator-name = "SDHI0 Vcc";
  69                 regulator-min-microvolt = <3300000>;
  70                 regulator-max-microvolt = <3300000>;
  71
  72                 gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
  73                 enable-active-high;
  74         };
  75
  76         vccq_sdhi0: regulator-vccq-sdhi0 {
  77                 compatible = "regulator-gpio";
  78
  79                 regulator-name = "SDHI0 VccQ";
  80                 regulator-min-microvolt = <1800000>;
  81                 regulator-max-microvolt = <3300000>;
  82
  83                 gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
  84                 gpios-states = <1>;
  85                 states = <3300000 1
  86                           1800000 0>;
  87         };
  88
  89         audio_clkout: audio-clkout {
  90                 /*
  91                  * This is same as <&rcar_sound 0>
  92                  * but needed to avoid cs2000/rcar_sound probe dead-lock
  93                  */
  94                 compatible = "fixed-clock";
  95                 #clock-cells = <0>;
  96                 clock-frequency = <11289600>;
  97         };
  98
  99         rsnd_ak4613: sound {
 100                 compatible = "simple-audio-card";
 101
 102                 simple-audio-card,format = "left_j";
 103                 simple-audio-card,bitclock-master = <&sndcpu>;
 104                 simple-audio-card,frame-master = <&sndcpu>;
 105
 106                 sndcpu: simple-audio-card,cpu {
 107                         sound-dai = <&rcar_sound>;
 108                 };
 109
 110                 sndcodec: simple-audio-card,codec {
 111                         sound-dai = <&ak4613>;
 112                 };
 113         };
 114 };
 115
 116 &extal_clk {
 117         clock-frequency = <16666666>;
 118 };
 119
 120 &extalr_clk {
 121         clock-frequency = <32768>;
 122 };
 123
 124 &pfc {
 125         pinctrl-0 = <&scif_clk_pins>;
 126         pinctrl-names = "default";
 127
 128         scif2_pins: scif2 {
 129                 groups = "scif2_data_a";
 130                 function = "scif2";
 131         };
 132
 133         scif_clk_pins: scif_clk {
 134                 groups = "scif_clk_a";
 135                 function = "scif_clk";
 136         };
 137
 138         i2c2_pins: i2c2 {
 139                 groups = "i2c2_a";
 140                 function = "i2c2";
 141         };
 142
 143         avb_pins: avb {
 144                 groups = "avb_mdc";
 145                 function = "avb";
 146         };
 147
 148         sdhi0_pins_3v3: sd0_3v3 {
 149                 groups = "sdhi0_data4", "sdhi0_ctrl";
 150                 function = "sdhi0";
 151                 power-source = <3300>;
 152         };
 153
 154         sdhi0_pins_1v8: sd0_1v8 {
 155                 groups = "sdhi0_data4", "sdhi0_ctrl";
 156                 function = "sdhi0";
 157                 power-source = <1800>;
 158         };
 159
 160         sound_pins: sound {
 161                 groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
 162                 function = "ssi";
 163         };
 164
 165         sound_clk_pins: sound-clk {
 166                 groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
 167                          "audio_clkout_a", "audio_clkout3_a";
 168                 function = "audio_clk";
 169         };
 170
 171         usb1_pins: usb1 {
 172                 groups = "usb1";
 173                 function = "usb1";
 174         };
 175 };
 176
 177 &scif2 {
 178         pinctrl-0 = <&scif2_pins>;
 179         pinctrl-names = "default";
 180
 181         status = "okay";
 182 };
 183
 184 &scif_clk {
 185         clock-frequency = <14745600>;
 186         status = "okay";
 187 };
 188
 189 &i2c2 {
 190         pinctrl-0 = <&i2c2_pins>;
 191         pinctrl-names = "default";
 192
 193         status = "okay";
 194
 195         clock-frequency = <100000>;
 196
 197         ak4613: codec@10 {
 198                 compatible = "asahi-kasei,ak4613";
 199                 #sound-dai-cells = <0>;
 200                 reg = <0x10>;
 201                 clocks = <&rcar_sound 3>;
 202
 203                 asahi-kasei,in1-single-end;
 204                 asahi-kasei,in2-single-end;
 205                 asahi-kasei,out1-single-end;
 206                 asahi-kasei,out2-single-end;
 207                 asahi-kasei,out3-single-end;
 208                 asahi-kasei,out4-single-end;
 209                 asahi-kasei,out5-single-end;
 210                 asahi-kasei,out6-single-end;
 211         };
 212
 213         cs2000: clk-multiplier@4f {
 214                 #clock-cells = <0>;
 215                 compatible = "cirrus,cs2000-cp";
 216                 reg = <0x4f>;
 217                 clocks = <&audio_clkout>, <&x12_clk>;
 218                 clock-names = "clk_in", "ref_clk";
 219
 220                 assigned-clocks = <&cs2000>;
 221                 assigned-clock-rates = <24576000>; /* 1/1 divide */
 222         };
 223 };
 224
 225 &rcar_sound {
 226         pinctrl-0 = <&sound_pins &sound_clk_pins>;
 227         pinctrl-names = "default";
 228
 229         /* Single DAI */
 230         #sound-dai-cells = <0>;
 231
 232         /* audio_clkout0/1/2/3 */
 233         #clock-cells = <1>;
 234         clock-frequency = <11289600>;
 235
 236         status = "okay";
 237
 238         /* update <audio_clk_b> to <cs2000> */
 239         clocks = <&cpg CPG_MOD 1005>,
 240                  <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
 241                  <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
 242                  <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
 243                  <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
 244                  <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
 245                  <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
 246                  <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
 247                  <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
 248                  <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
 249                  <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
 250                  <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
 251                  <&audio_clk_a>, <&cs2000>,
 252                  <&audio_clk_c>,
 253                  <&cpg CPG_CORE R8A7795_CLK_S0D4>;
 254
 255         rcar_sound,dai {
 256                 dai0 {
 257                         playback = <&ssi0 &src0 &dvc0>;
 258                         capture  = <&ssi1 &src1 &dvc1>;
 259                 };
 260         };
 261 };
 262
 263 &sdhi0 {
 264         pinctrl-0 = <&sdhi0_pins_3v3>;
 265         pinctrl-1 = <&sdhi0_pins_1v8>;
 266         pinctrl-names = "default", "state_uhs";
 267
 268         vmmc-supply = <&vcc_sdhi0>;
 269         vqmmc-supply = <&vccq_sdhi0>;
 270         cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
 271         bus-width = <4>;
 272         sd-uhs-sdr50;
 273         status = "okay";
 274 };
 275
 276 &ssi1 {
 277         shared-pin;
 278 };
 279
 280 &wdt0 {
 281         timeout-sec = <60>;
 282         status = "okay";
 283 };
 284
 285 &audio_clk_a {
 286         clock-frequency = <22579200>;
 287 };
 288
 289 &avb {
 290         pinctrl-0 = <&avb_pins>;
 291         pinctrl-names = "default";
 292         renesas,no-ether-link;
 293         phy-handle = <&phy0>;
 294         status = "okay";
 295
 296         phy0: ethernet-phy@0 {
 297                 rxc-skew-ps = <900>;
 298                 rxdv-skew-ps = <0>;
 299                 rxd0-skew-ps = <0>;
 300                 rxd1-skew-ps = <0>;
 301                 rxd2-skew-ps = <0>;
 302                 rxd3-skew-ps = <0>;
 303                 txc-skew-ps = <900>;
 304                 txen-skew-ps = <0>;
 305                 txd0-skew-ps = <0>;
 306                 txd1-skew-ps = <0>;
 307                 txd2-skew-ps = <0>;
 308                 txd3-skew-ps = <0>;
 309                 reg = <0>;
 310                 interrupt-parent = <&gpio2>;
 311                 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
 312         };
 313 };
 314
 315 &usb2_phy1 {
 316         pinctrl-0 = <&usb1_pins>;
 317         pinctrl-names = "default";
 318
 319         status = "okay";
 320 };
 321
 322 &ehci1 {
 323         status = "okay";
 324 };
 325
 326 &ohci1 {
 327         status = "okay";
 328 };