arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts

   1 /*
   2  * Device Tree Source for the Salvator-X board
   3  *
   4  * Copyright (C) 2015 Renesas Electronics Corp.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 /*
  12  * SSI-AK4613
  13  *
  14  * This command is required when Playback/Capture
  15  *
  16  *      amixer set "DVC Out" 100%
  17  *      amixer set "DVC In" 100%
  18  *
  19  * You can use Mute
  20  *
  21  *      amixer set "DVC Out Mute" on
  22  *      amixer set "DVC In Mute" on
  23  *
  24  * You can use Volume Ramp
  25  *
  26  *      amixer set "DVC Out Ramp Up Rate"   "0.125 dB/64 steps"
  27  *      amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
  28  *      amixer set "DVC Out Ramp" on
  29  *      aplay xxx.wav &
  30  *      amixer set "DVC Out"  80%  // Volume Down
  31  *      amixer set "DVC Out" 100%  // Volume Up
  32  */
  33
  34 /dts-v1/;
  35 #include "r8a7795.dtsi"
  36 #include <dt-bindings/gpio/gpio.h>
  37
  38 / {
  39         model = "Renesas Salvator-X board based on r8a7795";
  40         compatible = "renesas,salvator-x", "renesas,r8a7795";
  41
  42         aliases {
  43                 serial0 = &scif2;
  44                 serial1 = &scif1;
  45                 ethernet0 = &avb;
  46         };
  47
  48         chosen {
  49                 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
  50                 stdout-path = "serial0:115200n8";
  51         };
  52
  53         memory@48000000 {
  54                 device_type = "memory";
  55                 /* first 128MB is reserved for secure area. */
  56                 reg = <0x0 0x48000000 0x0 0x38000000>;
  57         };
  58
  59         x12_clk: x12_clk {
  60                 compatible = "fixed-clock";
  61                 #clock-cells = <0>;
  62                 clock-frequency = <24576000>;
  63         };
  64
  65         vcc_sdhi0: regulator-vcc-sdhi0 {
  66                 compatible = "regulator-fixed";
  67
  68                 regulator-name = "SDHI0 Vcc";
  69                 regulator-min-microvolt = <3300000>;
  70                 regulator-max-microvolt = <3300000>;
  71
  72                 gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
  73                 enable-active-high;
  74         };
  75
  76         vccq_sdhi0: regulator-vccq-sdhi0 {
  77                 compatible = "regulator-gpio";
  78
  79                 regulator-name = "SDHI0 VccQ";
  80                 regulator-min-microvolt = <1800000>;
  81                 regulator-max-microvolt = <3300000>;
  82
  83                 gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
  84                 gpios-states = <1>;
  85                 states = <3300000 1
  86                           1800000 0>;
  87         };
  88
  89         vcc_sdhi3: regulator-vcc-sdhi3 {
  90                 compatible = "regulator-fixed";
  91
  92                 regulator-name = "SDHI3 Vcc";
  93                 regulator-min-microvolt = <3300000>;
  94                 regulator-max-microvolt = <3300000>;
  95
  96                 gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
  97                 enable-active-high;
  98         };
  99
 100         vccq_sdhi3: regulator-vccq-sdhi3 {
 101                 compatible = "regulator-gpio";
 102
 103                 regulator-name = "SDHI3 VccQ";
 104                 regulator-min-microvolt = <1800000>;
 105                 regulator-max-microvolt = <3300000>;
 106
 107                 gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
 108                 gpios-states = <1>;
 109                 states = <3300000 1
 110                           1800000 0>;
 111         };
 112
 113         audio_clkout: audio_clkout {
 114                 /*
 115                  * This is same as <&rcar_sound 0>
 116                  * but needed to avoid cs2000/rcar_sound probe dead-lock
 117                  */
 118                 compatible = "fixed-clock";
 119                 #clock-cells = <0>;
 120                 clock-frequency = <11289600>;
 121         };
 122
 123         rsnd_ak4613: sound {
 124                 compatible = "simple-audio-card";
 125
 126                 simple-audio-card,format = "left_j";
 127                 simple-audio-card,bitclock-master = <&sndcpu>;
 128                 simple-audio-card,frame-master = <&sndcpu>;
 129
 130                 sndcpu: simple-audio-card,cpu {
 131                         sound-dai = <&rcar_sound>;
 132                 };
 133
 134                 sndcodec: simple-audio-card,codec {
 135                         sound-dai = <&ak4613>;
 136                 };
 137         };
 138 };
 139
 140 &extal_clk {
 141         clock-frequency = <16666666>;
 142 };
 143
 144 &extalr_clk {
 145         clock-frequency = <32768>;
 146 };
 147
 148 &pfc {
 149         pinctrl-0 = <&scif_clk_pins>;
 150         pinctrl-names = "default";
 151
 152         scif1_pins: scif1 {
 153                 groups = "scif1_data_a", "scif1_ctrl";
 154                 function = "scif1";
 155         };
 156         scif2_pins: scif2 {
 157                 groups = "scif2_data_a";
 158                 function = "scif2";
 159         };
 160         scif_clk_pins: scif_clk {
 161                 groups = "scif_clk_a";
 162                 function = "scif_clk";
 163         };
 164
 165         i2c2_pins: i2c2 {
 166                 groups = "i2c2_a";
 167                 function = "i2c2";
 168         };
 169
 170         avb_pins: avb {
 171                 groups = "avb_mdc";
 172                 function = "avb";
 173         };
 174
 175         sdhi0_pins: sd0 {
 176                 groups = "sdhi0_data4", "sdhi0_ctrl";
 177                 function = "sdhi0";
 178         };
 179
 180         sdhi3_pins: sd3 {
 181                 groups = "sdhi3_data4", "sdhi3_ctrl";
 182                 function = "sdhi3";
 183         };
 184
 185         sound_pins: sound {
 186                 groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
 187                 function = "ssi";
 188         };
 189
 190         sound_clk_pins: sound_clk {
 191                 groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
 192                          "audio_clkout_a", "audio_clkout3_a";
 193                 function = "audio_clk";
 194         };
 195
 196         usb1_pins: usb1 {
 197                 groups = "usb1";
 198                 function = "usb1";
 199         };
 200
 201         usb2_pins: usb2 {
 202                 groups = "usb2";
 203                 function = "usb2";
 204         };
 205 };
 206
 207 &scif1 {
 208         pinctrl-0 = <&scif1_pins>;
 209         pinctrl-names = "default";
 210
 211         uart-has-rtscts;
 212         status = "okay";
 213 };
 214
 215 &scif2 {
 216         pinctrl-0 = <&scif2_pins>;
 217         pinctrl-names = "default";
 218
 219         status = "okay";
 220 };
 221
 222 &scif_clk {
 223         clock-frequency = <14745600>;
 224         status = "okay";
 225 };
 226
 227 &i2c2 {
 228         pinctrl-0 = <&i2c2_pins>;
 229         pinctrl-names = "default";
 230
 231         status = "okay";
 232
 233         clock-frequency = <100000>;
 234
 235         ak4613: codec@10 {
 236                 compatible = "asahi-kasei,ak4613";
 237                 #sound-dai-cells = <0>;
 238                 reg = <0x10>;
 239                 clocks = <&rcar_sound 3>;
 240
 241                 asahi-kasei,in1-single-end;
 242                 asahi-kasei,in2-single-end;
 243                 asahi-kasei,out1-single-end;
 244                 asahi-kasei,out2-single-end;
 245                 asahi-kasei,out3-single-end;
 246                 asahi-kasei,out4-single-end;
 247                 asahi-kasei,out5-single-end;
 248                 asahi-kasei,out6-single-end;
 249         };
 250
 251         cs2000: clk_multiplier@4f {
 252                 #clock-cells = <0>;
 253                 compatible = "cirrus,cs2000-cp";
 254                 reg = <0x4f>;
 255                 clocks = <&audio_clkout>, <&x12_clk>;
 256                 clock-names = "clk_in", "ref_clk";
 257
 258                 assigned-clocks = <&cs2000>;
 259                 assigned-clock-rates = <24576000>; /* 1/1 divide */
 260         };
 261 };
 262
 263 &rcar_sound {
 264         pinctrl-0 = <&sound_pins &sound_clk_pins>;
 265         pinctrl-names = "default";
 266
 267         /* Single DAI */
 268         #sound-dai-cells = <0>;
 269
 270         /* audio_clkout0/1/2/3 */
 271         #clock-cells = <1>;
 272         clock-frequency = <11289600>;
 273
 274         status = "okay";
 275
 276         /* update <audio_clk_b> to <cs2000> */
 277         clocks = <&cpg CPG_MOD 1005>,
 278                  <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
 279                  <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
 280                  <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
 281                  <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
 282                  <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
 283                  <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
 284                  <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
 285                  <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
 286                  <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
 287                  <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
 288                  <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
 289                  <&audio_clk_a>, <&cs2000>,
 290                  <&audio_clk_c>,
 291                  <&cpg CPG_CORE R8A7795_CLK_S0D4>;
 292
 293         rcar_sound,dai {
 294                 dai0 {
 295                         playback = <&ssi0 &src0 &dvc0>;
 296                         capture  = <&ssi1 &src1 &dvc1>;
 297                 };
 298         };
 299 };
 300
 301 &sata {
 302         status = "okay";
 303 };
 304
 305 &sdhi0 {
 306         pinctrl-0 = <&sdhi0_pins>;
 307         pinctrl-names = "default";
 308
 309         vmmc-supply = <&vcc_sdhi0>;
 310         vqmmc-supply = <&vccq_sdhi0>;
 311         cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
 312         wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
 313         bus-width = <4>;
 314         status = "okay";
 315 };
 316
 317 &sdhi3 {
 318         pinctrl-0 = <&sdhi3_pins>;
 319         pinctrl-names = "default";
 320
 321         vmmc-supply = <&vcc_sdhi3>;
 322         vqmmc-supply = <&vccq_sdhi3>;
 323         cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
 324         wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
 325         bus-width = <4>;
 326         status = "okay";
 327 };
 328
 329 &ssi1 {
 330         shared-pin;
 331 };
 332
 333 &wdt0 {
 334         timeout-sec = <60>;
 335         status = "okay";
 336 };
 337
 338 &audio_clk_a {
 339         clock-frequency = <22579200>;
 340 };
 341
 342 &avb {
 343         pinctrl-0 = <&avb_pins>;
 344         pinctrl-names = "default";
 345         renesas,no-ether-link;
 346         phy-handle = <&phy0>;
 347         status = "okay";
 348
 349         phy0: ethernet-phy@0 {
 350                 rxc-skew-ps = <900>;
 351                 rxdv-skew-ps = <0>;
 352                 rxd0-skew-ps = <0>;
 353                 rxd1-skew-ps = <0>;
 354                 rxd2-skew-ps = <0>;
 355                 rxd3-skew-ps = <0>;
 356                 txc-skew-ps = <900>;
 357                 txen-skew-ps = <0>;
 358                 txd0-skew-ps = <0>;
 359                 txd1-skew-ps = <0>;
 360                 txd2-skew-ps = <0>;
 361                 txd3-skew-ps = <0>;
 362                 reg = <0>;
 363                 interrupt-parent = <&gpio2>;
 364                 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
 365         };
 366 };
 367
 368 &xhci0 {
 369         status = "okay";
 370 };
 371
 372 &usb2_phy1 {
 373         pinctrl-0 = <&usb1_pins>;
 374         pinctrl-names = "default";
 375
 376         status = "okay";
 377 };
 378
 379 &usb2_phy2 {
 380         pinctrl-0 = <&usb2_pins>;
 381         pinctrl-names = "default";
 382
 383         status = "okay";
 384 };
 385
 386 &ehci1 {
 387         status = "okay";
 388 };
 389
 390 &ehci2 {
 391         status = "okay";
 392 };
 393
 394 &ohci1 {
 395         status = "okay";
 396 };
 397
 398 &ohci2 {
 399         status = "okay";
 400 };
 401
 402 &pcie_bus_clk {
 403         clock-frequency = <100000000>;
 404         status = "okay";
 405 };
 406
 407 &pciec0 {
 408         status = "okay";
 409 };
 410
 411 &pciec1 {
 412         status = "okay";
 413 };