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Merge remote-tracking branch 'kspp/for-next/kspp'
[deliverable/linux.git] / arch / arm64 / boot / dts / rockchip / rk3368.dtsi
1 /*
2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/soc/rockchip,boot-mode.h>
49 #include <dt-bindings/thermal/thermal.h>
50
51 / {
52 compatible = "rockchip,rk3368";
53 interrupt-parent = <&gic>;
54 #address-cells = <2>;
55 #size-cells = <2>;
56
57 aliases {
58 ethernet0 = &gmac;
59 i2c0 = &i2c0;
60 i2c1 = &i2c1;
61 i2c2 = &i2c2;
62 i2c3 = &i2c3;
63 i2c4 = &i2c4;
64 i2c5 = &i2c5;
65 serial0 = &uart0;
66 serial1 = &uart1;
67 serial2 = &uart2;
68 serial3 = &uart3;
69 serial4 = &uart4;
70 spi0 = &spi0;
71 spi1 = &spi1;
72 spi2 = &spi2;
73 };
74
75 cpus {
76 #address-cells = <0x2>;
77 #size-cells = <0x0>;
78
79 cpu-map {
80 cluster0 {
81 core0 {
82 cpu = <&cpu_b0>;
83 };
84 core1 {
85 cpu = <&cpu_b1>;
86 };
87 core2 {
88 cpu = <&cpu_b2>;
89 };
90 core3 {
91 cpu = <&cpu_b3>;
92 };
93 };
94
95 cluster1 {
96 core0 {
97 cpu = <&cpu_l0>;
98 };
99 core1 {
100 cpu = <&cpu_l1>;
101 };
102 core2 {
103 cpu = <&cpu_l2>;
104 };
105 core3 {
106 cpu = <&cpu_l3>;
107 };
108 };
109 };
110
111 idle-states {
112 entry-method = "psci";
113
114 cpu_sleep: cpu-sleep-0 {
115 compatible = "arm,idle-state";
116 arm,psci-suspend-param = <0x1010000>;
117 entry-latency-us = <0x3fffffff>;
118 exit-latency-us = <0x40000000>;
119 min-residency-us = <0xffffffff>;
120 };
121 };
122
123 cpu_l0: cpu@0 {
124 device_type = "cpu";
125 compatible = "arm,cortex-a53", "arm,armv8";
126 reg = <0x0 0x0>;
127 cpu-idle-states = <&cpu_sleep>;
128 enable-method = "psci";
129
130 #cooling-cells = <2>; /* min followed by max */
131 };
132
133 cpu_l1: cpu@1 {
134 device_type = "cpu";
135 compatible = "arm,cortex-a53", "arm,armv8";
136 reg = <0x0 0x1>;
137 cpu-idle-states = <&cpu_sleep>;
138 enable-method = "psci";
139 };
140
141 cpu_l2: cpu@2 {
142 device_type = "cpu";
143 compatible = "arm,cortex-a53", "arm,armv8";
144 reg = <0x0 0x2>;
145 cpu-idle-states = <&cpu_sleep>;
146 enable-method = "psci";
147 };
148
149 cpu_l3: cpu@3 {
150 device_type = "cpu";
151 compatible = "arm,cortex-a53", "arm,armv8";
152 reg = <0x0 0x3>;
153 cpu-idle-states = <&cpu_sleep>;
154 enable-method = "psci";
155 };
156
157 cpu_b0: cpu@100 {
158 device_type = "cpu";
159 compatible = "arm,cortex-a53", "arm,armv8";
160 reg = <0x0 0x100>;
161 cpu-idle-states = <&cpu_sleep>;
162 enable-method = "psci";
163
164 #cooling-cells = <2>; /* min followed by max */
165 };
166
167 cpu_b1: cpu@101 {
168 device_type = "cpu";
169 compatible = "arm,cortex-a53", "arm,armv8";
170 reg = <0x0 0x101>;
171 cpu-idle-states = <&cpu_sleep>;
172 enable-method = "psci";
173 };
174
175 cpu_b2: cpu@102 {
176 device_type = "cpu";
177 compatible = "arm,cortex-a53", "arm,armv8";
178 reg = <0x0 0x102>;
179 cpu-idle-states = <&cpu_sleep>;
180 enable-method = "psci";
181 };
182
183 cpu_b3: cpu@103 {
184 device_type = "cpu";
185 compatible = "arm,cortex-a53", "arm,armv8";
186 reg = <0x0 0x103>;
187 cpu-idle-states = <&cpu_sleep>;
188 enable-method = "psci";
189 };
190 };
191
192 arm-pmu {
193 compatible = "arm,armv8-pmuv3";
194 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
202 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
203 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
204 <&cpu_b2>, <&cpu_b3>;
205 };
206
207 psci {
208 compatible = "arm,psci-0.2";
209 method = "smc";
210 };
211
212 timer {
213 compatible = "arm,armv8-timer";
214 interrupts = <GIC_PPI 13
215 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
216 <GIC_PPI 14
217 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
218 <GIC_PPI 11
219 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
220 <GIC_PPI 10
221 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
222 };
223
224 xin24m: oscillator {
225 compatible = "fixed-clock";
226 clock-frequency = <24000000>;
227 clock-output-names = "xin24m";
228 #clock-cells = <0>;
229 };
230
231 sdmmc: dwmmc@ff0c0000 {
232 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
233 reg = <0x0 0xff0c0000 0x0 0x4000>;
234 clock-freq-min-max = <400000 150000000>;
235 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
236 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
237 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
238 fifo-depth = <0x100>;
239 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
240 status = "disabled";
241 };
242
243 sdio0: dwmmc@ff0d0000 {
244 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
245 reg = <0x0 0xff0d0000 0x0 0x4000>;
246 clock-freq-min-max = <400000 150000000>;
247 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
248 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
249 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
250 fifo-depth = <0x100>;
251 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
252 status = "disabled";
253 };
254
255 emmc: dwmmc@ff0f0000 {
256 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
257 reg = <0x0 0xff0f0000 0x0 0x4000>;
258 clock-freq-min-max = <400000 150000000>;
259 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
260 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
261 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
262 fifo-depth = <0x100>;
263 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
264 status = "disabled";
265 };
266
267 saradc: saradc@ff100000 {
268 compatible = "rockchip,saradc";
269 reg = <0x0 0xff100000 0x0 0x100>;
270 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
271 #io-channel-cells = <1>;
272 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
273 clock-names = "saradc", "apb_pclk";
274 resets = <&cru SRST_SARADC>;
275 reset-names = "saradc-apb";
276 status = "disabled";
277 };
278
279 spi0: spi@ff110000 {
280 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
281 reg = <0x0 0xff110000 0x0 0x1000>;
282 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
283 clock-names = "spiclk", "apb_pclk";
284 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
285 pinctrl-names = "default";
286 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
287 #address-cells = <1>;
288 #size-cells = <0>;
289 status = "disabled";
290 };
291
292 spi1: spi@ff120000 {
293 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
294 reg = <0x0 0xff120000 0x0 0x1000>;
295 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
296 clock-names = "spiclk", "apb_pclk";
297 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
300 #address-cells = <1>;
301 #size-cells = <0>;
302 status = "disabled";
303 };
304
305 spi2: spi@ff130000 {
306 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
307 reg = <0x0 0xff130000 0x0 0x1000>;
308 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
309 clock-names = "spiclk", "apb_pclk";
310 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
311 pinctrl-names = "default";
312 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
313 #address-cells = <1>;
314 #size-cells = <0>;
315 status = "disabled";
316 };
317
318 i2c2: i2c@ff140000 {
319 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
320 reg = <0x0 0xff140000 0x0 0x1000>;
321 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
322 #address-cells = <1>;
323 #size-cells = <0>;
324 clock-names = "i2c";
325 clocks = <&cru PCLK_I2C2>;
326 pinctrl-names = "default";
327 pinctrl-0 = <&i2c2_xfer>;
328 status = "disabled";
329 };
330
331 i2c3: i2c@ff150000 {
332 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
333 reg = <0x0 0xff150000 0x0 0x1000>;
334 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
335 #address-cells = <1>;
336 #size-cells = <0>;
337 clock-names = "i2c";
338 clocks = <&cru PCLK_I2C3>;
339 pinctrl-names = "default";
340 pinctrl-0 = <&i2c3_xfer>;
341 status = "disabled";
342 };
343
344 i2c4: i2c@ff160000 {
345 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
346 reg = <0x0 0xff160000 0x0 0x1000>;
347 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
348 #address-cells = <1>;
349 #size-cells = <0>;
350 clock-names = "i2c";
351 clocks = <&cru PCLK_I2C4>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&i2c4_xfer>;
354 status = "disabled";
355 };
356
357 i2c5: i2c@ff170000 {
358 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
359 reg = <0x0 0xff170000 0x0 0x1000>;
360 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
361 #address-cells = <1>;
362 #size-cells = <0>;
363 clock-names = "i2c";
364 clocks = <&cru PCLK_I2C5>;
365 pinctrl-names = "default";
366 pinctrl-0 = <&i2c5_xfer>;
367 status = "disabled";
368 };
369
370 uart0: serial@ff180000 {
371 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
372 reg = <0x0 0xff180000 0x0 0x100>;
373 clock-frequency = <24000000>;
374 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
375 clock-names = "baudclk", "apb_pclk";
376 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
377 reg-shift = <2>;
378 reg-io-width = <4>;
379 status = "disabled";
380 };
381
382 uart1: serial@ff190000 {
383 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
384 reg = <0x0 0xff190000 0x0 0x100>;
385 clock-frequency = <24000000>;
386 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
387 clock-names = "baudclk", "apb_pclk";
388 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
389 reg-shift = <2>;
390 reg-io-width = <4>;
391 status = "disabled";
392 };
393
394 uart3: serial@ff1b0000 {
395 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
396 reg = <0x0 0xff1b0000 0x0 0x100>;
397 clock-frequency = <24000000>;
398 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
399 clock-names = "baudclk", "apb_pclk";
400 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
401 reg-shift = <2>;
402 reg-io-width = <4>;
403 status = "disabled";
404 };
405
406 uart4: serial@ff1c0000 {
407 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
408 reg = <0x0 0xff1c0000 0x0 0x100>;
409 clock-frequency = <24000000>;
410 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
411 clock-names = "baudclk", "apb_pclk";
412 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
413 reg-shift = <2>;
414 reg-io-width = <4>;
415 status = "disabled";
416 };
417
418 thermal-zones {
419 cpu {
420 polling-delay-passive = <100>; /* milliseconds */
421 polling-delay = <5000>; /* milliseconds */
422
423 thermal-sensors = <&tsadc 0>;
424
425 trips {
426 cpu_alert0: cpu_alert0 {
427 temperature = <75000>; /* millicelsius */
428 hysteresis = <2000>; /* millicelsius */
429 type = "passive";
430 };
431 cpu_alert1: cpu_alert1 {
432 temperature = <80000>; /* millicelsius */
433 hysteresis = <2000>; /* millicelsius */
434 type = "passive";
435 };
436 cpu_crit: cpu_crit {
437 temperature = <95000>; /* millicelsius */
438 hysteresis = <2000>; /* millicelsius */
439 type = "critical";
440 };
441 };
442
443 cooling-maps {
444 map0 {
445 trip = <&cpu_alert0>;
446 cooling-device =
447 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
448 };
449 map1 {
450 trip = <&cpu_alert1>;
451 cooling-device =
452 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
453 };
454 };
455 };
456
457 gpu {
458 polling-delay-passive = <100>; /* milliseconds */
459 polling-delay = <5000>; /* milliseconds */
460
461 thermal-sensors = <&tsadc 1>;
462
463 trips {
464 gpu_alert0: gpu_alert0 {
465 temperature = <80000>; /* millicelsius */
466 hysteresis = <2000>; /* millicelsius */
467 type = "passive";
468 };
469 gpu_crit: gpu_crit {
470 temperature = <115000>; /* millicelsius */
471 hysteresis = <2000>; /* millicelsius */
472 type = "critical";
473 };
474 };
475
476 cooling-maps {
477 map0 {
478 trip = <&gpu_alert0>;
479 cooling-device =
480 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
481 };
482 };
483 };
484 };
485
486 tsadc: tsadc@ff280000 {
487 compatible = "rockchip,rk3368-tsadc";
488 reg = <0x0 0xff280000 0x0 0x100>;
489 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
491 clock-names = "tsadc", "apb_pclk";
492 resets = <&cru SRST_TSADC>;
493 reset-names = "tsadc-apb";
494 pinctrl-names = "init", "default", "sleep";
495 pinctrl-0 = <&otp_gpio>;
496 pinctrl-1 = <&otp_out>;
497 pinctrl-2 = <&otp_gpio>;
498 #thermal-sensor-cells = <1>;
499 rockchip,hw-tshut-temp = <95000>;
500 status = "disabled";
501 };
502
503 gmac: ethernet@ff290000 {
504 compatible = "rockchip,rk3368-gmac";
505 reg = <0x0 0xff290000 0x0 0x10000>;
506 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
507 interrupt-names = "macirq";
508 rockchip,grf = <&grf>;
509 clocks = <&cru SCLK_MAC>,
510 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
511 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
512 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
513 clock-names = "stmmaceth",
514 "mac_clk_rx", "mac_clk_tx",
515 "clk_mac_ref", "clk_mac_refout",
516 "aclk_mac", "pclk_mac";
517 status = "disabled";
518 };
519
520 usb_host0_ehci: usb@ff500000 {
521 compatible = "generic-ehci";
522 reg = <0x0 0xff500000 0x0 0x100>;
523 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&cru HCLK_HOST0>;
525 clock-names = "usbhost";
526 status = "disabled";
527 };
528
529 usb_otg: usb@ff580000 {
530 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
531 "snps,dwc2";
532 reg = <0x0 0xff580000 0x0 0x40000>;
533 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&cru HCLK_OTG0>;
535 clock-names = "otg";
536 dr_mode = "otg";
537 g-np-tx-fifo-size = <16>;
538 g-rx-fifo-size = <275>;
539 g-tx-fifo-size = <256 128 128 64 64 32>;
540 g-use-dma;
541 status = "disabled";
542 };
543
544 i2c0: i2c@ff650000 {
545 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
546 reg = <0x0 0xff650000 0x0 0x1000>;
547 clocks = <&cru PCLK_I2C0>;
548 clock-names = "i2c";
549 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
550 pinctrl-names = "default";
551 pinctrl-0 = <&i2c0_xfer>;
552 #address-cells = <1>;
553 #size-cells = <0>;
554 status = "disabled";
555 };
556
557 i2c1: i2c@ff660000 {
558 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
559 reg = <0x0 0xff660000 0x0 0x1000>;
560 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
561 #address-cells = <1>;
562 #size-cells = <0>;
563 clock-names = "i2c";
564 clocks = <&cru PCLK_I2C1>;
565 pinctrl-names = "default";
566 pinctrl-0 = <&i2c1_xfer>;
567 status = "disabled";
568 };
569
570 pwm0: pwm@ff680000 {
571 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
572 reg = <0x0 0xff680000 0x0 0x10>;
573 #pwm-cells = <3>;
574 pinctrl-names = "default";
575 pinctrl-0 = <&pwm0_pin>;
576 clocks = <&cru PCLK_PWM1>;
577 clock-names = "pwm";
578 status = "disabled";
579 };
580
581 pwm1: pwm@ff680010 {
582 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
583 reg = <0x0 0xff680010 0x0 0x10>;
584 #pwm-cells = <3>;
585 pinctrl-names = "default";
586 pinctrl-0 = <&pwm1_pin>;
587 clocks = <&cru PCLK_PWM1>;
588 clock-names = "pwm";
589 status = "disabled";
590 };
591
592 pwm2: pwm@ff680020 {
593 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
594 reg = <0x0 0xff680020 0x0 0x10>;
595 #pwm-cells = <3>;
596 clocks = <&cru PCLK_PWM1>;
597 clock-names = "pwm";
598 status = "disabled";
599 };
600
601 pwm3: pwm@ff680030 {
602 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
603 reg = <0x0 0xff680030 0x0 0x10>;
604 #pwm-cells = <3>;
605 pinctrl-names = "default";
606 pinctrl-0 = <&pwm3_pin>;
607 clocks = <&cru PCLK_PWM1>;
608 clock-names = "pwm";
609 status = "disabled";
610 };
611
612 uart2: serial@ff690000 {
613 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
614 reg = <0x0 0xff690000 0x0 0x100>;
615 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
616 clock-names = "baudclk", "apb_pclk";
617 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
618 pinctrl-names = "default";
619 pinctrl-0 = <&uart2_xfer>;
620 reg-shift = <2>;
621 reg-io-width = <4>;
622 status = "disabled";
623 };
624
625 mbox: mbox@ff6b0000 {
626 compatible = "rockchip,rk3368-mailbox";
627 reg = <0x0 0xff6b0000 0x0 0x1000>;
628 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
631 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&cru PCLK_MAILBOX>;
633 clock-names = "pclk_mailbox";
634 #mbox-cells = <1>;
635 };
636
637 pmugrf: syscon@ff738000 {
638 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
639 reg = <0x0 0xff738000 0x0 0x1000>;
640
641 pmu_io_domains: io-domains {
642 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
643 status = "disabled";
644 };
645
646 reboot-mode {
647 compatible = "syscon-reboot-mode";
648 offset = <0x200>;
649 mode-normal = <BOOT_NORMAL>;
650 mode-recovery = <BOOT_RECOVERY>;
651 mode-bootloader = <BOOT_FASTBOOT>;
652 mode-loader = <BOOT_BL_DOWNLOAD>;
653 };
654 };
655
656 cru: clock-controller@ff760000 {
657 compatible = "rockchip,rk3368-cru";
658 reg = <0x0 0xff760000 0x0 0x1000>;
659 rockchip,grf = <&grf>;
660 #clock-cells = <1>;
661 #reset-cells = <1>;
662 };
663
664 grf: syscon@ff770000 {
665 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
666 reg = <0x0 0xff770000 0x0 0x1000>;
667
668 io_domains: io-domains {
669 compatible = "rockchip,rk3368-io-voltage-domain";
670 status = "disabled";
671 };
672 };
673
674 wdt: watchdog@ff800000 {
675 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
676 reg = <0x0 0xff800000 0x0 0x100>;
677 clocks = <&cru PCLK_WDT>;
678 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
679 status = "disabled";
680 };
681
682 timer@ff810000 {
683 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
684 reg = <0x0 0xff810000 0x0 0x20>;
685 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
686 };
687
688 gic: interrupt-controller@ffb71000 {
689 compatible = "arm,gic-400";
690 interrupt-controller;
691 #interrupt-cells = <3>;
692 #address-cells = <0>;
693
694 reg = <0x0 0xffb71000 0x0 0x1000>,
695 <0x0 0xffb72000 0x0 0x2000>,
696 <0x0 0xffb74000 0x0 0x2000>,
697 <0x0 0xffb76000 0x0 0x2000>;
698 interrupts = <GIC_PPI 9
699 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
700 };
701
702 pinctrl: pinctrl {
703 compatible = "rockchip,rk3368-pinctrl";
704 rockchip,grf = <&grf>;
705 rockchip,pmu = <&pmugrf>;
706 #address-cells = <0x2>;
707 #size-cells = <0x2>;
708 ranges;
709
710 gpio0: gpio0@ff750000 {
711 compatible = "rockchip,gpio-bank";
712 reg = <0x0 0xff750000 0x0 0x100>;
713 clocks = <&cru PCLK_GPIO0>;
714 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
715
716 gpio-controller;
717 #gpio-cells = <0x2>;
718
719 interrupt-controller;
720 #interrupt-cells = <0x2>;
721 };
722
723 gpio1: gpio1@ff780000 {
724 compatible = "rockchip,gpio-bank";
725 reg = <0x0 0xff780000 0x0 0x100>;
726 clocks = <&cru PCLK_GPIO1>;
727 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
728
729 gpio-controller;
730 #gpio-cells = <0x2>;
731
732 interrupt-controller;
733 #interrupt-cells = <0x2>;
734 };
735
736 gpio2: gpio2@ff790000 {
737 compatible = "rockchip,gpio-bank";
738 reg = <0x0 0xff790000 0x0 0x100>;
739 clocks = <&cru PCLK_GPIO2>;
740 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
741
742 gpio-controller;
743 #gpio-cells = <0x2>;
744
745 interrupt-controller;
746 #interrupt-cells = <0x2>;
747 };
748
749 gpio3: gpio3@ff7a0000 {
750 compatible = "rockchip,gpio-bank";
751 reg = <0x0 0xff7a0000 0x0 0x100>;
752 clocks = <&cru PCLK_GPIO3>;
753 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
754
755 gpio-controller;
756 #gpio-cells = <0x2>;
757
758 interrupt-controller;
759 #interrupt-cells = <0x2>;
760 };
761
762 pcfg_pull_up: pcfg-pull-up {
763 bias-pull-up;
764 };
765
766 pcfg_pull_down: pcfg-pull-down {
767 bias-pull-down;
768 };
769
770 pcfg_pull_none: pcfg-pull-none {
771 bias-disable;
772 };
773
774 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
775 bias-disable;
776 drive-strength = <12>;
777 };
778
779 emmc {
780 emmc_clk: emmc-clk {
781 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
782 };
783
784 emmc_cmd: emmc-cmd {
785 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
786 };
787
788 emmc_pwr: emmc-pwr {
789 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
790 };
791
792 emmc_bus1: emmc-bus1 {
793 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
794 };
795
796 emmc_bus4: emmc-bus4 {
797 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
798 <1 19 RK_FUNC_2 &pcfg_pull_up>,
799 <1 20 RK_FUNC_2 &pcfg_pull_up>,
800 <1 21 RK_FUNC_2 &pcfg_pull_up>;
801 };
802
803 emmc_bus8: emmc-bus8 {
804 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
805 <1 19 RK_FUNC_2 &pcfg_pull_up>,
806 <1 20 RK_FUNC_2 &pcfg_pull_up>,
807 <1 21 RK_FUNC_2 &pcfg_pull_up>,
808 <1 22 RK_FUNC_2 &pcfg_pull_up>,
809 <1 23 RK_FUNC_2 &pcfg_pull_up>,
810 <1 24 RK_FUNC_2 &pcfg_pull_up>,
811 <1 25 RK_FUNC_2 &pcfg_pull_up>;
812 };
813 };
814
815 gmac {
816 rgmii_pins: rgmii-pins {
817 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
818 <3 24 RK_FUNC_1 &pcfg_pull_none>,
819 <3 19 RK_FUNC_1 &pcfg_pull_none>,
820 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
821 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
822 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
823 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
824 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
825 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
826 <3 15 RK_FUNC_1 &pcfg_pull_none>,
827 <3 16 RK_FUNC_1 &pcfg_pull_none>,
828 <3 17 RK_FUNC_1 &pcfg_pull_none>,
829 <3 18 RK_FUNC_1 &pcfg_pull_none>,
830 <3 25 RK_FUNC_1 &pcfg_pull_none>,
831 <3 20 RK_FUNC_1 &pcfg_pull_none>;
832 };
833
834 rmii_pins: rmii-pins {
835 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
836 <3 24 RK_FUNC_1 &pcfg_pull_none>,
837 <3 19 RK_FUNC_1 &pcfg_pull_none>,
838 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
839 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
840 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
841 <3 15 RK_FUNC_1 &pcfg_pull_none>,
842 <3 16 RK_FUNC_1 &pcfg_pull_none>,
843 <3 20 RK_FUNC_1 &pcfg_pull_none>,
844 <3 21 RK_FUNC_1 &pcfg_pull_none>;
845 };
846 };
847
848 i2c0 {
849 i2c0_xfer: i2c0-xfer {
850 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
851 <0 7 RK_FUNC_1 &pcfg_pull_none>;
852 };
853 };
854
855 i2c1 {
856 i2c1_xfer: i2c1-xfer {
857 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
858 <2 22 RK_FUNC_1 &pcfg_pull_none>;
859 };
860 };
861
862 i2c2 {
863 i2c2_xfer: i2c2-xfer {
864 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
865 <3 31 RK_FUNC_2 &pcfg_pull_none>;
866 };
867 };
868
869 i2c3 {
870 i2c3_xfer: i2c3-xfer {
871 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
872 <1 17 RK_FUNC_1 &pcfg_pull_none>;
873 };
874 };
875
876 i2c4 {
877 i2c4_xfer: i2c4-xfer {
878 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
879 <3 25 RK_FUNC_2 &pcfg_pull_none>;
880 };
881 };
882
883 i2c5 {
884 i2c5_xfer: i2c5-xfer {
885 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
886 <3 27 RK_FUNC_2 &pcfg_pull_none>;
887 };
888 };
889
890 pwm0 {
891 pwm0_pin: pwm0-pin {
892 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
893 };
894 };
895
896 pwm1 {
897 pwm1_pin: pwm1-pin {
898 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
899 };
900 };
901
902 pwm3 {
903 pwm3_pin: pwm3-pin {
904 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
905 };
906 };
907
908 sdio0 {
909 sdio0_bus1: sdio0-bus1 {
910 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
911 };
912
913 sdio0_bus4: sdio0-bus4 {
914 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
915 <2 29 RK_FUNC_1 &pcfg_pull_up>,
916 <2 30 RK_FUNC_1 &pcfg_pull_up>,
917 <2 31 RK_FUNC_1 &pcfg_pull_up>;
918 };
919
920 sdio0_cmd: sdio0-cmd {
921 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
922 };
923
924 sdio0_clk: sdio0-clk {
925 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
926 };
927
928 sdio0_cd: sdio0-cd {
929 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
930 };
931
932 sdio0_wp: sdio0-wp {
933 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
934 };
935
936 sdio0_pwr: sdio0-pwr {
937 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
938 };
939
940 sdio0_bkpwr: sdio0-bkpwr {
941 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
942 };
943
944 sdio0_int: sdio0-int {
945 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
946 };
947 };
948
949 sdmmc {
950 sdmmc_clk: sdmmc-clk {
951 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
952 };
953
954 sdmmc_cmd: sdmmc-cmd {
955 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
956 };
957
958 sdmmc_cd: sdmmc-cd {
959 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
960 };
961
962 sdmmc_bus1: sdmmc-bus1 {
963 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
964 };
965
966 sdmmc_bus4: sdmmc-bus4 {
967 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
968 <2 6 RK_FUNC_1 &pcfg_pull_up>,
969 <2 7 RK_FUNC_1 &pcfg_pull_up>,
970 <2 8 RK_FUNC_1 &pcfg_pull_up>;
971 };
972 };
973
974 spi0 {
975 spi0_clk: spi0-clk {
976 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
977 };
978 spi0_cs0: spi0-cs0 {
979 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
980 };
981 spi0_cs1: spi0-cs1 {
982 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
983 };
984 spi0_tx: spi0-tx {
985 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
986 };
987 spi0_rx: spi0-rx {
988 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
989 };
990 };
991
992 spi1 {
993 spi1_clk: spi1-clk {
994 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
995 };
996 spi1_cs0: spi1-cs0 {
997 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
998 };
999 spi1_cs1: spi1-cs1 {
1000 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1001 };
1002 spi1_rx: spi1-rx {
1003 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1004 };
1005 spi1_tx: spi1-tx {
1006 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1007 };
1008 };
1009
1010 spi2 {
1011 spi2_clk: spi2-clk {
1012 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1013 };
1014 spi2_cs0: spi2-cs0 {
1015 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1016 };
1017 spi2_rx: spi2-rx {
1018 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1019 };
1020 spi2_tx: spi2-tx {
1021 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1022 };
1023 };
1024
1025 tsadc {
1026 otp_gpio: otp-gpio {
1027 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
1028 };
1029
1030 otp_out: otp-out {
1031 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
1032 };
1033 };
1034
1035 uart0 {
1036 uart0_xfer: uart0-xfer {
1037 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1038 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1039 };
1040
1041 uart0_cts: uart0-cts {
1042 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1043 };
1044
1045 uart0_rts: uart0-rts {
1046 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1047 };
1048 };
1049
1050 uart1 {
1051 uart1_xfer: uart1-xfer {
1052 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1053 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1054 };
1055
1056 uart1_cts: uart1-cts {
1057 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1058 };
1059
1060 uart1_rts: uart1-rts {
1061 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1062 };
1063 };
1064
1065 uart2 {
1066 uart2_xfer: uart2-xfer {
1067 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1068 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1069 };
1070 /* no rts / cts for uart2 */
1071 };
1072
1073 uart3 {
1074 uart3_xfer: uart3-xfer {
1075 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1076 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1077 };
1078
1079 uart3_cts: uart3-cts {
1080 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1081 };
1082
1083 uart3_rts: uart3-rts {
1084 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1085 };
1086 };
1087
1088 uart4 {
1089 uart4_xfer: uart4-xfer {
1090 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1091 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1092 };
1093
1094 uart4_cts: uart4-cts {
1095 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1096 };
1097
1098 uart4_rts: uart4-rts {
1099 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1100 };
1101 };
1102 };
1103 };
Linux kernel - Deliverables
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