2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/thermal/thermal.h>
51 compatible = "rockchip,rk3399";
53 interrupt-parent = <&gic>;
106 compatible = "arm,cortex-a53", "arm,armv8";
108 enable-method = "psci";
109 #cooling-cells = <2>; /* min followed by max */
110 clocks = <&cru ARMCLKL>;
115 compatible = "arm,cortex-a53", "arm,armv8";
117 enable-method = "psci";
118 clocks = <&cru ARMCLKL>;
123 compatible = "arm,cortex-a53", "arm,armv8";
125 enable-method = "psci";
126 clocks = <&cru ARMCLKL>;
131 compatible = "arm,cortex-a53", "arm,armv8";
133 enable-method = "psci";
134 clocks = <&cru ARMCLKL>;
139 compatible = "arm,cortex-a72", "arm,armv8";
141 enable-method = "psci";
142 #cooling-cells = <2>; /* min followed by max */
143 clocks = <&cru ARMCLKB>;
148 compatible = "arm,cortex-a72", "arm,armv8";
150 enable-method = "psci";
151 clocks = <&cru ARMCLKB>;
156 compatible = "arm,psci-1.0";
161 compatible = "arm,armv8-timer";
162 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
163 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
164 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
165 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
169 compatible = "fixed-clock";
170 clock-frequency = <24000000>;
171 clock-output-names = "xin24m";
176 compatible = "simple-bus";
177 #address-cells = <2>;
181 dmac_bus: dma-controller@ff6d0000 {
182 compatible = "arm,pl330", "arm,primecell";
183 reg = <0x0 0xff6d0000 0x0 0x4000>;
184 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&cru ACLK_DMAC0_PERILP>;
188 clock-names = "apb_pclk";
191 dmac_peri: dma-controller@ff6e0000 {
192 compatible = "arm,pl330", "arm,primecell";
193 reg = <0x0 0xff6e0000 0x0 0x4000>;
194 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&cru ACLK_DMAC1_PERILP>;
198 clock-names = "apb_pclk";
202 sdio0: dwmmc@fe310000 {
203 compatible = "rockchip,rk3399-dw-mshc",
204 "rockchip,rk3288-dw-mshc";
205 reg = <0x0 0xfe310000 0x0 0x4000>;
206 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
207 clock-freq-min-max = <400000 150000000>;
208 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
209 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
210 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
211 fifo-depth = <0x100>;
215 sdmmc: dwmmc@fe320000 {
216 compatible = "rockchip,rk3399-dw-mshc",
217 "rockchip,rk3288-dw-mshc";
218 reg = <0x0 0xfe320000 0x0 0x4000>;
219 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
220 clock-freq-min-max = <400000 150000000>;
221 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
222 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
223 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
224 fifo-depth = <0x100>;
228 sdhci: sdhci@fe330000 {
229 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
230 reg = <0x0 0xfe330000 0x0 0x10000>;
231 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
232 arasan,soc-ctl-syscon = <&grf>;
233 assigned-clocks = <&cru SCLK_EMMC>;
234 assigned-clock-rates = <200000000>;
235 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
236 clock-names = "clk_xin", "clk_ahb";
237 clock-output-names = "emmc_cardclock";
240 phy-names = "phy_arasan";
244 usb_host0_ehci: usb@fe380000 {
245 compatible = "generic-ehci";
246 reg = <0x0 0xfe380000 0x0 0x20000>;
247 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
249 clock-names = "hclk_host0", "hclk_host0_arb";
253 usb_host0_ohci: usb@fe3a0000 {
254 compatible = "generic-ohci";
255 reg = <0x0 0xfe3a0000 0x0 0x20000>;
256 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
258 clock-names = "hclk_host0", "hclk_host0_arb";
262 usb_host1_ehci: usb@fe3c0000 {
263 compatible = "generic-ehci";
264 reg = <0x0 0xfe3c0000 0x0 0x20000>;
265 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
267 clock-names = "hclk_host1", "hclk_host1_arb";
271 usb_host1_ohci: usb@fe3e0000 {
272 compatible = "generic-ohci";
273 reg = <0x0 0xfe3e0000 0x0 0x20000>;
274 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
276 clock-names = "hclk_host1", "hclk_host1_arb";
280 gic: interrupt-controller@fee00000 {
281 compatible = "arm,gic-v3";
282 #interrupt-cells = <3>;
283 #address-cells = <2>;
286 interrupt-controller;
288 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
289 <0x0 0xfef00000 0 0xc0000>, /* GICR */
290 <0x0 0xfff00000 0 0x10000>, /* GICC */
291 <0x0 0xfff10000 0 0x10000>, /* GICH */
292 <0x0 0xfff20000 0 0x10000>; /* GICV */
293 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
294 its: interrupt-controller@fee20000 {
295 compatible = "arm,gic-v3-its";
297 reg = <0x0 0xfee20000 0x0 0x20000>;
302 compatible = "rockchip,rk3399-i2c";
303 reg = <0x0 0xff110000 0x0 0x1000>;
304 assigned-clocks = <&cru SCLK_I2C1>;
305 assigned-clock-rates = <200000000>;
306 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
307 clock-names = "i2c", "pclk";
308 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&i2c1_xfer>;
311 #address-cells = <1>;
317 compatible = "rockchip,rk3399-i2c";
318 reg = <0x0 0xff120000 0x0 0x1000>;
319 assigned-clocks = <&cru SCLK_I2C2>;
320 assigned-clock-rates = <200000000>;
321 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
322 clock-names = "i2c", "pclk";
323 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
324 pinctrl-names = "default";
325 pinctrl-0 = <&i2c2_xfer>;
326 #address-cells = <1>;
332 compatible = "rockchip,rk3399-i2c";
333 reg = <0x0 0xff130000 0x0 0x1000>;
334 assigned-clocks = <&cru SCLK_I2C3>;
335 assigned-clock-rates = <200000000>;
336 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
337 clock-names = "i2c", "pclk";
338 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
339 pinctrl-names = "default";
340 pinctrl-0 = <&i2c3_xfer>;
341 #address-cells = <1>;
347 compatible = "rockchip,rk3399-i2c";
348 reg = <0x0 0xff140000 0x0 0x1000>;
349 assigned-clocks = <&cru SCLK_I2C5>;
350 assigned-clock-rates = <200000000>;
351 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
352 clock-names = "i2c", "pclk";
353 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
354 pinctrl-names = "default";
355 pinctrl-0 = <&i2c5_xfer>;
356 #address-cells = <1>;
362 compatible = "rockchip,rk3399-i2c";
363 reg = <0x0 0xff150000 0x0 0x1000>;
364 assigned-clocks = <&cru SCLK_I2C6>;
365 assigned-clock-rates = <200000000>;
366 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
367 clock-names = "i2c", "pclk";
368 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
369 pinctrl-names = "default";
370 pinctrl-0 = <&i2c6_xfer>;
371 #address-cells = <1>;
377 compatible = "rockchip,rk3399-i2c";
378 reg = <0x0 0xff160000 0x0 0x1000>;
379 assigned-clocks = <&cru SCLK_I2C7>;
380 assigned-clock-rates = <200000000>;
381 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
382 clock-names = "i2c", "pclk";
383 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
384 pinctrl-names = "default";
385 pinctrl-0 = <&i2c7_xfer>;
386 #address-cells = <1>;
391 uart0: serial@ff180000 {
392 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
393 reg = <0x0 0xff180000 0x0 0x100>;
394 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
395 clock-names = "baudclk", "apb_pclk";
396 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&uart0_xfer>;
404 uart1: serial@ff190000 {
405 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
406 reg = <0x0 0xff190000 0x0 0x100>;
407 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
408 clock-names = "baudclk", "apb_pclk";
409 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
412 pinctrl-names = "default";
413 pinctrl-0 = <&uart1_xfer>;
417 uart2: serial@ff1a0000 {
418 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
419 reg = <0x0 0xff1a0000 0x0 0x100>;
420 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
421 clock-names = "baudclk", "apb_pclk";
422 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
425 pinctrl-names = "default";
426 pinctrl-0 = <&uart2c_xfer>;
430 uart3: serial@ff1b0000 {
431 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
432 reg = <0x0 0xff1b0000 0x0 0x100>;
433 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
434 clock-names = "baudclk", "apb_pclk";
435 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
438 pinctrl-names = "default";
439 pinctrl-0 = <&uart3_xfer>;
444 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
445 reg = <0x0 0xff1c0000 0x0 0x1000>;
446 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
447 clock-names = "spiclk", "apb_pclk";
448 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
449 pinctrl-names = "default";
450 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
451 #address-cells = <1>;
457 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
458 reg = <0x0 0xff1d0000 0x0 0x1000>;
459 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
460 clock-names = "spiclk", "apb_pclk";
461 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
462 pinctrl-names = "default";
463 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
464 #address-cells = <1>;
470 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
471 reg = <0x0 0xff1e0000 0x0 0x1000>;
472 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
473 clock-names = "spiclk", "apb_pclk";
474 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
475 pinctrl-names = "default";
476 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
477 #address-cells = <1>;
483 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
484 reg = <0x0 0xff1f0000 0x0 0x1000>;
485 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
486 clock-names = "spiclk", "apb_pclk";
487 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
488 pinctrl-names = "default";
489 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
490 #address-cells = <1>;
496 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
497 reg = <0x0 0xff200000 0x0 0x1000>;
498 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
499 clock-names = "spiclk", "apb_pclk";
500 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
501 pinctrl-names = "default";
502 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
503 #address-cells = <1>;
510 polling-delay-passive = <100>;
511 polling-delay = <1000>;
513 thermal-sensors = <&tsadc 0>;
516 cpu_alert0: cpu_alert0 {
517 temperature = <70000>;
521 cpu_alert1: cpu_alert1 {
522 temperature = <75000>;
527 temperature = <95000>;
535 trip = <&cpu_alert0>;
537 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
540 trip = <&cpu_alert1>;
542 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
543 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
549 polling-delay-passive = <100>;
550 polling-delay = <1000>;
552 thermal-sensors = <&tsadc 1>;
555 gpu_alert0: gpu_alert0 {
556 temperature = <75000>;
561 temperature = <95000>;
569 trip = <&gpu_alert0>;
571 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
577 tsadc: tsadc@ff260000 {
578 compatible = "rockchip,rk3399-tsadc";
579 reg = <0x0 0xff260000 0x0 0x100>;
580 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
581 assigned-clocks = <&cru SCLK_TSADC>;
582 assigned-clock-rates = <750000>;
583 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
584 clock-names = "tsadc", "apb_pclk";
585 resets = <&cru SRST_TSADC>;
586 reset-names = "tsadc-apb";
587 rockchip,grf = <&grf>;
588 rockchip,hw-tshut-temp = <95000>;
589 pinctrl-names = "init", "default", "sleep";
590 pinctrl-0 = <&otp_gpio>;
591 pinctrl-1 = <&otp_out>;
592 pinctrl-2 = <&otp_gpio>;
593 #thermal-sensor-cells = <1>;
597 pmugrf: syscon@ff320000 {
598 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
599 reg = <0x0 0xff320000 0x0 0x1000>;
600 #address-cells = <1>;
603 pmu_io_domains: io-domains {
604 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
610 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
611 reg = <0x0 0xff350000 0x0 0x1000>;
612 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
613 clock-names = "spiclk", "apb_pclk";
614 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
615 pinctrl-names = "default";
616 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
617 #address-cells = <1>;
622 uart4: serial@ff370000 {
623 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
624 reg = <0x0 0xff370000 0x0 0x100>;
625 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
626 clock-names = "baudclk", "apb_pclk";
627 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
630 pinctrl-names = "default";
631 pinctrl-0 = <&uart4_xfer>;
636 compatible = "rockchip,rk3399-i2c";
637 reg = <0x0 0xff3c0000 0x0 0x1000>;
638 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
639 assigned-clock-rates = <200000000>;
640 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
641 clock-names = "i2c", "pclk";
642 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
643 pinctrl-names = "default";
644 pinctrl-0 = <&i2c0_xfer>;
645 #address-cells = <1>;
651 compatible = "rockchip,rk3399-i2c";
652 reg = <0x0 0xff3d0000 0x0 0x1000>;
653 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
654 assigned-clock-rates = <200000000>;
655 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
656 clock-names = "i2c", "pclk";
657 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
658 pinctrl-names = "default";
659 pinctrl-0 = <&i2c4_xfer>;
660 #address-cells = <1>;
666 compatible = "rockchip,rk3399-i2c";
667 reg = <0x0 0xff3e0000 0x0 0x1000>;
668 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
669 assigned-clock-rates = <200000000>;
670 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
671 clock-names = "i2c", "pclk";
672 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
673 pinctrl-names = "default";
674 pinctrl-0 = <&i2c8_xfer>;
675 #address-cells = <1>;
681 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
682 reg = <0x0 0xff420000 0x0 0x10>;
684 pinctrl-names = "default";
685 pinctrl-0 = <&pwm0_pin>;
686 clocks = <&pmucru PCLK_RKPWM_PMU>;
692 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
693 reg = <0x0 0xff420010 0x0 0x10>;
695 pinctrl-names = "default";
696 pinctrl-0 = <&pwm1_pin>;
697 clocks = <&pmucru PCLK_RKPWM_PMU>;
703 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
704 reg = <0x0 0xff420020 0x0 0x10>;
706 pinctrl-names = "default";
707 pinctrl-0 = <&pwm2_pin>;
708 clocks = <&pmucru PCLK_RKPWM_PMU>;
714 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
715 reg = <0x0 0xff420030 0x0 0x10>;
717 pinctrl-names = "default";
718 pinctrl-0 = <&pwm3a_pin>;
719 clocks = <&pmucru PCLK_RKPWM_PMU>;
724 pmucru: pmu-clock-controller@ff750000 {
725 compatible = "rockchip,rk3399-pmucru";
726 reg = <0x0 0xff750000 0x0 0x1000>;
729 assigned-clocks = <&pmucru PLL_PPLL>;
730 assigned-clock-rates = <676000000>;
733 cru: clock-controller@ff760000 {
734 compatible = "rockchip,rk3399-cru";
735 reg = <0x0 0xff760000 0x0 0x1000>;
739 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
741 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
743 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
745 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
746 assigned-clock-rates =
747 <594000000>, <800000000>,
749 <150000000>, <75000000>,
751 <100000000>, <100000000>,
753 <100000000>, <50000000>;
756 grf: syscon@ff770000 {
757 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
758 reg = <0x0 0xff770000 0x0 0x10000>;
759 #address-cells = <1>;
762 io_domains: io-domains {
763 compatible = "rockchip,rk3399-io-voltage-domain";
768 compatible = "rockchip,rk3399-emmc-phy";
771 clock-names = "emmcclk";
778 compatible = "snps,dw-wdt";
779 reg = <0x0 0xff840000 0x0 0x100>;
780 clocks = <&cru PCLK_WDT>;
781 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
784 rktimer: rktimer@ff850000 {
785 compatible = "rockchip,rk3399-timer";
786 reg = <0x0 0xff850000 0x0 0x1000>;
787 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
789 clock-names = "pclk", "timer";
792 spdif: spdif@ff870000 {
793 compatible = "rockchip,rk3399-spdif";
794 reg = <0x0 0xff870000 0x0 0x1000>;
795 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
796 dmas = <&dmac_bus 7>;
798 clock-names = "mclk", "hclk";
799 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
800 pinctrl-names = "default";
801 pinctrl-0 = <&spdif_bus>;
806 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
807 reg = <0x0 0xff880000 0x0 0x1000>;
808 rockchip,grf = <&grf>;
809 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
810 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
811 dma-names = "tx", "rx";
812 clock-names = "i2s_clk", "i2s_hclk";
813 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
814 pinctrl-names = "default";
815 pinctrl-0 = <&i2s0_8ch_bus>;
820 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
821 reg = <0x0 0xff890000 0x0 0x1000>;
822 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
823 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
824 dma-names = "tx", "rx";
825 clock-names = "i2s_clk", "i2s_hclk";
826 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
827 pinctrl-names = "default";
828 pinctrl-0 = <&i2s1_2ch_bus>;
833 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
834 reg = <0x0 0xff8a0000 0x0 0x1000>;
835 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
836 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
837 dma-names = "tx", "rx";
838 clock-names = "i2s_clk", "i2s_hclk";
839 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
844 compatible = "rockchip,rk3399-pinctrl";
845 rockchip,grf = <&grf>;
846 rockchip,pmu = <&pmugrf>;
847 #address-cells = <2>;
851 gpio0: gpio0@ff720000 {
852 compatible = "rockchip,gpio-bank";
853 reg = <0x0 0xff720000 0x0 0x100>;
854 clocks = <&pmucru PCLK_GPIO0_PMU>;
855 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
860 interrupt-controller;
861 #interrupt-cells = <0x2>;
864 gpio1: gpio1@ff730000 {
865 compatible = "rockchip,gpio-bank";
866 reg = <0x0 0xff730000 0x0 0x100>;
867 clocks = <&pmucru PCLK_GPIO1_PMU>;
868 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
873 interrupt-controller;
874 #interrupt-cells = <0x2>;
877 gpio2: gpio2@ff780000 {
878 compatible = "rockchip,gpio-bank";
879 reg = <0x0 0xff780000 0x0 0x100>;
880 clocks = <&cru PCLK_GPIO2>;
881 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
886 interrupt-controller;
887 #interrupt-cells = <0x2>;
890 gpio3: gpio3@ff788000 {
891 compatible = "rockchip,gpio-bank";
892 reg = <0x0 0xff788000 0x0 0x100>;
893 clocks = <&cru PCLK_GPIO3>;
894 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
899 interrupt-controller;
900 #interrupt-cells = <0x2>;
903 gpio4: gpio4@ff790000 {
904 compatible = "rockchip,gpio-bank";
905 reg = <0x0 0xff790000 0x0 0x100>;
906 clocks = <&cru PCLK_GPIO4>;
907 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
912 interrupt-controller;
913 #interrupt-cells = <0x2>;
916 pcfg_pull_up: pcfg-pull-up {
920 pcfg_pull_down: pcfg-pull-down {
924 pcfg_pull_none: pcfg-pull-none {
928 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
930 drive-strength = <12>;
933 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
935 drive-strength = <8>;
938 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
940 drive-strength = <4>;
943 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
945 drive-strength = <2>;
948 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
950 drive-strength = <12>;
953 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
955 drive-strength = <13>;
959 i2c0_xfer: i2c0-xfer {
961 <1 15 RK_FUNC_2 &pcfg_pull_none>,
962 <1 16 RK_FUNC_2 &pcfg_pull_none>;
967 i2c1_xfer: i2c1-xfer {
969 <4 2 RK_FUNC_1 &pcfg_pull_none>,
970 <4 1 RK_FUNC_1 &pcfg_pull_none>;
975 i2c2_xfer: i2c2-xfer {
977 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
978 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
983 i2c3_xfer: i2c3-xfer {
985 <4 17 RK_FUNC_1 &pcfg_pull_none>,
986 <4 16 RK_FUNC_1 &pcfg_pull_none>;
991 i2c4_xfer: i2c4-xfer {
993 <1 12 RK_FUNC_1 &pcfg_pull_none>,
994 <1 11 RK_FUNC_1 &pcfg_pull_none>;
999 i2c5_xfer: i2c5-xfer {
1001 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1002 <3 10 RK_FUNC_2 &pcfg_pull_none>;
1007 i2c6_xfer: i2c6-xfer {
1009 <2 10 RK_FUNC_2 &pcfg_pull_none>,
1010 <2 9 RK_FUNC_2 &pcfg_pull_none>;
1015 i2c7_xfer: i2c7-xfer {
1017 <2 8 RK_FUNC_2 &pcfg_pull_none>,
1018 <2 7 RK_FUNC_2 &pcfg_pull_none>;
1023 i2c8_xfer: i2c8-xfer {
1025 <1 21 RK_FUNC_1 &pcfg_pull_none>,
1026 <1 20 RK_FUNC_1 &pcfg_pull_none>;
1031 i2s0_8ch_bus: i2s0-8ch-bus {
1033 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1034 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1035 <3 26 RK_FUNC_1 &pcfg_pull_none>,
1036 <3 27 RK_FUNC_1 &pcfg_pull_none>,
1037 <3 28 RK_FUNC_1 &pcfg_pull_none>,
1038 <3 29 RK_FUNC_1 &pcfg_pull_none>,
1039 <3 30 RK_FUNC_1 &pcfg_pull_none>,
1040 <3 31 RK_FUNC_1 &pcfg_pull_none>,
1041 <4 0 RK_FUNC_1 &pcfg_pull_none>;
1046 i2s1_2ch_bus: i2s1-2ch-bus {
1048 <4 3 RK_FUNC_1 &pcfg_pull_none>,
1049 <4 4 RK_FUNC_1 &pcfg_pull_none>,
1050 <4 5 RK_FUNC_1 &pcfg_pull_none>,
1051 <4 6 RK_FUNC_1 &pcfg_pull_none>,
1052 <4 7 RK_FUNC_1 &pcfg_pull_none>;
1057 ap_pwroff: ap-pwroff {
1058 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
1061 ddrio_pwroff: ddrio-pwroff {
1062 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1067 spdif_bus: spdif-bus {
1069 <4 21 RK_FUNC_1 &pcfg_pull_none>;
1074 spi0_clk: spi0-clk {
1076 <3 6 RK_FUNC_2 &pcfg_pull_up>;
1078 spi0_cs0: spi0-cs0 {
1080 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1082 spi0_cs1: spi0-cs1 {
1084 <3 8 RK_FUNC_2 &pcfg_pull_up>;
1088 <3 5 RK_FUNC_2 &pcfg_pull_up>;
1092 <3 4 RK_FUNC_2 &pcfg_pull_up>;
1097 spi1_clk: spi1-clk {
1099 <1 9 RK_FUNC_2 &pcfg_pull_up>;
1101 spi1_cs0: spi1-cs0 {
1103 <1 10 RK_FUNC_2 &pcfg_pull_up>;
1107 <1 7 RK_FUNC_2 &pcfg_pull_up>;
1111 <1 8 RK_FUNC_2 &pcfg_pull_up>;
1116 spi2_clk: spi2-clk {
1118 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1120 spi2_cs0: spi2-cs0 {
1122 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1126 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1130 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1135 spi3_clk: spi3-clk {
1137 <1 17 RK_FUNC_1 &pcfg_pull_up>;
1139 spi3_cs0: spi3-cs0 {
1141 <1 18 RK_FUNC_1 &pcfg_pull_up>;
1145 <1 15 RK_FUNC_1 &pcfg_pull_up>;
1149 <1 16 RK_FUNC_1 &pcfg_pull_up>;
1154 spi4_clk: spi4-clk {
1156 <3 2 RK_FUNC_2 &pcfg_pull_up>;
1158 spi4_cs0: spi4-cs0 {
1160 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1164 <3 0 RK_FUNC_2 &pcfg_pull_up>;
1168 <3 1 RK_FUNC_2 &pcfg_pull_up>;
1173 spi5_clk: spi5-clk {
1175 <2 22 RK_FUNC_2 &pcfg_pull_up>;
1177 spi5_cs0: spi5-cs0 {
1179 <2 23 RK_FUNC_2 &pcfg_pull_up>;
1183 <2 20 RK_FUNC_2 &pcfg_pull_up>;
1187 <2 21 RK_FUNC_2 &pcfg_pull_up>;
1192 otp_gpio: otp-gpio {
1193 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1197 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1202 uart0_xfer: uart0-xfer {
1204 <2 16 RK_FUNC_1 &pcfg_pull_up>,
1205 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1208 uart0_cts: uart0-cts {
1210 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1213 uart0_rts: uart0-rts {
1215 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1220 uart1_xfer: uart1-xfer {
1222 <3 12 RK_FUNC_2 &pcfg_pull_up>,
1223 <3 13 RK_FUNC_2 &pcfg_pull_none>;
1228 uart2a_xfer: uart2a-xfer {
1230 <4 8 RK_FUNC_2 &pcfg_pull_up>,
1231 <4 9 RK_FUNC_2 &pcfg_pull_none>;
1236 uart2b_xfer: uart2b-xfer {
1238 <4 16 RK_FUNC_2 &pcfg_pull_up>,
1239 <4 17 RK_FUNC_2 &pcfg_pull_none>;
1244 uart2c_xfer: uart2c-xfer {
1246 <4 19 RK_FUNC_1 &pcfg_pull_up>,
1247 <4 20 RK_FUNC_1 &pcfg_pull_none>;
1252 uart3_xfer: uart3-xfer {
1254 <3 14 RK_FUNC_2 &pcfg_pull_up>,
1255 <3 15 RK_FUNC_2 &pcfg_pull_none>;
1258 uart3_cts: uart3-cts {
1260 <3 18 RK_FUNC_2 &pcfg_pull_none>;
1263 uart3_rts: uart3-rts {
1265 <3 19 RK_FUNC_2 &pcfg_pull_none>;
1270 uart4_xfer: uart4-xfer {
1272 <1 7 RK_FUNC_1 &pcfg_pull_up>,
1273 <1 8 RK_FUNC_1 &pcfg_pull_none>;
1278 uarthdcp_xfer: uarthdcp-xfer {
1280 <4 21 RK_FUNC_2 &pcfg_pull_up>,
1281 <4 22 RK_FUNC_2 &pcfg_pull_none>;
1286 pwm0_pin: pwm0-pin {
1288 <4 18 RK_FUNC_1 &pcfg_pull_none>;
1291 vop0_pwm_pin: vop0-pwm-pin {
1293 <4 18 RK_FUNC_2 &pcfg_pull_none>;
1298 pwm1_pin: pwm1-pin {
1300 <4 22 RK_FUNC_1 &pcfg_pull_none>;
1303 vop1_pwm_pin: vop1-pwm-pin {
1305 <4 18 RK_FUNC_3 &pcfg_pull_none>;
1310 pwm2_pin: pwm2-pin {
1312 <1 19 RK_FUNC_1 &pcfg_pull_none>;
1317 pwm3a_pin: pwm3a-pin {
1319 <0 6 RK_FUNC_1 &pcfg_pull_none>;
1324 pwm3b_pin: pwm3b-pin {
1326 <1 14 RK_FUNC_1 &pcfg_pull_none>;