arch/arm64/include/asm/cacheflush.h

   1 /*
   2  * Based on arch/arm/include/asm/cacheflush.h
   3  *
   4  * Copyright (C) 1999-2002 Russell King.
   5  * Copyright (C) 2012 ARM Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef __ASM_CACHEFLUSH_H
  20 #define __ASM_CACHEFLUSH_H
  21
  22 #include <linux/mm.h>
  23
  24 /*
  25  * This flag is used to indicate that the page pointed to by a pte is clean
  26  * and does not require cleaning before returning it to the user.
  27  */
  28 #define PG_dcache_clean PG_arch_1
  29
  30 /*
  31  *      MM Cache Management
  32  *      ===================
  33  *
  34  *      The arch/arm64/mm/cache.S implements these methods.
  35  *
  36  *      Start addresses are inclusive and end addresses are exclusive; start
  37  *      addresses should be rounded down, end addresses up.
  38  *
  39  *      See Documentation/cachetlb.txt for more information. Please note that
  40  *      the implementation assumes non-aliasing VIPT D-cache and (aliasing)
  41  *      VIPT or ASID-tagged VIVT I-cache.
  42  *
  43  *      flush_cache_mm(mm)
  44  *
  45  *              Clean and invalidate all user space cache entries
  46  *              before a change of page tables.
  47  *
  48  *      flush_icache_range(start, end)
  49  *
  50  *              Ensure coherency between the I-cache and the D-cache in the
  51  *              region described by start, end.
  52  *              - start  - virtual start address
  53  *              - end    - virtual end address
  54  *
  55  *      __flush_cache_user_range(start, end)
  56  *
  57  *              Ensure coherency between the I-cache and the D-cache in the
  58  *              region described by start, end.
  59  *              - start  - virtual start address
  60  *              - end    - virtual end address
  61  *
  62  *      __flush_dcache_area(kaddr, size)
  63  *
  64  *              Ensure that the data held in page is written back.
  65  *              - kaddr  - page address
  66  *              - size   - region size
  67  */
  68 extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
  69 extern void flush_icache_range(unsigned long start, unsigned long end);
  70 extern void __flush_dcache_area(void *addr, size_t len);
  71 extern void __clean_dcache_area_poc(void *addr, size_t len);
  72 extern void __clean_dcache_area_pou(void *addr, size_t len);
  73 extern long __flush_cache_user_range(unsigned long start, unsigned long end);
  74
  75 static inline void flush_cache_mm(struct mm_struct *mm)
  76 {
  77 }
  78
  79 static inline void flush_cache_page(struct vm_area_struct *vma,
  80                                     unsigned long user_addr, unsigned long pfn)
  81 {
  82 }
  83
  84 /*
  85  * Cache maintenance functions used by the DMA API. No to be used directly.
  86  */
  87 extern void __dma_map_area(const void *, size_t, int);
  88 extern void __dma_unmap_area(const void *, size_t, int);
  89 extern void __dma_flush_area(const void *, size_t);
  90
  91 /*
  92  * Copy user data from/to a page which is mapped into a different
  93  * processes address space.  Really, we want to allow our "user
  94  * space" model to handle this.
  95  */
  96 extern void copy_to_user_page(struct vm_area_struct *, struct page *,
  97         unsigned long, void *, const void *, unsigned long);
  98 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
  99         do {                                                    \
 100                 memcpy(dst, src, len);                          \
 101         } while (0)
 102
 103 #define flush_cache_dup_mm(mm) flush_cache_mm(mm)
 104
 105 /*
 106  * flush_dcache_page is used when the kernel has written to the page
 107  * cache page at virtual address page->virtual.
 108  *
 109  * If this page isn't mapped (ie, page_mapping == NULL), or it might
 110  * have userspace mappings, then we _must_ always clean + invalidate
 111  * the dcache entries associated with the kernel mapping.
 112  *
 113  * Otherwise we can defer the operation, and clean the cache when we are
 114  * about to change to user space.  This is the same method as used on SPARC64.
 115  * See update_mmu_cache for the user space part.
 116  */
 117 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
 118 extern void flush_dcache_page(struct page *);
 119
 120 static inline void __flush_icache_all(void)
 121 {
 122         asm("ic ialluis");
 123         dsb(ish);
 124 }
 125
 126 #define flush_dcache_mmap_lock(mapping) \
 127         spin_lock_irq(&(mapping)->tree_lock)
 128 #define flush_dcache_mmap_unlock(mapping) \
 129         spin_unlock_irq(&(mapping)->tree_lock)
 130
 131 /*
 132  * We don't appear to need to do anything here.  In fact, if we did, we'd
 133  * duplicate cache flushing elsewhere performed by flush_dcache_page().
 134  */
 135 #define flush_icache_page(vma,page)     do { } while (0)
 136
 137 /*
 138  * Not required on AArch64 (PIPT or VIPT non-aliasing D-cache).
 139  */
 140 static inline void flush_cache_vmap(unsigned long start, unsigned long end)
 141 {
 142 }
 143
 144 static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
 145 {
 146 }
 147
 148 int set_memory_ro(unsigned long addr, int numpages);
 149 int set_memory_rw(unsigned long addr, int numpages);
 150 int set_memory_x(unsigned long addr, int numpages);
 151 int set_memory_nx(unsigned long addr, int numpages);
 152
 153 #endif