arch/arm64/include/asm/hw_breakpoint.h

   1 /*
   2  * Copyright (C) 2012 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16 #ifndef __ASM_HW_BREAKPOINT_H
  17 #define __ASM_HW_BREAKPOINT_H
  18
  19 #include <asm/cputype.h>
  20 #include <asm/cpufeature.h>
  21 #include <asm/sysreg.h>
  22 #include <asm/virt.h>
  23
  24 #ifdef __KERNEL__
  25
  26 struct arch_hw_breakpoint_ctrl {
  27         u32 __reserved  : 19,
  28         len             : 8,
  29         type            : 2,
  30         privilege       : 2,
  31         enabled         : 1;
  32 };
  33
  34 struct arch_hw_breakpoint {
  35         u64 address;
  36         u64 trigger;
  37         struct arch_hw_breakpoint_ctrl ctrl;
  38 };
  39
  40 /* Privilege Levels */
  41 #define AARCH64_BREAKPOINT_EL1  1
  42 #define AARCH64_BREAKPOINT_EL0  2
  43
  44 #define DBG_HMC_HYP             (1 << 13)
  45
  46 static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)
  47 {
  48         u32 val = (ctrl.len << 5) | (ctrl.type << 3) | (ctrl.privilege << 1) |
  49                 ctrl.enabled;
  50
  51         if (is_kernel_in_hyp_mode() && ctrl.privilege == AARCH64_BREAKPOINT_EL1)
  52                 val |= DBG_HMC_HYP;
  53
  54         return val;
  55 }
  56
  57 static inline void decode_ctrl_reg(u32 reg,
  58                                    struct arch_hw_breakpoint_ctrl *ctrl)
  59 {
  60         ctrl->enabled   = reg & 0x1;
  61         reg >>= 1;
  62         ctrl->privilege = reg & 0x3;
  63         reg >>= 2;
  64         ctrl->type      = reg & 0x3;
  65         reg >>= 2;
  66         ctrl->len       = reg & 0xff;
  67 }
  68
  69 /* Breakpoint */
  70 #define ARM_BREAKPOINT_EXECUTE  0
  71
  72 /* Watchpoints */
  73 #define ARM_BREAKPOINT_LOAD     1
  74 #define ARM_BREAKPOINT_STORE    2
  75 #define AARCH64_ESR_ACCESS_MASK (1 << 6)
  76
  77 /* Lengths */
  78 #define ARM_BREAKPOINT_LEN_1    0x1
  79 #define ARM_BREAKPOINT_LEN_2    0x3
  80 #define ARM_BREAKPOINT_LEN_4    0xf
  81 #define ARM_BREAKPOINT_LEN_8    0xff
  82
  83 /* Kernel stepping */
  84 #define ARM_KERNEL_STEP_NONE    0
  85 #define ARM_KERNEL_STEP_ACTIVE  1
  86 #define ARM_KERNEL_STEP_SUSPEND 2
  87
  88 /*
  89  * Limits.
  90  * Changing these will require modifications to the register accessors.
  91  */
  92 #define ARM_MAX_BRP             16
  93 #define ARM_MAX_WRP             16
  94
  95 /* Virtual debug register bases. */
  96 #define AARCH64_DBG_REG_BVR     0
  97 #define AARCH64_DBG_REG_BCR     (AARCH64_DBG_REG_BVR + ARM_MAX_BRP)
  98 #define AARCH64_DBG_REG_WVR     (AARCH64_DBG_REG_BCR + ARM_MAX_BRP)
  99 #define AARCH64_DBG_REG_WCR     (AARCH64_DBG_REG_WVR + ARM_MAX_WRP)
 100
 101 /* Debug register names. */
 102 #define AARCH64_DBG_REG_NAME_BVR        bvr
 103 #define AARCH64_DBG_REG_NAME_BCR        bcr
 104 #define AARCH64_DBG_REG_NAME_WVR        wvr
 105 #define AARCH64_DBG_REG_NAME_WCR        wcr
 106
 107 /* Accessor macros for the debug registers. */
 108 #define AARCH64_DBG_READ(N, REG, VAL) do {\
 109         VAL = read_sysreg(dbg##REG##N##_el1);\
 110 } while (0)
 111
 112 #define AARCH64_DBG_WRITE(N, REG, VAL) do {\
 113         write_sysreg(VAL, dbg##REG##N##_el1);\
 114 } while (0)
 115
 116 struct task_struct;
 117 struct notifier_block;
 118 struct perf_event;
 119 struct pmu;
 120
 121 extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
 122                                   int *gen_len, int *gen_type);
 123 extern int arch_check_bp_in_kernelspace(struct perf_event *bp);
 124 extern int arch_validate_hwbkpt_settings(struct perf_event *bp);
 125 extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
 126                                            unsigned long val, void *data);
 127
 128 extern int arch_install_hw_breakpoint(struct perf_event *bp);
 129 extern void arch_uninstall_hw_breakpoint(struct perf_event *bp);
 130 extern void hw_breakpoint_pmu_read(struct perf_event *bp);
 131 extern int hw_breakpoint_slots(int type);
 132
 133 #ifdef CONFIG_HAVE_HW_BREAKPOINT
 134 extern void hw_breakpoint_thread_switch(struct task_struct *next);
 135 extern void ptrace_hw_copy_thread(struct task_struct *task);
 136 #else
 137 static inline void hw_breakpoint_thread_switch(struct task_struct *next)
 138 {
 139 }
 140 static inline void ptrace_hw_copy_thread(struct task_struct *task)
 141 {
 142 }
 143 #endif
 144
 145 /* Determine number of BRP registers available. */
 146 static inline int get_num_brps(void)
 147 {
 148         u64 dfr0 = read_system_reg(SYS_ID_AA64DFR0_EL1);
 149         return 1 +
 150                 cpuid_feature_extract_unsigned_field(dfr0,
 151                                                 ID_AA64DFR0_BRPS_SHIFT);
 152 }
 153
 154 /* Determine number of WRP registers available. */
 155 static inline int get_num_wrps(void)
 156 {
 157         u64 dfr0 = read_system_reg(SYS_ID_AA64DFR0_EL1);
 158         return 1 +
 159                 cpuid_feature_extract_unsigned_field(dfr0,
 160                                                 ID_AA64DFR0_WRPS_SHIFT);
 161 }
 162
 163 #endif  /* __KERNEL__ */
 164 #endif  /* __ASM_BREAKPOINT_H */