arch/arm64/include/asm/io.h

   1 /*
   2  * Based on arch/arm/include/asm/io.h
   3  *
   4  * Copyright (C) 1996-2000 Russell King
   5  * Copyright (C) 2012 ARM Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef __ASM_IO_H
  20 #define __ASM_IO_H
  21
  22 #ifdef __KERNEL__
  23
  24 #include <linux/types.h>
  25 #include <linux/blk_types.h>
  26
  27 #include <asm/byteorder.h>
  28 #include <asm/barrier.h>
  29 #include <asm/memory.h>
  30 #include <asm/pgtable.h>
  31 #include <asm/early_ioremap.h>
  32 #include <asm/alternative.h>
  33 #include <asm/cpufeature.h>
  34
  35 #include <xen/xen.h>
  36
  37 /*
  38  * Generic IO read/write.  These perform native-endian accesses.
  39  */
  40 #define __raw_writeb __raw_writeb
  41 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
  42 {
  43         asm volatile("strb %w0, [%1]" : : "rZ" (val), "r" (addr));
  44 }
  45
  46 #define __raw_writew __raw_writew
  47 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
  48 {
  49         asm volatile("strh %w0, [%1]" : : "rZ" (val), "r" (addr));
  50 }
  51
  52 #define __raw_writel __raw_writel
  53 static inline void __raw_writel(u32 val, volatile void __iomem *addr)
  54 {
  55         asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr));
  56 }
  57
  58 #define __raw_writeq __raw_writeq
  59 static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
  60 {
  61         asm volatile("str %x0, [%1]" : : "rZ" (val), "r" (addr));
  62 }
  63
  64 #define __raw_readb __raw_readb
  65 static inline u8 __raw_readb(const volatile void __iomem *addr)
  66 {
  67         u8 val;
  68         asm volatile(ALTERNATIVE("ldrb %w0, [%1]",
  69                                  "ldarb %w0, [%1]",
  70                                  ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
  71                      : "=r" (val) : "r" (addr));
  72         return val;
  73 }
  74
  75 #define __raw_readw __raw_readw
  76 static inline u16 __raw_readw(const volatile void __iomem *addr)
  77 {
  78         u16 val;
  79
  80         asm volatile(ALTERNATIVE("ldrh %w0, [%1]",
  81                                  "ldarh %w0, [%1]",
  82                                  ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
  83                      : "=r" (val) : "r" (addr));
  84         return val;
  85 }
  86
  87 #define __raw_readl __raw_readl
  88 static inline u32 __raw_readl(const volatile void __iomem *addr)
  89 {
  90         u32 val;
  91         asm volatile(ALTERNATIVE("ldr %w0, [%1]",
  92                                  "ldar %w0, [%1]",
  93                                  ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
  94                      : "=r" (val) : "r" (addr));
  95         return val;
  96 }
  97
  98 #define __raw_readq __raw_readq
  99 static inline u64 __raw_readq(const volatile void __iomem *addr)
 100 {
 101         u64 val;
 102         asm volatile(ALTERNATIVE("ldr %0, [%1]",
 103                                  "ldar %0, [%1]",
 104                                  ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
 105                      : "=r" (val) : "r" (addr));
 106         return val;
 107 }
 108
 109 /* IO barriers */
 110 #define __iormb()               rmb()
 111 #define __iowmb()               wmb()
 112
 113 #define mmiowb()                do { } while (0)
 114
 115 /*
 116  * Relaxed I/O memory access primitives. These follow the Device memory
 117  * ordering rules but do not guarantee any ordering relative to Normal memory
 118  * accesses.
 119  */
 120 #define readb_relaxed(c)        ({ u8  __r = __raw_readb(c); __r; })
 121 #define readw_relaxed(c)        ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
 122 #define readl_relaxed(c)        ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
 123 #define readq_relaxed(c)        ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
 124
 125 #define writeb_relaxed(v,c)     ((void)__raw_writeb((v),(c)))
 126 #define writew_relaxed(v,c)     ((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
 127 #define writel_relaxed(v,c)     ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
 128 #define writeq_relaxed(v,c)     ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
 129
 130 /*
 131  * I/O memory access primitives. Reads are ordered relative to any
 132  * following Normal memory access. Writes are ordered relative to any prior
 133  * Normal memory access.
 134  */
 135 #define readb(c)                ({ u8  __v = readb_relaxed(c); __iormb(); __v; })
 136 #define readw(c)                ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
 137 #define readl(c)                ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
 138 #define readq(c)                ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
 139
 140 #define writeb(v,c)             ({ __iowmb(); writeb_relaxed((v),(c)); })
 141 #define writew(v,c)             ({ __iowmb(); writew_relaxed((v),(c)); })
 142 #define writel(v,c)             ({ __iowmb(); writel_relaxed((v),(c)); })
 143 #define writeq(v,c)             ({ __iowmb(); writeq_relaxed((v),(c)); })
 144
 145 /*
 146  *  I/O port access primitives.
 147  */
 148 #define arch_has_dev_port()     (1)
 149 #define IO_SPACE_LIMIT          (PCI_IO_SIZE - 1)
 150 #define PCI_IOBASE              ((void __iomem *)PCI_IO_START)
 151
 152 /*
 153  * String version of I/O memory access operations.
 154  */
 155 extern void __memcpy_fromio(void *, const volatile void __iomem *, size_t);
 156 extern void __memcpy_toio(volatile void __iomem *, const void *, size_t);
 157 extern void __memset_io(volatile void __iomem *, int, size_t);
 158
 159 #define memset_io(c,v,l)        __memset_io((c),(v),(l))
 160 #define memcpy_fromio(a,c,l)    __memcpy_fromio((a),(c),(l))
 161 #define memcpy_toio(c,a,l)      __memcpy_toio((c),(a),(l))
 162
 163 /*
 164  * I/O memory mapping functions.
 165  */
 166 extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot);
 167 extern void __iounmap(volatile void __iomem *addr);
 168 extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size);
 169
 170 #define ioremap(addr, size)             __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
 171 #define ioremap_nocache(addr, size)     __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
 172 #define ioremap_wc(addr, size)          __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
 173 #define ioremap_wt(addr, size)          __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
 174 #define iounmap                         __iounmap
 175
 176 /*
 177  * io{read,write}{16,32,64}be() macros
 178  */
 179 #define ioread16be(p)           ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
 180 #define ioread32be(p)           ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
 181 #define ioread64be(p)           ({ __u64 __v = be64_to_cpu((__force __be64)__raw_readq(p)); __iormb(); __v; })
 182
 183 #define iowrite16be(v,p)        ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
 184 #define iowrite32be(v,p)        ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
 185 #define iowrite64be(v,p)        ({ __iowmb(); __raw_writeq((__force __u64)cpu_to_be64(v), p); })
 186
 187 #include <asm-generic/io.h>
 188
 189 /*
 190  * More restrictive address range checking than the default implementation
 191  * (PHYS_OFFSET and PHYS_MASK taken into account).
 192  */
 193 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
 194 extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
 195 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
 196
 197 extern int devmem_is_allowed(unsigned long pfn);
 198
 199 struct bio_vec;
 200 extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
 201                                       const struct bio_vec *vec2);
 202 #define BIOVEC_PHYS_MERGEABLE(vec1, vec2)                               \
 203         (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) &&                         \
 204          (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2)))
 205
 206 #endif  /* __KERNEL__ */
 207 #endif  /* __ASM_IO_H */