arch/arm64/include/asm/kvm_mmu.h

   1 /*
   2  * Copyright (C) 2012,2013 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef __ARM64_KVM_MMU_H__
  19 #define __ARM64_KVM_MMU_H__
  20
  21 #include <asm/page.h>
  22 #include <asm/memory.h>
  23 #include <asm/cpufeature.h>
  24
  25 /*
  26  * As ARMv8.0 only has the TTBR0_EL2 register, we cannot express
  27  * "negative" addresses. This makes it impossible to directly share
  28  * mappings with the kernel.
  29  *
  30  * Instead, give the HYP mode its own VA region at a fixed offset from
  31  * the kernel by just masking the top bits (which are all ones for a
  32  * kernel address). We need to find out how many bits to mask.
  33  *
  34  * We want to build a set of page tables that cover both parts of the
  35  * idmap (the trampoline page used to initialize EL2), and our normal
  36  * runtime VA space, at the same time.
  37  *
  38  * Given that the kernel uses VA_BITS for its entire address space,
  39  * and that half of that space (VA_BITS - 1) is used for the linear
  40  * mapping, we can also limit the EL2 space to (VA_BITS - 1).
  41  *
  42  * The main question is "Within the VA_BITS space, does EL2 use the
  43  * top or the bottom half of that space to shadow the kernel's linear
  44  * mapping?". As we need to idmap the trampoline page, this is
  45  * determined by the range in which this page lives.
  46  *
  47  * If the page is in the bottom half, we have to use the top half. If
  48  * the page is in the top half, we have to use the bottom half:
  49  *
  50  * T = __virt_to_phys(__hyp_idmap_text_start)
  51  * if (T & BIT(VA_BITS - 1))
  52  *      HYP_VA_MIN = 0  //idmap in upper half
  53  * else
  54  *      HYP_VA_MIN = 1 << (VA_BITS - 1)
  55  * HYP_VA_MAX = HYP_VA_MIN + (1 << (VA_BITS - 1)) - 1
  56  *
  57  * This of course assumes that the trampoline page exists within the
  58  * VA_BITS range. If it doesn't, then it means we're in the odd case
  59  * where the kernel idmap (as well as HYP) uses more levels than the
  60  * kernel runtime page tables (as seen when the kernel is configured
  61  * for 4k pages, 39bits VA, and yet memory lives just above that
  62  * limit, forcing the idmap to use 4 levels of page tables while the
  63  * kernel itself only uses 3). In this particular case, it doesn't
  64  * matter which side of VA_BITS we use, as we're guaranteed not to
  65  * conflict with anything.
  66  *
  67  * When using VHE, there are no separate hyp mappings and all KVM
  68  * functionality is already mapped as part of the main kernel
  69  * mappings, and none of this applies in that case.
  70  */
  71
  72 #define HYP_PAGE_OFFSET_HIGH_MASK       ((UL(1) << VA_BITS) - 1)
  73 #define HYP_PAGE_OFFSET_LOW_MASK        ((UL(1) << (VA_BITS - 1)) - 1)
  74
  75 #ifdef __ASSEMBLY__
  76
  77 #include <asm/alternative.h>
  78 #include <asm/cpufeature.h>
  79
  80 /*
  81  * Convert a kernel VA into a HYP VA.
  82  * reg: VA to be converted.
  83  *
  84  * This generates the following sequences:
  85  * - High mask:
  86  *              and x0, x0, #HYP_PAGE_OFFSET_HIGH_MASK
  87  *              nop
  88  * - Low mask:
  89  *              and x0, x0, #HYP_PAGE_OFFSET_HIGH_MASK
  90  *              and x0, x0, #HYP_PAGE_OFFSET_LOW_MASK
  91  * - VHE:
  92  *              nop
  93  *              nop
  94  *
  95  * The "low mask" version works because the mask is a strict subset of
  96  * the "high mask", hence performing the first mask for nothing.
  97  * Should be completely invisible on any viable CPU.
  98  */
  99 .macro kern_hyp_va      reg
 100 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
 101         and     \reg, \reg, #HYP_PAGE_OFFSET_HIGH_MASK
 102 alternative_else
 103         nop
 104 alternative_endif
 105 alternative_if_not ARM64_HYP_OFFSET_LOW
 106         nop
 107 alternative_else
 108         and     \reg, \reg, #HYP_PAGE_OFFSET_LOW_MASK
 109 alternative_endif
 110 .endm
 111
 112 #else
 113
 114 #include <asm/pgalloc.h>
 115 #include <asm/cachetype.h>
 116 #include <asm/cacheflush.h>
 117 #include <asm/mmu_context.h>
 118 #include <asm/pgtable.h>
 119
 120 static inline unsigned long __kern_hyp_va(unsigned long v)
 121 {
 122         asm volatile(ALTERNATIVE("and %0, %0, %1",
 123                                  "nop",
 124                                  ARM64_HAS_VIRT_HOST_EXTN)
 125                      : "+r" (v)
 126                      : "i" (HYP_PAGE_OFFSET_HIGH_MASK));
 127         asm volatile(ALTERNATIVE("nop",
 128                                  "and %0, %0, %1",
 129                                  ARM64_HYP_OFFSET_LOW)
 130                      : "+r" (v)
 131                      : "i" (HYP_PAGE_OFFSET_LOW_MASK));
 132         return v;
 133 }
 134
 135 #define kern_hyp_va(v)  (typeof(v))(__kern_hyp_va((unsigned long)(v)))
 136
 137 /*
 138  * We currently only support a 40bit IPA.
 139  */
 140 #define KVM_PHYS_SHIFT  (40)
 141 #define KVM_PHYS_SIZE   (1UL << KVM_PHYS_SHIFT)
 142 #define KVM_PHYS_MASK   (KVM_PHYS_SIZE - 1UL)
 143
 144 #include <asm/stage2_pgtable.h>
 145
 146 int create_hyp_mappings(void *from, void *to, pgprot_t prot);
 147 int create_hyp_io_mappings(void *from, void *to, phys_addr_t);
 148 void free_hyp_pgds(void);
 149
 150 void stage2_unmap_vm(struct kvm *kvm);
 151 int kvm_alloc_stage2_pgd(struct kvm *kvm);
 152 void kvm_free_stage2_pgd(struct kvm *kvm);
 153 int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
 154                           phys_addr_t pa, unsigned long size, bool writable);
 155
 156 int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run);
 157
 158 void kvm_mmu_free_memory_caches(struct kvm_vcpu *vcpu);
 159
 160 phys_addr_t kvm_mmu_get_httbr(void);
 161 phys_addr_t kvm_get_idmap_vector(void);
 162 phys_addr_t kvm_get_idmap_start(void);
 163 int kvm_mmu_init(void);
 164 void kvm_clear_hyp_idmap(void);
 165
 166 #define kvm_set_pte(ptep, pte)          set_pte(ptep, pte)
 167 #define kvm_set_pmd(pmdp, pmd)          set_pmd(pmdp, pmd)
 168
 169 static inline void kvm_clean_pgd(pgd_t *pgd) {}
 170 static inline void kvm_clean_pmd(pmd_t *pmd) {}
 171 static inline void kvm_clean_pmd_entry(pmd_t *pmd) {}
 172 static inline void kvm_clean_pte(pte_t *pte) {}
 173 static inline void kvm_clean_pte_entry(pte_t *pte) {}
 174
 175 static inline pte_t kvm_s2pte_mkwrite(pte_t pte)
 176 {
 177         pte_val(pte) |= PTE_S2_RDWR;
 178         return pte;
 179 }
 180
 181 static inline pmd_t kvm_s2pmd_mkwrite(pmd_t pmd)
 182 {
 183         pmd_val(pmd) |= PMD_S2_RDWR;
 184         return pmd;
 185 }
 186
 187 static inline void kvm_set_s2pte_readonly(pte_t *pte)
 188 {
 189         pteval_t pteval;
 190         unsigned long tmp;
 191
 192         asm volatile("//        kvm_set_s2pte_readonly\n"
 193         "       prfm    pstl1strm, %2\n"
 194         "1:     ldxr    %0, %2\n"
 195         "       and     %0, %0, %3              // clear PTE_S2_RDWR\n"
 196         "       orr     %0, %0, %4              // set PTE_S2_RDONLY\n"
 197         "       stxr    %w1, %0, %2\n"
 198         "       cbnz    %w1, 1b\n"
 199         : "=&r" (pteval), "=&r" (tmp), "+Q" (pte_val(*pte))
 200         : "L" (~PTE_S2_RDWR), "L" (PTE_S2_RDONLY));
 201 }
 202
 203 static inline bool kvm_s2pte_readonly(pte_t *pte)
 204 {
 205         return (pte_val(*pte) & PTE_S2_RDWR) == PTE_S2_RDONLY;
 206 }
 207
 208 static inline void kvm_set_s2pmd_readonly(pmd_t *pmd)
 209 {
 210         kvm_set_s2pte_readonly((pte_t *)pmd);
 211 }
 212
 213 static inline bool kvm_s2pmd_readonly(pmd_t *pmd)
 214 {
 215         return kvm_s2pte_readonly((pte_t *)pmd);
 216 }
 217
 218 static inline bool kvm_page_empty(void *ptr)
 219 {
 220         struct page *ptr_page = virt_to_page(ptr);
 221         return page_count(ptr_page) == 1;
 222 }
 223
 224 #define hyp_pte_table_empty(ptep) kvm_page_empty(ptep)
 225
 226 #ifdef __PAGETABLE_PMD_FOLDED
 227 #define hyp_pmd_table_empty(pmdp) (0)
 228 #else
 229 #define hyp_pmd_table_empty(pmdp) kvm_page_empty(pmdp)
 230 #endif
 231
 232 #ifdef __PAGETABLE_PUD_FOLDED
 233 #define hyp_pud_table_empty(pudp) (0)
 234 #else
 235 #define hyp_pud_table_empty(pudp) kvm_page_empty(pudp)
 236 #endif
 237
 238 struct kvm;
 239
 240 #define kvm_flush_dcache_to_poc(a,l)    __flush_dcache_area((a), (l))
 241
 242 static inline bool vcpu_has_cache_enabled(struct kvm_vcpu *vcpu)
 243 {
 244         return (vcpu_sys_reg(vcpu, SCTLR_EL1) & 0b101) == 0b101;
 245 }
 246
 247 static inline void __coherent_cache_guest_page(struct kvm_vcpu *vcpu,
 248                                                kvm_pfn_t pfn,
 249                                                unsigned long size,
 250                                                bool ipa_uncached)
 251 {
 252         void *va = page_address(pfn_to_page(pfn));
 253
 254         if (!vcpu_has_cache_enabled(vcpu) || ipa_uncached)
 255                 kvm_flush_dcache_to_poc(va, size);
 256
 257         if (!icache_is_aliasing()) {            /* PIPT */
 258                 flush_icache_range((unsigned long)va,
 259                                    (unsigned long)va + size);
 260         } else if (!icache_is_aivivt()) {       /* non ASID-tagged VIVT */
 261                 /* any kind of VIPT cache */
 262                 __flush_icache_all();
 263         }
 264 }
 265
 266 static inline void __kvm_flush_dcache_pte(pte_t pte)
 267 {
 268         struct page *page = pte_page(pte);
 269         kvm_flush_dcache_to_poc(page_address(page), PAGE_SIZE);
 270 }
 271
 272 static inline void __kvm_flush_dcache_pmd(pmd_t pmd)
 273 {
 274         struct page *page = pmd_page(pmd);
 275         kvm_flush_dcache_to_poc(page_address(page), PMD_SIZE);
 276 }
 277
 278 static inline void __kvm_flush_dcache_pud(pud_t pud)
 279 {
 280         struct page *page = pud_page(pud);
 281         kvm_flush_dcache_to_poc(page_address(page), PUD_SIZE);
 282 }
 283
 284 #define kvm_virt_to_phys(x)             __virt_to_phys((unsigned long)(x))
 285
 286 void kvm_set_way_flush(struct kvm_vcpu *vcpu);
 287 void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled);
 288
 289 static inline bool __kvm_cpu_uses_extended_idmap(void)
 290 {
 291         return __cpu_uses_extended_idmap();
 292 }
 293
 294 static inline void __kvm_extend_hypmap(pgd_t *boot_hyp_pgd,
 295                                        pgd_t *hyp_pgd,
 296                                        pgd_t *merged_hyp_pgd,
 297                                        unsigned long hyp_idmap_start)
 298 {
 299         int idmap_idx;
 300
 301         /*
 302          * Use the first entry to access the HYP mappings. It is
 303          * guaranteed to be free, otherwise we wouldn't use an
 304          * extended idmap.
 305          */
 306         VM_BUG_ON(pgd_val(merged_hyp_pgd[0]));
 307         merged_hyp_pgd[0] = __pgd(__pa(hyp_pgd) | PMD_TYPE_TABLE);
 308
 309         /*
 310          * Create another extended level entry that points to the boot HYP map,
 311          * which contains an ID mapping of the HYP init code. We essentially
 312          * merge the boot and runtime HYP maps by doing so, but they don't
 313          * overlap anyway, so this is fine.
 314          */
 315         idmap_idx = hyp_idmap_start >> VA_BITS;
 316         VM_BUG_ON(pgd_val(merged_hyp_pgd[idmap_idx]));
 317         merged_hyp_pgd[idmap_idx] = __pgd(__pa(boot_hyp_pgd) | PMD_TYPE_TABLE);
 318 }
 319
 320 static inline unsigned int kvm_get_vmid_bits(void)
 321 {
 322         int reg = read_system_reg(SYS_ID_AA64MMFR1_EL1);
 323
 324         return (cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR1_VMIDBITS_SHIFT) == 2) ? 16 : 8;
 325 }
 326
 327 #endif /* __ASSEMBLY__ */
 328 #endif /* __ARM64_KVM_MMU_H__ */