arch/arm64/include/asm/mmu_context.h

   1 /*
   2  * Based on arch/arm/include/asm/mmu_context.h
   3  *
   4  * Copyright (C) 1996 Russell King.
   5  * Copyright (C) 2012 ARM Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef __ASM_MMU_CONTEXT_H
  20 #define __ASM_MMU_CONTEXT_H
  21
  22 #include <linux/compiler.h>
  23 #include <linux/sched.h>
  24
  25 #include <asm/cacheflush.h>
  26 #include <asm/proc-fns.h>
  27 #include <asm-generic/mm_hooks.h>
  28 #include <asm/cputype.h>
  29 #include <asm/pgtable.h>
  30 #include <asm/sysreg.h>
  31 #include <asm/tlbflush.h>
  32
  33 static inline void contextidr_thread_switch(struct task_struct *next)
  34 {
  35         if (!IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR))
  36                 return;
  37
  38         write_sysreg(task_pid_nr(next), contextidr_el1);
  39         isb();
  40 }
  41
  42 /*
  43  * Set TTBR0 to empty_zero_page. No translations will be possible via TTBR0.
  44  */
  45 static inline void cpu_set_reserved_ttbr0(void)
  46 {
  47         unsigned long ttbr = virt_to_phys(empty_zero_page);
  48
  49         write_sysreg(ttbr, ttbr0_el1);
  50         isb();
  51 }
  52
  53 /*
  54  * TCR.T0SZ value to use when the ID map is active. Usually equals
  55  * TCR_T0SZ(VA_BITS), unless system RAM is positioned very high in
  56  * physical memory, in which case it will be smaller.
  57  */
  58 extern u64 idmap_t0sz;
  59
  60 static inline bool __cpu_uses_extended_idmap(void)
  61 {
  62         return (!IS_ENABLED(CONFIG_ARM64_VA_BITS_48) &&
  63                 unlikely(idmap_t0sz != TCR_T0SZ(VA_BITS)));
  64 }
  65
  66 /*
  67  * Set TCR.T0SZ to its default value (based on VA_BITS)
  68  */
  69 static inline void __cpu_set_tcr_t0sz(unsigned long t0sz)
  70 {
  71         unsigned long tcr;
  72
  73         if (!__cpu_uses_extended_idmap())
  74                 return;
  75
  76         tcr = read_sysreg(tcr_el1);
  77         tcr &= ~TCR_T0SZ_MASK;
  78         tcr |= t0sz << TCR_T0SZ_OFFSET;
  79         write_sysreg(tcr, tcr_el1);
  80         isb();
  81 }
  82
  83 #define cpu_set_default_tcr_t0sz()      __cpu_set_tcr_t0sz(TCR_T0SZ(VA_BITS))
  84 #define cpu_set_idmap_tcr_t0sz()        __cpu_set_tcr_t0sz(idmap_t0sz)
  85
  86 /*
  87  * Remove the idmap from TTBR0_EL1 and install the pgd of the active mm.
  88  *
  89  * The idmap lives in the same VA range as userspace, but uses global entries
  90  * and may use a different TCR_EL1.T0SZ. To avoid issues resulting from
  91  * speculative TLB fetches, we must temporarily install the reserved page
  92  * tables while we invalidate the TLBs and set up the correct TCR_EL1.T0SZ.
  93  *
  94  * If current is a not a user task, the mm covers the TTBR1_EL1 page tables,
  95  * which should not be installed in TTBR0_EL1. In this case we can leave the
  96  * reserved page tables in place.
  97  */
  98 static inline void cpu_uninstall_idmap(void)
  99 {
 100         struct mm_struct *mm = current->active_mm;
 101
 102         cpu_set_reserved_ttbr0();
 103         local_flush_tlb_all();
 104         cpu_set_default_tcr_t0sz();
 105
 106         if (mm != &init_mm)
 107                 cpu_switch_mm(mm->pgd, mm);
 108 }
 109
 110 static inline void cpu_install_idmap(void)
 111 {
 112         cpu_set_reserved_ttbr0();
 113         local_flush_tlb_all();
 114         cpu_set_idmap_tcr_t0sz();
 115
 116         cpu_switch_mm(idmap_pg_dir, &init_mm);
 117 }
 118
 119 /*
 120  * Atomically replaces the active TTBR1_EL1 PGD with a new VA-compatible PGD,
 121  * avoiding the possibility of conflicting TLB entries being allocated.
 122  */
 123 static inline void cpu_replace_ttbr1(pgd_t *pgd)
 124 {
 125         typedef void (ttbr_replace_func)(phys_addr_t);
 126         extern ttbr_replace_func idmap_cpu_replace_ttbr1;
 127         ttbr_replace_func *replace_phys;
 128
 129         phys_addr_t pgd_phys = virt_to_phys(pgd);
 130
 131         replace_phys = (void *)virt_to_phys(idmap_cpu_replace_ttbr1);
 132
 133         cpu_install_idmap();
 134         replace_phys(pgd_phys);
 135         cpu_uninstall_idmap();
 136 }
 137
 138 /*
 139  * It would be nice to return ASIDs back to the allocator, but unfortunately
 140  * that introduces a race with a generation rollover where we could erroneously
 141  * free an ASID allocated in a future generation. We could workaround this by
 142  * freeing the ASID from the context of the dying mm (e.g. in arch_exit_mmap),
 143  * but we'd then need to make sure that we didn't dirty any TLBs afterwards.
 144  * Setting a reserved TTBR0 or EPD0 would work, but it all gets ugly when you
 145  * take CPU migration into account.
 146  */
 147 #define destroy_context(mm)             do { } while(0)
 148 void check_and_switch_context(struct mm_struct *mm, unsigned int cpu);
 149
 150 #define init_new_context(tsk,mm)        ({ atomic64_set(&(mm)->context.id, 0); 0; })
 151
 152 /*
 153  * This is called when "tsk" is about to enter lazy TLB mode.
 154  *
 155  * mm:  describes the currently active mm context
 156  * tsk: task which is entering lazy tlb
 157  * cpu: cpu number which is entering lazy tlb
 158  *
 159  * tsk->mm will be NULL
 160  */
 161 static inline void
 162 enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 163 {
 164 }
 165
 166 /*
 167  * This is the actual mm switch as far as the scheduler
 168  * is concerned.  No registers are touched.  We avoid
 169  * calling the CPU specific function when the mm hasn't
 170  * actually changed.
 171  */
 172 static inline void
 173 switch_mm(struct mm_struct *prev, struct mm_struct *next,
 174           struct task_struct *tsk)
 175 {
 176         unsigned int cpu = smp_processor_id();
 177
 178         if (prev == next)
 179                 return;
 180
 181         /*
 182          * init_mm.pgd does not contain any user mappings and it is always
 183          * active for kernel addresses in TTBR1. Just set the reserved TTBR0.
 184          */
 185         if (next == &init_mm) {
 186                 cpu_set_reserved_ttbr0();
 187                 return;
 188         }
 189
 190         check_and_switch_context(next, cpu);
 191 }
 192
 193 #define deactivate_mm(tsk,mm)   do { } while (0)
 194 #define activate_mm(prev,next)  switch_mm(prev, next, NULL)
 195
 196 void verify_cpu_asid_bits(void);
 197
 198 #endif