arch/arm64/include/asm/mmu_context.h

   1 /*
   2  * Based on arch/arm/include/asm/mmu_context.h
   3  *
   4  * Copyright (C) 1996 Russell King.
   5  * Copyright (C) 2012 ARM Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef __ASM_MMU_CONTEXT_H
  20 #define __ASM_MMU_CONTEXT_H
  21
  22 #include <linux/compiler.h>
  23 #include <linux/sched.h>
  24
  25 #include <asm/cacheflush.h>
  26 #include <asm/proc-fns.h>
  27 #include <asm-generic/mm_hooks.h>
  28 #include <asm/cputype.h>
  29 #include <asm/pgtable.h>
  30 #include <asm/tlbflush.h>
  31
  32 #ifdef CONFIG_PID_IN_CONTEXTIDR
  33 static inline void contextidr_thread_switch(struct task_struct *next)
  34 {
  35         asm(
  36         "       msr     contextidr_el1, %0\n"
  37         "       isb"
  38         :
  39         : "r" (task_pid_nr(next)));
  40 }
  41 #else
  42 static inline void contextidr_thread_switch(struct task_struct *next)
  43 {
  44 }
  45 #endif
  46
  47 /*
  48  * Set TTBR0 to empty_zero_page. No translations will be possible via TTBR0.
  49  */
  50 static inline void cpu_set_reserved_ttbr0(void)
  51 {
  52         unsigned long ttbr = virt_to_phys(empty_zero_page);
  53
  54         asm(
  55         "       msr     ttbr0_el1, %0                   // set TTBR0\n"
  56         "       isb"
  57         :
  58         : "r" (ttbr));
  59 }
  60
  61 /*
  62  * TCR.T0SZ value to use when the ID map is active. Usually equals
  63  * TCR_T0SZ(VA_BITS), unless system RAM is positioned very high in
  64  * physical memory, in which case it will be smaller.
  65  */
  66 extern u64 idmap_t0sz;
  67
  68 static inline bool __cpu_uses_extended_idmap(void)
  69 {
  70         return (!IS_ENABLED(CONFIG_ARM64_VA_BITS_48) &&
  71                 unlikely(idmap_t0sz != TCR_T0SZ(VA_BITS)));
  72 }
  73
  74 /*
  75  * Set TCR.T0SZ to its default value (based on VA_BITS)
  76  */
  77 static inline void cpu_set_default_tcr_t0sz(void)
  78 {
  79         unsigned long tcr;
  80
  81         if (!__cpu_uses_extended_idmap())
  82                 return;
  83
  84         asm volatile (
  85         "       mrs     %0, tcr_el1     ;"
  86         "       bfi     %0, %1, %2, %3  ;"
  87         "       msr     tcr_el1, %0     ;"
  88         "       isb"
  89         : "=&r" (tcr)
  90         : "r"(TCR_T0SZ(VA_BITS)), "I"(TCR_T0SZ_OFFSET), "I"(TCR_TxSZ_WIDTH));
  91 }
  92
  93 /*
  94  * Remove the idmap from TTBR0_EL1 and install the pgd of the active mm.
  95  *
  96  * The idmap lives in the same VA range as userspace, but uses global entries
  97  * and may use a different TCR_EL1.T0SZ. To avoid issues resulting from
  98  * speculative TLB fetches, we must temporarily install the reserved page
  99  * tables while we invalidate the TLBs and set up the correct TCR_EL1.T0SZ.
 100  *
 101  * If current is a not a user task, the mm covers the TTBR1_EL1 page tables,
 102  * which should not be installed in TTBR0_EL1. In this case we can leave the
 103  * reserved page tables in place.
 104  */
 105 static inline void cpu_uninstall_idmap(void)
 106 {
 107         struct mm_struct *mm = current->active_mm;
 108
 109         cpu_set_reserved_ttbr0();
 110         local_flush_tlb_all();
 111         cpu_set_default_tcr_t0sz();
 112
 113         if (mm != &init_mm)
 114                 cpu_switch_mm(mm->pgd, mm);
 115 }
 116
 117 /*
 118  * It would be nice to return ASIDs back to the allocator, but unfortunately
 119  * that introduces a race with a generation rollover where we could erroneously
 120  * free an ASID allocated in a future generation. We could workaround this by
 121  * freeing the ASID from the context of the dying mm (e.g. in arch_exit_mmap),
 122  * but we'd then need to make sure that we didn't dirty any TLBs afterwards.
 123  * Setting a reserved TTBR0 or EPD0 would work, but it all gets ugly when you
 124  * take CPU migration into account.
 125  */
 126 #define destroy_context(mm)             do { } while(0)
 127 void check_and_switch_context(struct mm_struct *mm, unsigned int cpu);
 128
 129 #define init_new_context(tsk,mm)        ({ atomic64_set(&(mm)->context.id, 0); 0; })
 130
 131 /*
 132  * This is called when "tsk" is about to enter lazy TLB mode.
 133  *
 134  * mm:  describes the currently active mm context
 135  * tsk: task which is entering lazy tlb
 136  * cpu: cpu number which is entering lazy tlb
 137  *
 138  * tsk->mm will be NULL
 139  */
 140 static inline void
 141 enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 142 {
 143 }
 144
 145 /*
 146  * This is the actual mm switch as far as the scheduler
 147  * is concerned.  No registers are touched.  We avoid
 148  * calling the CPU specific function when the mm hasn't
 149  * actually changed.
 150  */
 151 static inline void
 152 switch_mm(struct mm_struct *prev, struct mm_struct *next,
 153           struct task_struct *tsk)
 154 {
 155         unsigned int cpu = smp_processor_id();
 156
 157         if (prev == next)
 158                 return;
 159
 160         /*
 161          * init_mm.pgd does not contain any user mappings and it is always
 162          * active for kernel addresses in TTBR1. Just set the reserved TTBR0.
 163          */
 164         if (next == &init_mm) {
 165                 cpu_set_reserved_ttbr0();
 166                 return;
 167         }
 168
 169         check_and_switch_context(next, cpu);
 170 }
 171
 172 #define deactivate_mm(tsk,mm)   do { } while (0)
 173 #define activate_mm(prev,next)  switch_mm(prev, next, NULL)
 174
 175 #endif