arch/arm64/kernel/cpu_errata.c

   1 /*
   2  * Contains CPU specific errata definitions
   3  *
   4  * Copyright (C) 2014 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/types.h>
  20 #include <asm/cpu.h>
  21 #include <asm/cputype.h>
  22 #include <asm/cpufeature.h>
  23
  24 static bool __maybe_unused
  25 is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
  26 {
  27         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
  28         return MIDR_IS_CPU_MODEL_RANGE(read_cpuid_id(), entry->midr_model,
  29                                        entry->midr_range_min,
  30                                        entry->midr_range_max);
  31 }
  32
  33 static bool
  34 has_mismatched_cache_line_size(const struct arm64_cpu_capabilities *entry,
  35                                 int scope)
  36 {
  37         WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
  38         return (read_cpuid_cachetype() & arm64_ftr_reg_ctrel0.strict_mask) !=
  39                 (arm64_ftr_reg_ctrel0.sys_val & arm64_ftr_reg_ctrel0.strict_mask);
  40 }
  41
  42 static void cpu_enable_trap_ctr_access(void *__unused)
  43 {
  44         /* Clear SCTLR_EL1.UCT */
  45         config_sctlr_el1(SCTLR_EL1_UCT, 0);
  46 }
  47
  48 #define MIDR_RANGE(model, min, max) \
  49         .def_scope = SCOPE_LOCAL_CPU, \
  50         .matches = is_affected_midr_range, \
  51         .midr_model = model, \
  52         .midr_range_min = min, \
  53         .midr_range_max = max
  54
  55 const struct arm64_cpu_capabilities arm64_errata[] = {
  56 #if     defined(CONFIG_ARM64_ERRATUM_826319) || \
  57         defined(CONFIG_ARM64_ERRATUM_827319) || \
  58         defined(CONFIG_ARM64_ERRATUM_824069)
  59         {
  60         /* Cortex-A53 r0p[012] */
  61                 .desc = "ARM errata 826319, 827319, 824069",
  62                 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
  63                 MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x02),
  64                 .enable = cpu_enable_cache_maint_trap,
  65         },
  66 #endif
  67 #ifdef CONFIG_ARM64_ERRATUM_819472
  68         {
  69         /* Cortex-A53 r0p[01] */
  70                 .desc = "ARM errata 819472",
  71                 .capability = ARM64_WORKAROUND_CLEAN_CACHE,
  72                 MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x01),
  73                 .enable = cpu_enable_cache_maint_trap,
  74         },
  75 #endif
  76 #ifdef CONFIG_ARM64_ERRATUM_832075
  77         {
  78         /* Cortex-A57 r0p0 - r1p2 */
  79                 .desc = "ARM erratum 832075",
  80                 .capability = ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE,
  81                 MIDR_RANGE(MIDR_CORTEX_A57, 0x00,
  82                            (1 << MIDR_VARIANT_SHIFT) | 2),
  83         },
  84 #endif
  85 #ifdef CONFIG_ARM64_ERRATUM_834220
  86         {
  87         /* Cortex-A57 r0p0 - r1p2 */
  88                 .desc = "ARM erratum 834220",
  89                 .capability = ARM64_WORKAROUND_834220,
  90                 MIDR_RANGE(MIDR_CORTEX_A57, 0x00,
  91                            (1 << MIDR_VARIANT_SHIFT) | 2),
  92         },
  93 #endif
  94 #ifdef CONFIG_ARM64_ERRATUM_845719
  95         {
  96         /* Cortex-A53 r0p[01234] */
  97                 .desc = "ARM erratum 845719",
  98                 .capability = ARM64_WORKAROUND_845719,
  99                 MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04),
 100         },
 101 #endif
 102 #ifdef CONFIG_CAVIUM_ERRATUM_23154
 103         {
 104         /* Cavium ThunderX, pass 1.x */
 105                 .desc = "Cavium erratum 23154",
 106                 .capability = ARM64_WORKAROUND_CAVIUM_23154,
 107                 MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01),
 108         },
 109 #endif
 110 #ifdef CONFIG_CAVIUM_ERRATUM_27456
 111         {
 112         /* Cavium ThunderX, T88 pass 1.x - 2.1 */
 113                 .desc = "Cavium erratum 27456",
 114                 .capability = ARM64_WORKAROUND_CAVIUM_27456,
 115                 MIDR_RANGE(MIDR_THUNDERX, 0x00,
 116                            (1 << MIDR_VARIANT_SHIFT) | 1),
 117         },
 118         {
 119         /* Cavium ThunderX, T81 pass 1.0 */
 120                 .desc = "Cavium erratum 27456",
 121                 .capability = ARM64_WORKAROUND_CAVIUM_27456,
 122                 MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00),
 123         },
 124 #endif
 125         {
 126                 .desc = "Mismatched cache line size",
 127                 .capability = ARM64_MISMATCHED_CACHE_LINE_SIZE,
 128                 .matches = has_mismatched_cache_line_size,
 129                 .def_scope = SCOPE_LOCAL_CPU,
 130                 .enable = cpu_enable_trap_ctr_access,
 131         },
 132         {
 133         }
 134 };
 135
 136 /*
 137  * The CPU Errata work arounds are detected and applied at boot time
 138  * and the related information is freed soon after. If the new CPU requires
 139  * an errata not detected at boot, fail this CPU.
 140  */
 141 void verify_local_cpu_errata_workarounds(void)
 142 {
 143         const struct arm64_cpu_capabilities *caps = arm64_errata;
 144
 145         for (; caps->matches; caps++)
 146                 if (!cpus_have_cap(caps->capability) &&
 147                         caps->matches(caps, SCOPE_LOCAL_CPU)) {
 148                         pr_crit("CPU%d: Requires work around for %s, not detected"
 149                                         " at boot time\n",
 150                                 smp_processor_id(),
 151                                 caps->desc ? : "an erratum");
 152                         cpu_die_early();
 153                 }
 154 }
 155
 156 void update_cpu_errata_workarounds(void)
 157 {
 158         update_cpu_capabilities(arm64_errata, "enabling workaround for");
 159 }
 160
 161 void __init enable_errata_workarounds(void)
 162 {
 163         enable_cpu_capabilities(arm64_errata);
 164 }