arch/mips/bmips/setup.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   7  * Copyright (C) 2014 Kevin Cernekee <cernekee@gmail.com>
   8  */
   9
  10 #include <linux/init.h>
  11 #include <linux/bitops.h>
  12 #include <linux/bootmem.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/ioport.h>
  15 #include <linux/kernel.h>
  16 #include <linux/io.h>
  17 #include <linux/of.h>
  18 #include <linux/of_fdt.h>
  19 #include <linux/of_platform.h>
  20 #include <linux/smp.h>
  21 #include <asm/addrspace.h>
  22 #include <asm/bmips.h>
  23 #include <asm/bootinfo.h>
  24 #include <asm/cpu-type.h>
  25 #include <asm/mipsregs.h>
  26 #include <asm/prom.h>
  27 #include <asm/smp-ops.h>
  28 #include <asm/time.h>
  29 #include <asm/traps.h>
  30
  31 #define RELO_NORMAL_VEC         BIT(18)
  32
  33 #define REG_BCM6328_OTP         ((void __iomem *)CKSEG1ADDR(0x1000062c))
  34 #define BCM6328_TP1_DISABLED    BIT(9)
  35
  36 static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;
  37
  38 struct bmips_quirk {
  39         const char              *compatible;
  40         void                    (*quirk_fn)(void);
  41 };
  42
  43 static void kbase_setup(void)
  44 {
  45         __raw_writel(kbase | RELO_NORMAL_VEC,
  46                      BMIPS_GET_CBR() + BMIPS_RELO_VECTOR_CONTROL_1);
  47         ebase = kbase;
  48 }
  49
  50 static void bcm3384_viper_quirks(void)
  51 {
  52         /*
  53          * Some experimental CM boxes are set up to let CM own the Viper TP0
  54          * and let Linux own TP1.  This requires moving the kernel
  55          * load address to a non-conflicting region (e.g. via
  56          * CONFIG_PHYSICAL_START) and supplying an alternate DTB.
  57          * If we detect this condition, we need to move the MIPS exception
  58          * vectors up to an area that we own.
  59          *
  60          * This is distinct from the OTHER special case mentioned in
  61          * smp-bmips.c (boot on TP1, but enable SMP, then TP0 becomes our
  62          * logical CPU#1).  For the Viper TP1 case, SMP is off limits.
  63          *
  64          * Also note that many BMIPS435x CPUs do not have a
  65          * BMIPS_RELO_VECTOR_CONTROL_1 register, so it isn't safe to just
  66          * write VMLINUX_LOAD_ADDRESS into that register on every SoC.
  67          */
  68         board_ebase_setup = &kbase_setup;
  69         bmips_smp_enabled = 0;
  70 }
  71
  72 static void bcm63xx_fixup_cpu1(void)
  73 {
  74         /*
  75          * The bootloader has set up the CPU1 reset vector at
  76          * 0xa000_0200.
  77          * This conflicts with the special interrupt vector (IV).
  78          * The bootloader has also set up CPU1 to respond to the wrong
  79          * IPI interrupt.
  80          * Here we will start up CPU1 in the background and ask it to
  81          * reconfigure itself then go back to sleep.
  82          */
  83         memcpy((void *)0xa0000200, &bmips_smp_movevec, 0x20);
  84         __sync();
  85         set_c0_cause(C_SW0);
  86         cpumask_set_cpu(1, &bmips_booted_mask);
  87 }
  88
  89 static void bcm6328_quirks(void)
  90 {
  91         /* Check CPU1 status in OTP (it is usually disabled) */
  92         if (__raw_readl(REG_BCM6328_OTP) & BCM6328_TP1_DISABLED)
  93                 bmips_smp_enabled = 0;
  94         else
  95                 bcm63xx_fixup_cpu1();
  96 }
  97
  98 static void bcm6358_quirks(void)
  99 {
 100         /*
 101          * BCM3368/BCM6358 need special handling for their shared TLB, so
 102          * disable SMP for now
 103          */
 104         bmips_smp_enabled = 0;
 105 }
 106
 107 static void bcm6368_quirks(void)
 108 {
 109         bcm63xx_fixup_cpu1();
 110 }
 111
 112 static const struct bmips_quirk bmips_quirk_list[] = {
 113         { "brcm,bcm3368",               &bcm6358_quirks                 },
 114         { "brcm,bcm3384-viper",         &bcm3384_viper_quirks           },
 115         { "brcm,bcm33843-viper",        &bcm3384_viper_quirks           },
 116         { "brcm,bcm6328",               &bcm6328_quirks                 },
 117         { "brcm,bcm6358",               &bcm6358_quirks                 },
 118         { "brcm,bcm6362",               &bcm6368_quirks                 },
 119         { "brcm,bcm6368",               &bcm6368_quirks                 },
 120         { "brcm,bcm63168",              &bcm6368_quirks                 },
 121         { "brcm,bcm63268",              &bcm6368_quirks                 },
 122         { },
 123 };
 124
 125 void __init prom_init(void)
 126 {
 127         bmips_cpu_setup();
 128         register_bmips_smp_ops();
 129 }
 130
 131 void __init prom_free_prom_memory(void)
 132 {
 133 }
 134
 135 const char *get_system_type(void)
 136 {
 137         return "Generic BMIPS kernel";
 138 }
 139
 140 void __init plat_time_init(void)
 141 {
 142         struct device_node *np;
 143         u32 freq;
 144
 145         np = of_find_node_by_name(NULL, "cpus");
 146         if (!np)
 147                 panic("missing 'cpus' DT node");
 148         if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
 149                 panic("missing 'mips-hpt-frequency' property");
 150         of_node_put(np);
 151
 152         mips_hpt_frequency = freq;
 153 }
 154
 155 void __init plat_mem_setup(void)
 156 {
 157         void *dtb;
 158         const struct bmips_quirk *q;
 159
 160         set_io_port_base(0);
 161         ioport_resource.start = 0;
 162         ioport_resource.end = ~0;
 163
 164         /* intended to somewhat resemble ARM; see Documentation/arm/Booting */
 165         if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
 166                 dtb = phys_to_virt(fw_arg2);
 167         else if (fw_passed_dtb) /* UHI interface */
 168                 dtb = (void *)fw_passed_dtb;
 169         else if (__dtb_start != __dtb_end)
 170                 dtb = (void *)__dtb_start;
 171         else
 172                 panic("no dtb found");
 173
 174         __dt_setup_arch(dtb);
 175
 176         for (q = bmips_quirk_list; q->quirk_fn; q++) {
 177                 if (of_flat_dt_is_compatible(of_get_flat_dt_root(),
 178                                              q->compatible)) {
 179                         q->quirk_fn();
 180                 }
 181         }
 182 }
 183
 184 void __init device_tree_init(void)
 185 {
 186         struct device_node *np;
 187
 188         unflatten_and_copy_device_tree();
 189
 190         /* Disable SMP boot unless both CPUs are listed in DT and !disabled */
 191         np = of_find_node_by_name(NULL, "cpus");
 192         if (np && of_get_available_child_count(np) <= 1)
 193                 bmips_smp_enabled = 0;
 194         of_node_put(np);
 195 }
 196
 197 int __init plat_of_setup(void)
 198 {
 199         return __dt_register_buses("simple-bus", NULL);
 200 }
 201
 202 arch_initcall(plat_of_setup);
 203
 204 static int __init plat_dev_init(void)
 205 {
 206         of_clk_init(NULL);
 207         return 0;
 208 }
 209
 210 device_initcall(plat_dev_init);