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[deliverable/linux.git] / arch / mips / include / asm / kvm_host.h
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 * Authors: Sanjay Lal <sanjayl@kymasys.com>
8 */
9
10 #ifndef __MIPS_KVM_HOST_H__
11 #define __MIPS_KVM_HOST_H__
12
13 #include <linux/mutex.h>
14 #include <linux/hrtimer.h>
15 #include <linux/interrupt.h>
16 #include <linux/types.h>
17 #include <linux/kvm.h>
18 #include <linux/kvm_types.h>
19 #include <linux/threads.h>
20 #include <linux/spinlock.h>
21
22 #include <asm/inst.h>
23 #include <asm/mipsregs.h>
24
25 /* MIPS KVM register ids */
26 #define MIPS_CP0_32(_R, _S) \
27 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
28
29 #define MIPS_CP0_64(_R, _S) \
30 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
31
32 #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
33 #define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0)
34 #define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0)
35 #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
36 #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
37 #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
38 #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)
39 #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
40 #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
41 #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
42 #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
43 #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
44 #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
45 #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
46 #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
47 #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)
48 #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0)
49 #define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1)
50 #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)
51 #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1)
52 #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)
53 #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3)
54 #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4)
55 #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5)
56 #define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7)
57 #define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0)
58 #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
59 #define KVM_REG_MIPS_CP0_KSCRATCH1 MIPS_CP0_64(31, 2)
60 #define KVM_REG_MIPS_CP0_KSCRATCH2 MIPS_CP0_64(31, 3)
61 #define KVM_REG_MIPS_CP0_KSCRATCH3 MIPS_CP0_64(31, 4)
62 #define KVM_REG_MIPS_CP0_KSCRATCH4 MIPS_CP0_64(31, 5)
63 #define KVM_REG_MIPS_CP0_KSCRATCH5 MIPS_CP0_64(31, 6)
64 #define KVM_REG_MIPS_CP0_KSCRATCH6 MIPS_CP0_64(31, 7)
65
66
67 #define KVM_MAX_VCPUS 1
68 #define KVM_USER_MEM_SLOTS 8
69 /* memory slots that does not exposed to userspace */
70 #define KVM_PRIVATE_MEM_SLOTS 0
71
72 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
73 #define KVM_HALT_POLL_NS_DEFAULT 500000
74
75
76
77 /* Special address that contains the comm page, used for reducing # of traps */
78 #define KVM_GUEST_COMMPAGE_ADDR 0x0
79
80 #define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
81 ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
82
83 #define KVM_GUEST_KUSEG 0x00000000UL
84 #define KVM_GUEST_KSEG0 0x40000000UL
85 #define KVM_GUEST_KSEG23 0x60000000UL
86 #define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0xe0000000)
87 #define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
88
89 #define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
90 #define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
91 #define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
92
93 /*
94 * Map an address to a certain kernel segment
95 */
96 #define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
97 #define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
98 #define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
99
100 #define KVM_INVALID_PAGE 0xdeadbeef
101 #define KVM_INVALID_INST 0xdeadbeef
102 #define KVM_INVALID_ADDR 0xdeadbeef
103
104 extern atomic_t kvm_mips_instance;
105
106 struct kvm_vm_stat {
107 u32 remote_tlb_flush;
108 };
109
110 struct kvm_vcpu_stat {
111 u32 wait_exits;
112 u32 cache_exits;
113 u32 signal_exits;
114 u32 int_exits;
115 u32 cop_unusable_exits;
116 u32 tlbmod_exits;
117 u32 tlbmiss_ld_exits;
118 u32 tlbmiss_st_exits;
119 u32 addrerr_st_exits;
120 u32 addrerr_ld_exits;
121 u32 syscall_exits;
122 u32 resvd_inst_exits;
123 u32 break_inst_exits;
124 u32 trap_inst_exits;
125 u32 msa_fpe_exits;
126 u32 fpe_exits;
127 u32 msa_disabled_exits;
128 u32 flush_dcache_exits;
129 u32 halt_successful_poll;
130 u32 halt_attempted_poll;
131 u32 halt_poll_invalid;
132 u32 halt_wakeup;
133 };
134
135 struct kvm_arch_memory_slot {
136 };
137
138 struct kvm_arch {
139 /* Guest GVA->HPA page table */
140 unsigned long *guest_pmap;
141 unsigned long guest_pmap_npages;
142
143 /* Wired host TLB used for the commpage */
144 int commpage_tlb;
145 };
146
147 #define N_MIPS_COPROC_REGS 32
148 #define N_MIPS_COPROC_SEL 8
149
150 struct mips_coproc {
151 unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
152 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
153 unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
154 #endif
155 };
156
157 /*
158 * Coprocessor 0 register names
159 */
160 #define MIPS_CP0_TLB_INDEX 0
161 #define MIPS_CP0_TLB_RANDOM 1
162 #define MIPS_CP0_TLB_LOW 2
163 #define MIPS_CP0_TLB_LO0 2
164 #define MIPS_CP0_TLB_LO1 3
165 #define MIPS_CP0_TLB_CONTEXT 4
166 #define MIPS_CP0_TLB_PG_MASK 5
167 #define MIPS_CP0_TLB_WIRED 6
168 #define MIPS_CP0_HWRENA 7
169 #define MIPS_CP0_BAD_VADDR 8
170 #define MIPS_CP0_COUNT 9
171 #define MIPS_CP0_TLB_HI 10
172 #define MIPS_CP0_COMPARE 11
173 #define MIPS_CP0_STATUS 12
174 #define MIPS_CP0_CAUSE 13
175 #define MIPS_CP0_EXC_PC 14
176 #define MIPS_CP0_PRID 15
177 #define MIPS_CP0_CONFIG 16
178 #define MIPS_CP0_LLADDR 17
179 #define MIPS_CP0_WATCH_LO 18
180 #define MIPS_CP0_WATCH_HI 19
181 #define MIPS_CP0_TLB_XCONTEXT 20
182 #define MIPS_CP0_ECC 26
183 #define MIPS_CP0_CACHE_ERR 27
184 #define MIPS_CP0_TAG_LO 28
185 #define MIPS_CP0_TAG_HI 29
186 #define MIPS_CP0_ERROR_PC 30
187 #define MIPS_CP0_DEBUG 23
188 #define MIPS_CP0_DEPC 24
189 #define MIPS_CP0_PERFCNT 25
190 #define MIPS_CP0_ERRCTL 26
191 #define MIPS_CP0_DATA_LO 28
192 #define MIPS_CP0_DATA_HI 29
193 #define MIPS_CP0_DESAVE 31
194
195 #define MIPS_CP0_CONFIG_SEL 0
196 #define MIPS_CP0_CONFIG1_SEL 1
197 #define MIPS_CP0_CONFIG2_SEL 2
198 #define MIPS_CP0_CONFIG3_SEL 3
199 #define MIPS_CP0_CONFIG4_SEL 4
200 #define MIPS_CP0_CONFIG5_SEL 5
201
202 /* Config0 register bits */
203 #define CP0C0_M 31
204 #define CP0C0_K23 28
205 #define CP0C0_KU 25
206 #define CP0C0_MDU 20
207 #define CP0C0_MM 17
208 #define CP0C0_BM 16
209 #define CP0C0_BE 15
210 #define CP0C0_AT 13
211 #define CP0C0_AR 10
212 #define CP0C0_MT 7
213 #define CP0C0_VI 3
214 #define CP0C0_K0 0
215
216 /* Config1 register bits */
217 #define CP0C1_M 31
218 #define CP0C1_MMU 25
219 #define CP0C1_IS 22
220 #define CP0C1_IL 19
221 #define CP0C1_IA 16
222 #define CP0C1_DS 13
223 #define CP0C1_DL 10
224 #define CP0C1_DA 7
225 #define CP0C1_C2 6
226 #define CP0C1_MD 5
227 #define CP0C1_PC 4
228 #define CP0C1_WR 3
229 #define CP0C1_CA 2
230 #define CP0C1_EP 1
231 #define CP0C1_FP 0
232
233 /* Config2 Register bits */
234 #define CP0C2_M 31
235 #define CP0C2_TU 28
236 #define CP0C2_TS 24
237 #define CP0C2_TL 20
238 #define CP0C2_TA 16
239 #define CP0C2_SU 12
240 #define CP0C2_SS 8
241 #define CP0C2_SL 4
242 #define CP0C2_SA 0
243
244 /* Config3 Register bits */
245 #define CP0C3_M 31
246 #define CP0C3_ISA_ON_EXC 16
247 #define CP0C3_ULRI 13
248 #define CP0C3_DSPP 10
249 #define CP0C3_LPA 7
250 #define CP0C3_VEIC 6
251 #define CP0C3_VInt 5
252 #define CP0C3_SP 4
253 #define CP0C3_MT 2
254 #define CP0C3_SM 1
255 #define CP0C3_TL 0
256
257 /* MMU types, the first four entries have the same layout as the
258 CP0C0_MT field. */
259 enum mips_mmu_types {
260 MMU_TYPE_NONE,
261 MMU_TYPE_R4000,
262 MMU_TYPE_RESERVED,
263 MMU_TYPE_FMT,
264 MMU_TYPE_R3000,
265 MMU_TYPE_R6000,
266 MMU_TYPE_R8000
267 };
268
269 /* Resume Flags */
270 #define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */
271 #define RESUME_FLAG_HOST (1<<1) /* Resume host? */
272
273 #define RESUME_GUEST 0
274 #define RESUME_GUEST_DR RESUME_FLAG_DR
275 #define RESUME_HOST RESUME_FLAG_HOST
276
277 enum emulation_result {
278 EMULATE_DONE, /* no further processing */
279 EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */
280 EMULATE_FAIL, /* can't emulate this instruction */
281 EMULATE_WAIT, /* WAIT instruction */
282 EMULATE_PRIV_FAIL,
283 };
284
285 #define mips3_paddr_to_tlbpfn(x) \
286 (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
287 #define mips3_tlbpfn_to_paddr(x) \
288 ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
289
290 #define MIPS3_PG_SHIFT 6
291 #define MIPS3_PG_FRAME 0x3fffffc0
292
293 #define VPN2_MASK 0xffffe000
294 #define KVM_ENTRYHI_ASID MIPS_ENTRYHI_ASID
295 #define TLB_IS_GLOBAL(x) ((x).tlb_lo[0] & (x).tlb_lo[1] & ENTRYLO_G)
296 #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
297 #define TLB_ASID(x) ((x).tlb_hi & KVM_ENTRYHI_ASID)
298 #define TLB_LO_IDX(x, va) (((va) >> PAGE_SHIFT) & 1)
299 #define TLB_IS_VALID(x, va) ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_V)
300 #define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \
301 ((y) & VPN2_MASK & ~(x).tlb_mask))
302 #define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) || \
303 TLB_ASID(x) == ((y) & KVM_ENTRYHI_ASID))
304
305 struct kvm_mips_tlb {
306 long tlb_mask;
307 long tlb_hi;
308 long tlb_lo[2];
309 };
310
311 #define KVM_MIPS_AUX_FPU 0x1
312 #define KVM_MIPS_AUX_MSA 0x2
313
314 #define KVM_MIPS_GUEST_TLB_SIZE 64
315 struct kvm_vcpu_arch {
316 void *guest_ebase;
317 int (*vcpu_run)(struct kvm_run *run, struct kvm_vcpu *vcpu);
318 unsigned long host_stack;
319 unsigned long host_gp;
320
321 /* Host CP0 registers used when handling exits from guest */
322 unsigned long host_cp0_badvaddr;
323 unsigned long host_cp0_epc;
324 u32 host_cp0_cause;
325
326 /* GPRS */
327 unsigned long gprs[32];
328 unsigned long hi;
329 unsigned long lo;
330 unsigned long pc;
331
332 /* FPU State */
333 struct mips_fpu_struct fpu;
334 /* Which auxiliary state is loaded (KVM_MIPS_AUX_*) */
335 unsigned int aux_inuse;
336
337 /* COP0 State */
338 struct mips_coproc *cop0;
339
340 /* Host KSEG0 address of the EI/DI offset */
341 void *kseg0_commpage;
342
343 u32 io_gpr; /* GPR used as IO source/target */
344
345 struct hrtimer comparecount_timer;
346 /* Count timer control KVM register */
347 u32 count_ctl;
348 /* Count bias from the raw time */
349 u32 count_bias;
350 /* Frequency of timer in Hz */
351 u32 count_hz;
352 /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */
353 s64 count_dyn_bias;
354 /* Resume time */
355 ktime_t count_resume;
356 /* Period of timer tick in ns */
357 u64 count_period;
358
359 /* Bitmask of exceptions that are pending */
360 unsigned long pending_exceptions;
361
362 /* Bitmask of pending exceptions to be cleared */
363 unsigned long pending_exceptions_clr;
364
365 u32 pending_load_cause;
366
367 /* Save/Restore the entryhi register when are are preempted/scheduled back in */
368 unsigned long preempt_entryhi;
369
370 /* S/W Based TLB for guest */
371 struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
372
373 /* Cached guest kernel/user ASIDs */
374 u32 guest_user_asid[NR_CPUS];
375 u32 guest_kernel_asid[NR_CPUS];
376 struct mm_struct guest_kernel_mm, guest_user_mm;
377
378 int last_sched_cpu;
379
380 /* WAIT executed */
381 int wait;
382
383 u8 fpu_enabled;
384 u8 msa_enabled;
385 u8 kscratch_enabled;
386 };
387
388
389 #define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0])
390 #define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
391 #define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0])
392 #define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0])
393 #define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
394 #define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
395 #define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
396 #define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val))
397 #define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
398 #define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
399 #define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0])
400 #define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
401 #define kvm_read_c0_guest_hwrena(cop0) (cop0->reg[MIPS_CP0_HWRENA][0])
402 #define kvm_write_c0_guest_hwrena(cop0, val) (cop0->reg[MIPS_CP0_HWRENA][0] = (val))
403 #define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0])
404 #define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
405 #define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0])
406 #define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val))
407 #define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0])
408 #define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
409 #define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0])
410 #define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
411 #define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0])
412 #define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val))
413 #define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1])
414 #define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val))
415 #define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0])
416 #define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
417 #define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0])
418 #define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
419 #define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0])
420 #define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val))
421 #define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1])
422 #define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val))
423 #define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0])
424 #define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1])
425 #define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2])
426 #define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3])
427 #define kvm_read_c0_guest_config4(cop0) (cop0->reg[MIPS_CP0_CONFIG][4])
428 #define kvm_read_c0_guest_config5(cop0) (cop0->reg[MIPS_CP0_CONFIG][5])
429 #define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7])
430 #define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
431 #define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
432 #define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
433 #define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
434 #define kvm_write_c0_guest_config4(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][4] = (val))
435 #define kvm_write_c0_guest_config5(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][5] = (val))
436 #define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
437 #define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0])
438 #define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
439 #define kvm_read_c0_guest_kscratch1(cop0) (cop0->reg[MIPS_CP0_DESAVE][2])
440 #define kvm_read_c0_guest_kscratch2(cop0) (cop0->reg[MIPS_CP0_DESAVE][3])
441 #define kvm_read_c0_guest_kscratch3(cop0) (cop0->reg[MIPS_CP0_DESAVE][4])
442 #define kvm_read_c0_guest_kscratch4(cop0) (cop0->reg[MIPS_CP0_DESAVE][5])
443 #define kvm_read_c0_guest_kscratch5(cop0) (cop0->reg[MIPS_CP0_DESAVE][6])
444 #define kvm_read_c0_guest_kscratch6(cop0) (cop0->reg[MIPS_CP0_DESAVE][7])
445 #define kvm_write_c0_guest_kscratch1(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][2] = (val))
446 #define kvm_write_c0_guest_kscratch2(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][3] = (val))
447 #define kvm_write_c0_guest_kscratch3(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][4] = (val))
448 #define kvm_write_c0_guest_kscratch4(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][5] = (val))
449 #define kvm_write_c0_guest_kscratch5(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][6] = (val))
450 #define kvm_write_c0_guest_kscratch6(cop0, val) (cop0->reg[MIPS_CP0_DESAVE][7] = (val))
451
452 /*
453 * Some of the guest registers may be modified asynchronously (e.g. from a
454 * hrtimer callback in hard irq context) and therefore need stronger atomicity
455 * guarantees than other registers.
456 */
457
458 static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,
459 unsigned long val)
460 {
461 unsigned long temp;
462 do {
463 __asm__ __volatile__(
464 " .set mips3 \n"
465 " " __LL "%0, %1 \n"
466 " or %0, %2 \n"
467 " " __SC "%0, %1 \n"
468 " .set mips0 \n"
469 : "=&r" (temp), "+m" (*reg)
470 : "r" (val));
471 } while (unlikely(!temp));
472 }
473
474 static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,
475 unsigned long val)
476 {
477 unsigned long temp;
478 do {
479 __asm__ __volatile__(
480 " .set mips3 \n"
481 " " __LL "%0, %1 \n"
482 " and %0, %2 \n"
483 " " __SC "%0, %1 \n"
484 " .set mips0 \n"
485 : "=&r" (temp), "+m" (*reg)
486 : "r" (~val));
487 } while (unlikely(!temp));
488 }
489
490 static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,
491 unsigned long change,
492 unsigned long val)
493 {
494 unsigned long temp;
495 do {
496 __asm__ __volatile__(
497 " .set mips3 \n"
498 " " __LL "%0, %1 \n"
499 " and %0, %2 \n"
500 " or %0, %3 \n"
501 " " __SC "%0, %1 \n"
502 " .set mips0 \n"
503 : "=&r" (temp), "+m" (*reg)
504 : "r" (~change), "r" (val & change));
505 } while (unlikely(!temp));
506 }
507
508 #define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
509 #define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
510
511 /* Cause can be modified asynchronously from hardirq hrtimer callback */
512 #define kvm_set_c0_guest_cause(cop0, val) \
513 _kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
514 #define kvm_clear_c0_guest_cause(cop0, val) \
515 _kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
516 #define kvm_change_c0_guest_cause(cop0, change, val) \
517 _kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], \
518 change, val)
519
520 #define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val))
521 #define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
522 #define kvm_change_c0_guest_ebase(cop0, change, val) \
523 { \
524 kvm_clear_c0_guest_ebase(cop0, change); \
525 kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \
526 }
527
528 /* Helpers */
529
530 static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu)
531 {
532 return (!__builtin_constant_p(raw_cpu_has_fpu) || raw_cpu_has_fpu) &&
533 vcpu->fpu_enabled;
534 }
535
536 static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu)
537 {
538 return kvm_mips_guest_can_have_fpu(vcpu) &&
539 kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP;
540 }
541
542 static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu)
543 {
544 return (!__builtin_constant_p(cpu_has_msa) || cpu_has_msa) &&
545 vcpu->msa_enabled;
546 }
547
548 static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu)
549 {
550 return kvm_mips_guest_can_have_msa(vcpu) &&
551 kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA;
552 }
553
554 struct kvm_mips_callbacks {
555 int (*handle_cop_unusable)(struct kvm_vcpu *vcpu);
556 int (*handle_tlb_mod)(struct kvm_vcpu *vcpu);
557 int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu);
558 int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu);
559 int (*handle_addr_err_st)(struct kvm_vcpu *vcpu);
560 int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu);
561 int (*handle_syscall)(struct kvm_vcpu *vcpu);
562 int (*handle_res_inst)(struct kvm_vcpu *vcpu);
563 int (*handle_break)(struct kvm_vcpu *vcpu);
564 int (*handle_trap)(struct kvm_vcpu *vcpu);
565 int (*handle_msa_fpe)(struct kvm_vcpu *vcpu);
566 int (*handle_fpe)(struct kvm_vcpu *vcpu);
567 int (*handle_msa_disabled)(struct kvm_vcpu *vcpu);
568 int (*vm_init)(struct kvm *kvm);
569 int (*vcpu_init)(struct kvm_vcpu *vcpu);
570 int (*vcpu_setup)(struct kvm_vcpu *vcpu);
571 gpa_t (*gva_to_gpa)(gva_t gva);
572 void (*queue_timer_int)(struct kvm_vcpu *vcpu);
573 void (*dequeue_timer_int)(struct kvm_vcpu *vcpu);
574 void (*queue_io_int)(struct kvm_vcpu *vcpu,
575 struct kvm_mips_interrupt *irq);
576 void (*dequeue_io_int)(struct kvm_vcpu *vcpu,
577 struct kvm_mips_interrupt *irq);
578 int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority,
579 u32 cause);
580 int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority,
581 u32 cause);
582 unsigned long (*num_regs)(struct kvm_vcpu *vcpu);
583 int (*copy_reg_indices)(struct kvm_vcpu *vcpu, u64 __user *indices);
584 int (*get_one_reg)(struct kvm_vcpu *vcpu,
585 const struct kvm_one_reg *reg, s64 *v);
586 int (*set_one_reg)(struct kvm_vcpu *vcpu,
587 const struct kvm_one_reg *reg, s64 v);
588 int (*vcpu_get_regs)(struct kvm_vcpu *vcpu);
589 int (*vcpu_set_regs)(struct kvm_vcpu *vcpu);
590 };
591 extern struct kvm_mips_callbacks *kvm_mips_callbacks;
592 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
593
594 /* Debug: dump vcpu state */
595 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
596
597 /* Trampoline ASM routine to start running in "Guest" context */
598 extern int __kvm_mips_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu);
599
600 /* FPU/MSA context management */
601 void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu);
602 void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu);
603 void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu);
604 void __kvm_save_msa(struct kvm_vcpu_arch *vcpu);
605 void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu);
606 void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu);
607 void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu);
608 void kvm_own_fpu(struct kvm_vcpu *vcpu);
609 void kvm_own_msa(struct kvm_vcpu *vcpu);
610 void kvm_drop_fpu(struct kvm_vcpu *vcpu);
611 void kvm_lose_fpu(struct kvm_vcpu *vcpu);
612
613 /* TLB handling */
614 u32 kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
615
616 u32 kvm_get_user_asid(struct kvm_vcpu *vcpu);
617
618 u32 kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
619
620 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
621 struct kvm_vcpu *vcpu);
622
623 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
624 struct kvm_vcpu *vcpu);
625
626 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
627 struct kvm_mips_tlb *tlb);
628
629 extern enum emulation_result kvm_mips_handle_tlbmiss(u32 cause,
630 u32 *opc,
631 struct kvm_run *run,
632 struct kvm_vcpu *vcpu);
633
634 extern enum emulation_result kvm_mips_handle_tlbmod(u32 cause,
635 u32 *opc,
636 struct kvm_run *run,
637 struct kvm_vcpu *vcpu);
638
639 extern void kvm_mips_dump_host_tlbs(void);
640 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
641 extern int kvm_mips_host_tlb_write(struct kvm_vcpu *vcpu, unsigned long entryhi,
642 unsigned long entrylo0,
643 unsigned long entrylo1,
644 int flush_dcache_mask);
645 extern void kvm_mips_flush_host_tlb(int skip_kseg0);
646 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
647
648 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
649 unsigned long entryhi);
650 extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr);
651 extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu,
652 unsigned long gva);
653 extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
654 struct kvm_vcpu *vcpu);
655 extern void kvm_local_flush_tlb_all(void);
656 extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);
657 extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
658 extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
659
660 /* Emulation */
661 u32 kvm_get_inst(u32 *opc, struct kvm_vcpu *vcpu);
662 enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause);
663
664 extern enum emulation_result kvm_mips_emulate_inst(u32 cause,
665 u32 *opc,
666 struct kvm_run *run,
667 struct kvm_vcpu *vcpu);
668
669 extern enum emulation_result kvm_mips_emulate_syscall(u32 cause,
670 u32 *opc,
671 struct kvm_run *run,
672 struct kvm_vcpu *vcpu);
673
674 extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(u32 cause,
675 u32 *opc,
676 struct kvm_run *run,
677 struct kvm_vcpu *vcpu);
678
679 extern enum emulation_result kvm_mips_emulate_tlbinv_ld(u32 cause,
680 u32 *opc,
681 struct kvm_run *run,
682 struct kvm_vcpu *vcpu);
683
684 extern enum emulation_result kvm_mips_emulate_tlbmiss_st(u32 cause,
685 u32 *opc,
686 struct kvm_run *run,
687 struct kvm_vcpu *vcpu);
688
689 extern enum emulation_result kvm_mips_emulate_tlbinv_st(u32 cause,
690 u32 *opc,
691 struct kvm_run *run,
692 struct kvm_vcpu *vcpu);
693
694 extern enum emulation_result kvm_mips_emulate_tlbmod(u32 cause,
695 u32 *opc,
696 struct kvm_run *run,
697 struct kvm_vcpu *vcpu);
698
699 extern enum emulation_result kvm_mips_emulate_fpu_exc(u32 cause,
700 u32 *opc,
701 struct kvm_run *run,
702 struct kvm_vcpu *vcpu);
703
704 extern enum emulation_result kvm_mips_handle_ri(u32 cause,
705 u32 *opc,
706 struct kvm_run *run,
707 struct kvm_vcpu *vcpu);
708
709 extern enum emulation_result kvm_mips_emulate_ri_exc(u32 cause,
710 u32 *opc,
711 struct kvm_run *run,
712 struct kvm_vcpu *vcpu);
713
714 extern enum emulation_result kvm_mips_emulate_bp_exc(u32 cause,
715 u32 *opc,
716 struct kvm_run *run,
717 struct kvm_vcpu *vcpu);
718
719 extern enum emulation_result kvm_mips_emulate_trap_exc(u32 cause,
720 u32 *opc,
721 struct kvm_run *run,
722 struct kvm_vcpu *vcpu);
723
724 extern enum emulation_result kvm_mips_emulate_msafpe_exc(u32 cause,
725 u32 *opc,
726 struct kvm_run *run,
727 struct kvm_vcpu *vcpu);
728
729 extern enum emulation_result kvm_mips_emulate_fpe_exc(u32 cause,
730 u32 *opc,
731 struct kvm_run *run,
732 struct kvm_vcpu *vcpu);
733
734 extern enum emulation_result kvm_mips_emulate_msadis_exc(u32 cause,
735 u32 *opc,
736 struct kvm_run *run,
737 struct kvm_vcpu *vcpu);
738
739 extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
740 struct kvm_run *run);
741
742 u32 kvm_mips_read_count(struct kvm_vcpu *vcpu);
743 void kvm_mips_write_count(struct kvm_vcpu *vcpu, u32 count);
744 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack);
745 void kvm_mips_init_count(struct kvm_vcpu *vcpu);
746 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl);
747 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume);
748 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz);
749 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu);
750 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu);
751 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu);
752
753 enum emulation_result kvm_mips_check_privilege(u32 cause,
754 u32 *opc,
755 struct kvm_run *run,
756 struct kvm_vcpu *vcpu);
757
758 enum emulation_result kvm_mips_emulate_cache(union mips_instruction inst,
759 u32 *opc,
760 u32 cause,
761 struct kvm_run *run,
762 struct kvm_vcpu *vcpu);
763 enum emulation_result kvm_mips_emulate_CP0(union mips_instruction inst,
764 u32 *opc,
765 u32 cause,
766 struct kvm_run *run,
767 struct kvm_vcpu *vcpu);
768 enum emulation_result kvm_mips_emulate_store(union mips_instruction inst,
769 u32 cause,
770 struct kvm_run *run,
771 struct kvm_vcpu *vcpu);
772 enum emulation_result kvm_mips_emulate_load(union mips_instruction inst,
773 u32 cause,
774 struct kvm_run *run,
775 struct kvm_vcpu *vcpu);
776
777 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu);
778 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu);
779 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu);
780 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu);
781
782 /* Dynamic binary translation */
783 extern int kvm_mips_trans_cache_index(union mips_instruction inst,
784 u32 *opc, struct kvm_vcpu *vcpu);
785 extern int kvm_mips_trans_cache_va(union mips_instruction inst, u32 *opc,
786 struct kvm_vcpu *vcpu);
787 extern int kvm_mips_trans_mfc0(union mips_instruction inst, u32 *opc,
788 struct kvm_vcpu *vcpu);
789 extern int kvm_mips_trans_mtc0(union mips_instruction inst, u32 *opc,
790 struct kvm_vcpu *vcpu);
791
792 /* Misc */
793 extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
794 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
795
796 static inline void kvm_arch_hardware_disable(void) {}
797 static inline void kvm_arch_hardware_unsetup(void) {}
798 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
799 static inline void kvm_arch_free_memslot(struct kvm *kvm,
800 struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {}
801 static inline void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) {}
802 static inline void kvm_arch_flush_shadow_all(struct kvm *kvm) {}
803 static inline void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
804 struct kvm_memory_slot *slot) {}
805 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
806 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
807 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {}
808 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {}
809 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
810
811 #endif /* __MIPS_KVM_HOST_H__ */
Linux kernel - Deliverables
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