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MIPS: KVM: Drop unused hpa0/hpa1 args from function
[deliverable/linux.git] / arch / mips / include / asm / kvm_host.h
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 * Authors: Sanjay Lal <sanjayl@kymasys.com>
8 */
9
10 #ifndef __MIPS_KVM_HOST_H__
11 #define __MIPS_KVM_HOST_H__
12
13 #include <linux/mutex.h>
14 #include <linux/hrtimer.h>
15 #include <linux/interrupt.h>
16 #include <linux/types.h>
17 #include <linux/kvm.h>
18 #include <linux/kvm_types.h>
19 #include <linux/threads.h>
20 #include <linux/spinlock.h>
21
22 /* MIPS KVM register ids */
23 #define MIPS_CP0_32(_R, _S) \
24 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
25
26 #define MIPS_CP0_64(_R, _S) \
27 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
28
29 #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
30 #define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0)
31 #define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0)
32 #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
33 #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
34 #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
35 #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)
36 #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
37 #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
38 #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
39 #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
40 #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
41 #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
42 #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
43 #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
44 #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)
45 #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0)
46 #define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1)
47 #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)
48 #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1)
49 #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)
50 #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3)
51 #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4)
52 #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5)
53 #define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7)
54 #define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0)
55 #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
56
57
58 #define KVM_MAX_VCPUS 1
59 #define KVM_USER_MEM_SLOTS 8
60 /* memory slots that does not exposed to userspace */
61 #define KVM_PRIVATE_MEM_SLOTS 0
62
63 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
64 #define KVM_HALT_POLL_NS_DEFAULT 500000
65
66
67
68 /* Special address that contains the comm page, used for reducing # of traps */
69 #define KVM_GUEST_COMMPAGE_ADDR 0x0
70
71 #define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
72 ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
73
74 #define KVM_GUEST_KUSEG 0x00000000UL
75 #define KVM_GUEST_KSEG0 0x40000000UL
76 #define KVM_GUEST_KSEG23 0x60000000UL
77 #define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0xe0000000)
78 #define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
79
80 #define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
81 #define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
82 #define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
83
84 /*
85 * Map an address to a certain kernel segment
86 */
87 #define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
88 #define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
89 #define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
90
91 #define KVM_INVALID_PAGE 0xdeadbeef
92 #define KVM_INVALID_INST 0xdeadbeef
93 #define KVM_INVALID_ADDR 0xdeadbeef
94
95 extern atomic_t kvm_mips_instance;
96
97 struct kvm_vm_stat {
98 u32 remote_tlb_flush;
99 };
100
101 struct kvm_vcpu_stat {
102 u32 wait_exits;
103 u32 cache_exits;
104 u32 signal_exits;
105 u32 int_exits;
106 u32 cop_unusable_exits;
107 u32 tlbmod_exits;
108 u32 tlbmiss_ld_exits;
109 u32 tlbmiss_st_exits;
110 u32 addrerr_st_exits;
111 u32 addrerr_ld_exits;
112 u32 syscall_exits;
113 u32 resvd_inst_exits;
114 u32 break_inst_exits;
115 u32 trap_inst_exits;
116 u32 msa_fpe_exits;
117 u32 fpe_exits;
118 u32 msa_disabled_exits;
119 u32 flush_dcache_exits;
120 u32 halt_successful_poll;
121 u32 halt_attempted_poll;
122 u32 halt_poll_invalid;
123 u32 halt_wakeup;
124 };
125
126 enum kvm_mips_exit_types {
127 WAIT_EXITS,
128 CACHE_EXITS,
129 SIGNAL_EXITS,
130 INT_EXITS,
131 COP_UNUSABLE_EXITS,
132 TLBMOD_EXITS,
133 TLBMISS_LD_EXITS,
134 TLBMISS_ST_EXITS,
135 ADDRERR_ST_EXITS,
136 ADDRERR_LD_EXITS,
137 SYSCALL_EXITS,
138 RESVD_INST_EXITS,
139 BREAK_INST_EXITS,
140 TRAP_INST_EXITS,
141 MSA_FPE_EXITS,
142 FPE_EXITS,
143 MSA_DISABLED_EXITS,
144 FLUSH_DCACHE_EXITS,
145 MAX_KVM_MIPS_EXIT_TYPES
146 };
147
148 struct kvm_arch_memory_slot {
149 };
150
151 struct kvm_arch {
152 /* Guest GVA->HPA page table */
153 unsigned long *guest_pmap;
154 unsigned long guest_pmap_npages;
155
156 /* Wired host TLB used for the commpage */
157 int commpage_tlb;
158 };
159
160 #define N_MIPS_COPROC_REGS 32
161 #define N_MIPS_COPROC_SEL 8
162
163 struct mips_coproc {
164 unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
165 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
166 unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
167 #endif
168 };
169
170 /*
171 * Coprocessor 0 register names
172 */
173 #define MIPS_CP0_TLB_INDEX 0
174 #define MIPS_CP0_TLB_RANDOM 1
175 #define MIPS_CP0_TLB_LOW 2
176 #define MIPS_CP0_TLB_LO0 2
177 #define MIPS_CP0_TLB_LO1 3
178 #define MIPS_CP0_TLB_CONTEXT 4
179 #define MIPS_CP0_TLB_PG_MASK 5
180 #define MIPS_CP0_TLB_WIRED 6
181 #define MIPS_CP0_HWRENA 7
182 #define MIPS_CP0_BAD_VADDR 8
183 #define MIPS_CP0_COUNT 9
184 #define MIPS_CP0_TLB_HI 10
185 #define MIPS_CP0_COMPARE 11
186 #define MIPS_CP0_STATUS 12
187 #define MIPS_CP0_CAUSE 13
188 #define MIPS_CP0_EXC_PC 14
189 #define MIPS_CP0_PRID 15
190 #define MIPS_CP0_CONFIG 16
191 #define MIPS_CP0_LLADDR 17
192 #define MIPS_CP0_WATCH_LO 18
193 #define MIPS_CP0_WATCH_HI 19
194 #define MIPS_CP0_TLB_XCONTEXT 20
195 #define MIPS_CP0_ECC 26
196 #define MIPS_CP0_CACHE_ERR 27
197 #define MIPS_CP0_TAG_LO 28
198 #define MIPS_CP0_TAG_HI 29
199 #define MIPS_CP0_ERROR_PC 30
200 #define MIPS_CP0_DEBUG 23
201 #define MIPS_CP0_DEPC 24
202 #define MIPS_CP0_PERFCNT 25
203 #define MIPS_CP0_ERRCTL 26
204 #define MIPS_CP0_DATA_LO 28
205 #define MIPS_CP0_DATA_HI 29
206 #define MIPS_CP0_DESAVE 31
207
208 #define MIPS_CP0_CONFIG_SEL 0
209 #define MIPS_CP0_CONFIG1_SEL 1
210 #define MIPS_CP0_CONFIG2_SEL 2
211 #define MIPS_CP0_CONFIG3_SEL 3
212 #define MIPS_CP0_CONFIG4_SEL 4
213 #define MIPS_CP0_CONFIG5_SEL 5
214
215 /* Config0 register bits */
216 #define CP0C0_M 31
217 #define CP0C0_K23 28
218 #define CP0C0_KU 25
219 #define CP0C0_MDU 20
220 #define CP0C0_MM 17
221 #define CP0C0_BM 16
222 #define CP0C0_BE 15
223 #define CP0C0_AT 13
224 #define CP0C0_AR 10
225 #define CP0C0_MT 7
226 #define CP0C0_VI 3
227 #define CP0C0_K0 0
228
229 /* Config1 register bits */
230 #define CP0C1_M 31
231 #define CP0C1_MMU 25
232 #define CP0C1_IS 22
233 #define CP0C1_IL 19
234 #define CP0C1_IA 16
235 #define CP0C1_DS 13
236 #define CP0C1_DL 10
237 #define CP0C1_DA 7
238 #define CP0C1_C2 6
239 #define CP0C1_MD 5
240 #define CP0C1_PC 4
241 #define CP0C1_WR 3
242 #define CP0C1_CA 2
243 #define CP0C1_EP 1
244 #define CP0C1_FP 0
245
246 /* Config2 Register bits */
247 #define CP0C2_M 31
248 #define CP0C2_TU 28
249 #define CP0C2_TS 24
250 #define CP0C2_TL 20
251 #define CP0C2_TA 16
252 #define CP0C2_SU 12
253 #define CP0C2_SS 8
254 #define CP0C2_SL 4
255 #define CP0C2_SA 0
256
257 /* Config3 Register bits */
258 #define CP0C3_M 31
259 #define CP0C3_ISA_ON_EXC 16
260 #define CP0C3_ULRI 13
261 #define CP0C3_DSPP 10
262 #define CP0C3_LPA 7
263 #define CP0C3_VEIC 6
264 #define CP0C3_VInt 5
265 #define CP0C3_SP 4
266 #define CP0C3_MT 2
267 #define CP0C3_SM 1
268 #define CP0C3_TL 0
269
270 /* MMU types, the first four entries have the same layout as the
271 CP0C0_MT field. */
272 enum mips_mmu_types {
273 MMU_TYPE_NONE,
274 MMU_TYPE_R4000,
275 MMU_TYPE_RESERVED,
276 MMU_TYPE_FMT,
277 MMU_TYPE_R3000,
278 MMU_TYPE_R6000,
279 MMU_TYPE_R8000
280 };
281
282 /* Resume Flags */
283 #define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */
284 #define RESUME_FLAG_HOST (1<<1) /* Resume host? */
285
286 #define RESUME_GUEST 0
287 #define RESUME_GUEST_DR RESUME_FLAG_DR
288 #define RESUME_HOST RESUME_FLAG_HOST
289
290 enum emulation_result {
291 EMULATE_DONE, /* no further processing */
292 EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */
293 EMULATE_FAIL, /* can't emulate this instruction */
294 EMULATE_WAIT, /* WAIT instruction */
295 EMULATE_PRIV_FAIL,
296 };
297
298 #define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
299 #define MIPS3_PG_V 0x00000002 /* Valid */
300 #define MIPS3_PG_NV 0x00000000
301 #define MIPS3_PG_D 0x00000004 /* Dirty */
302
303 #define mips3_paddr_to_tlbpfn(x) \
304 (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
305 #define mips3_tlbpfn_to_paddr(x) \
306 ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
307
308 #define MIPS3_PG_SHIFT 6
309 #define MIPS3_PG_FRAME 0x3fffffc0
310
311 #define VPN2_MASK 0xffffe000
312 #define KVM_ENTRYHI_ASID MIPS_ENTRYHI_ASID
313 #define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && \
314 ((x).tlb_lo1 & MIPS3_PG_G))
315 #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
316 #define TLB_ASID(x) ((x).tlb_hi & KVM_ENTRYHI_ASID)
317 #define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) \
318 ? ((x).tlb_lo1 & MIPS3_PG_V) \
319 : ((x).tlb_lo0 & MIPS3_PG_V))
320 #define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \
321 ((y) & VPN2_MASK & ~(x).tlb_mask))
322 #define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) || \
323 TLB_ASID(x) == ((y) & KVM_ENTRYHI_ASID))
324
325 struct kvm_mips_tlb {
326 long tlb_mask;
327 long tlb_hi;
328 long tlb_lo0;
329 long tlb_lo1;
330 };
331
332 #define KVM_MIPS_FPU_FPU 0x1
333 #define KVM_MIPS_FPU_MSA 0x2
334
335 #define KVM_MIPS_GUEST_TLB_SIZE 64
336 struct kvm_vcpu_arch {
337 void *host_ebase, *guest_ebase;
338 int (*vcpu_run)(struct kvm_run *run, struct kvm_vcpu *vcpu);
339 unsigned long host_stack;
340 unsigned long host_gp;
341
342 /* Host CP0 registers used when handling exits from guest */
343 unsigned long host_cp0_badvaddr;
344 unsigned long host_cp0_epc;
345 u32 host_cp0_cause;
346
347 /* GPRS */
348 unsigned long gprs[32];
349 unsigned long hi;
350 unsigned long lo;
351 unsigned long pc;
352
353 /* FPU State */
354 struct mips_fpu_struct fpu;
355 /* Which FPU state is loaded (KVM_MIPS_FPU_*) */
356 unsigned int fpu_inuse;
357
358 /* COP0 State */
359 struct mips_coproc *cop0;
360
361 /* Host KSEG0 address of the EI/DI offset */
362 void *kseg0_commpage;
363
364 u32 io_gpr; /* GPR used as IO source/target */
365
366 struct hrtimer comparecount_timer;
367 /* Count timer control KVM register */
368 u32 count_ctl;
369 /* Count bias from the raw time */
370 u32 count_bias;
371 /* Frequency of timer in Hz */
372 u32 count_hz;
373 /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */
374 s64 count_dyn_bias;
375 /* Resume time */
376 ktime_t count_resume;
377 /* Period of timer tick in ns */
378 u64 count_period;
379
380 /* Bitmask of exceptions that are pending */
381 unsigned long pending_exceptions;
382
383 /* Bitmask of pending exceptions to be cleared */
384 unsigned long pending_exceptions_clr;
385
386 u32 pending_load_cause;
387
388 /* Save/Restore the entryhi register when are are preempted/scheduled back in */
389 unsigned long preempt_entryhi;
390
391 /* S/W Based TLB for guest */
392 struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
393
394 /* Cached guest kernel/user ASIDs */
395 u32 guest_user_asid[NR_CPUS];
396 u32 guest_kernel_asid[NR_CPUS];
397 struct mm_struct guest_kernel_mm, guest_user_mm;
398
399 int last_sched_cpu;
400
401 /* WAIT executed */
402 int wait;
403
404 u8 fpu_enabled;
405 u8 msa_enabled;
406 };
407
408
409 #define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0])
410 #define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
411 #define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0])
412 #define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0])
413 #define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
414 #define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
415 #define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
416 #define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val))
417 #define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
418 #define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
419 #define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0])
420 #define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
421 #define kvm_read_c0_guest_hwrena(cop0) (cop0->reg[MIPS_CP0_HWRENA][0])
422 #define kvm_write_c0_guest_hwrena(cop0, val) (cop0->reg[MIPS_CP0_HWRENA][0] = (val))
423 #define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0])
424 #define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
425 #define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0])
426 #define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val))
427 #define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0])
428 #define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
429 #define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0])
430 #define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
431 #define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0])
432 #define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val))
433 #define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1])
434 #define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val))
435 #define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0])
436 #define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
437 #define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0])
438 #define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
439 #define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0])
440 #define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val))
441 #define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1])
442 #define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val))
443 #define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0])
444 #define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1])
445 #define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2])
446 #define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3])
447 #define kvm_read_c0_guest_config4(cop0) (cop0->reg[MIPS_CP0_CONFIG][4])
448 #define kvm_read_c0_guest_config5(cop0) (cop0->reg[MIPS_CP0_CONFIG][5])
449 #define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7])
450 #define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
451 #define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
452 #define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
453 #define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
454 #define kvm_write_c0_guest_config4(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][4] = (val))
455 #define kvm_write_c0_guest_config5(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][5] = (val))
456 #define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
457 #define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0])
458 #define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
459
460 /*
461 * Some of the guest registers may be modified asynchronously (e.g. from a
462 * hrtimer callback in hard irq context) and therefore need stronger atomicity
463 * guarantees than other registers.
464 */
465
466 static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,
467 unsigned long val)
468 {
469 unsigned long temp;
470 do {
471 __asm__ __volatile__(
472 " .set mips3 \n"
473 " " __LL "%0, %1 \n"
474 " or %0, %2 \n"
475 " " __SC "%0, %1 \n"
476 " .set mips0 \n"
477 : "=&r" (temp), "+m" (*reg)
478 : "r" (val));
479 } while (unlikely(!temp));
480 }
481
482 static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,
483 unsigned long val)
484 {
485 unsigned long temp;
486 do {
487 __asm__ __volatile__(
488 " .set mips3 \n"
489 " " __LL "%0, %1 \n"
490 " and %0, %2 \n"
491 " " __SC "%0, %1 \n"
492 " .set mips0 \n"
493 : "=&r" (temp), "+m" (*reg)
494 : "r" (~val));
495 } while (unlikely(!temp));
496 }
497
498 static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,
499 unsigned long change,
500 unsigned long val)
501 {
502 unsigned long temp;
503 do {
504 __asm__ __volatile__(
505 " .set mips3 \n"
506 " " __LL "%0, %1 \n"
507 " and %0, %2 \n"
508 " or %0, %3 \n"
509 " " __SC "%0, %1 \n"
510 " .set mips0 \n"
511 : "=&r" (temp), "+m" (*reg)
512 : "r" (~change), "r" (val & change));
513 } while (unlikely(!temp));
514 }
515
516 #define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
517 #define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
518
519 /* Cause can be modified asynchronously from hardirq hrtimer callback */
520 #define kvm_set_c0_guest_cause(cop0, val) \
521 _kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
522 #define kvm_clear_c0_guest_cause(cop0, val) \
523 _kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
524 #define kvm_change_c0_guest_cause(cop0, change, val) \
525 _kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], \
526 change, val)
527
528 #define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val))
529 #define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
530 #define kvm_change_c0_guest_ebase(cop0, change, val) \
531 { \
532 kvm_clear_c0_guest_ebase(cop0, change); \
533 kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \
534 }
535
536 /* Helpers */
537
538 static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu)
539 {
540 return (!__builtin_constant_p(cpu_has_fpu) || cpu_has_fpu) &&
541 vcpu->fpu_enabled;
542 }
543
544 static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu)
545 {
546 return kvm_mips_guest_can_have_fpu(vcpu) &&
547 kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP;
548 }
549
550 static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu)
551 {
552 return (!__builtin_constant_p(cpu_has_msa) || cpu_has_msa) &&
553 vcpu->msa_enabled;
554 }
555
556 static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu)
557 {
558 return kvm_mips_guest_can_have_msa(vcpu) &&
559 kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA;
560 }
561
562 struct kvm_mips_callbacks {
563 int (*handle_cop_unusable)(struct kvm_vcpu *vcpu);
564 int (*handle_tlb_mod)(struct kvm_vcpu *vcpu);
565 int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu);
566 int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu);
567 int (*handle_addr_err_st)(struct kvm_vcpu *vcpu);
568 int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu);
569 int (*handle_syscall)(struct kvm_vcpu *vcpu);
570 int (*handle_res_inst)(struct kvm_vcpu *vcpu);
571 int (*handle_break)(struct kvm_vcpu *vcpu);
572 int (*handle_trap)(struct kvm_vcpu *vcpu);
573 int (*handle_msa_fpe)(struct kvm_vcpu *vcpu);
574 int (*handle_fpe)(struct kvm_vcpu *vcpu);
575 int (*handle_msa_disabled)(struct kvm_vcpu *vcpu);
576 int (*vm_init)(struct kvm *kvm);
577 int (*vcpu_init)(struct kvm_vcpu *vcpu);
578 int (*vcpu_setup)(struct kvm_vcpu *vcpu);
579 gpa_t (*gva_to_gpa)(gva_t gva);
580 void (*queue_timer_int)(struct kvm_vcpu *vcpu);
581 void (*dequeue_timer_int)(struct kvm_vcpu *vcpu);
582 void (*queue_io_int)(struct kvm_vcpu *vcpu,
583 struct kvm_mips_interrupt *irq);
584 void (*dequeue_io_int)(struct kvm_vcpu *vcpu,
585 struct kvm_mips_interrupt *irq);
586 int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority,
587 u32 cause);
588 int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority,
589 u32 cause);
590 int (*get_one_reg)(struct kvm_vcpu *vcpu,
591 const struct kvm_one_reg *reg, s64 *v);
592 int (*set_one_reg)(struct kvm_vcpu *vcpu,
593 const struct kvm_one_reg *reg, s64 v);
594 int (*vcpu_get_regs)(struct kvm_vcpu *vcpu);
595 int (*vcpu_set_regs)(struct kvm_vcpu *vcpu);
596 };
597 extern struct kvm_mips_callbacks *kvm_mips_callbacks;
598 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
599
600 /* Debug: dump vcpu state */
601 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
602
603 /* Trampoline ASM routine to start running in "Guest" context */
604 extern int __kvm_mips_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu);
605
606 /* FPU/MSA context management */
607 void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu);
608 void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu);
609 void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu);
610 void __kvm_save_msa(struct kvm_vcpu_arch *vcpu);
611 void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu);
612 void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu);
613 void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu);
614 void kvm_own_fpu(struct kvm_vcpu *vcpu);
615 void kvm_own_msa(struct kvm_vcpu *vcpu);
616 void kvm_drop_fpu(struct kvm_vcpu *vcpu);
617 void kvm_lose_fpu(struct kvm_vcpu *vcpu);
618
619 /* TLB handling */
620 u32 kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
621
622 u32 kvm_get_user_asid(struct kvm_vcpu *vcpu);
623
624 u32 kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
625
626 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
627 struct kvm_vcpu *vcpu);
628
629 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
630 struct kvm_vcpu *vcpu);
631
632 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
633 struct kvm_mips_tlb *tlb);
634
635 extern enum emulation_result kvm_mips_handle_tlbmiss(u32 cause,
636 u32 *opc,
637 struct kvm_run *run,
638 struct kvm_vcpu *vcpu);
639
640 extern enum emulation_result kvm_mips_handle_tlbmod(u32 cause,
641 u32 *opc,
642 struct kvm_run *run,
643 struct kvm_vcpu *vcpu);
644
645 extern void kvm_mips_dump_host_tlbs(void);
646 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
647 extern int kvm_mips_host_tlb_write(struct kvm_vcpu *vcpu, unsigned long entryhi,
648 unsigned long entrylo0,
649 unsigned long entrylo1,
650 int flush_dcache_mask);
651 extern void kvm_mips_flush_host_tlb(int skip_kseg0);
652 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
653
654 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
655 unsigned long entryhi);
656 extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr);
657 extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu,
658 unsigned long gva);
659 extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
660 struct kvm_vcpu *vcpu);
661 extern void kvm_local_flush_tlb_all(void);
662 extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);
663 extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
664 extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
665
666 /* Emulation */
667 u32 kvm_get_inst(u32 *opc, struct kvm_vcpu *vcpu);
668 enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause);
669
670 extern enum emulation_result kvm_mips_emulate_inst(u32 cause,
671 u32 *opc,
672 struct kvm_run *run,
673 struct kvm_vcpu *vcpu);
674
675 extern enum emulation_result kvm_mips_emulate_syscall(u32 cause,
676 u32 *opc,
677 struct kvm_run *run,
678 struct kvm_vcpu *vcpu);
679
680 extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(u32 cause,
681 u32 *opc,
682 struct kvm_run *run,
683 struct kvm_vcpu *vcpu);
684
685 extern enum emulation_result kvm_mips_emulate_tlbinv_ld(u32 cause,
686 u32 *opc,
687 struct kvm_run *run,
688 struct kvm_vcpu *vcpu);
689
690 extern enum emulation_result kvm_mips_emulate_tlbmiss_st(u32 cause,
691 u32 *opc,
692 struct kvm_run *run,
693 struct kvm_vcpu *vcpu);
694
695 extern enum emulation_result kvm_mips_emulate_tlbinv_st(u32 cause,
696 u32 *opc,
697 struct kvm_run *run,
698 struct kvm_vcpu *vcpu);
699
700 extern enum emulation_result kvm_mips_emulate_tlbmod(u32 cause,
701 u32 *opc,
702 struct kvm_run *run,
703 struct kvm_vcpu *vcpu);
704
705 extern enum emulation_result kvm_mips_emulate_fpu_exc(u32 cause,
706 u32 *opc,
707 struct kvm_run *run,
708 struct kvm_vcpu *vcpu);
709
710 extern enum emulation_result kvm_mips_handle_ri(u32 cause,
711 u32 *opc,
712 struct kvm_run *run,
713 struct kvm_vcpu *vcpu);
714
715 extern enum emulation_result kvm_mips_emulate_ri_exc(u32 cause,
716 u32 *opc,
717 struct kvm_run *run,
718 struct kvm_vcpu *vcpu);
719
720 extern enum emulation_result kvm_mips_emulate_bp_exc(u32 cause,
721 u32 *opc,
722 struct kvm_run *run,
723 struct kvm_vcpu *vcpu);
724
725 extern enum emulation_result kvm_mips_emulate_trap_exc(u32 cause,
726 u32 *opc,
727 struct kvm_run *run,
728 struct kvm_vcpu *vcpu);
729
730 extern enum emulation_result kvm_mips_emulate_msafpe_exc(u32 cause,
731 u32 *opc,
732 struct kvm_run *run,
733 struct kvm_vcpu *vcpu);
734
735 extern enum emulation_result kvm_mips_emulate_fpe_exc(u32 cause,
736 u32 *opc,
737 struct kvm_run *run,
738 struct kvm_vcpu *vcpu);
739
740 extern enum emulation_result kvm_mips_emulate_msadis_exc(u32 cause,
741 u32 *opc,
742 struct kvm_run *run,
743 struct kvm_vcpu *vcpu);
744
745 extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
746 struct kvm_run *run);
747
748 u32 kvm_mips_read_count(struct kvm_vcpu *vcpu);
749 void kvm_mips_write_count(struct kvm_vcpu *vcpu, u32 count);
750 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack);
751 void kvm_mips_init_count(struct kvm_vcpu *vcpu);
752 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl);
753 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume);
754 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz);
755 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu);
756 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu);
757 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu);
758
759 enum emulation_result kvm_mips_check_privilege(u32 cause,
760 u32 *opc,
761 struct kvm_run *run,
762 struct kvm_vcpu *vcpu);
763
764 enum emulation_result kvm_mips_emulate_cache(u32 inst,
765 u32 *opc,
766 u32 cause,
767 struct kvm_run *run,
768 struct kvm_vcpu *vcpu);
769 enum emulation_result kvm_mips_emulate_CP0(u32 inst,
770 u32 *opc,
771 u32 cause,
772 struct kvm_run *run,
773 struct kvm_vcpu *vcpu);
774 enum emulation_result kvm_mips_emulate_store(u32 inst,
775 u32 cause,
776 struct kvm_run *run,
777 struct kvm_vcpu *vcpu);
778 enum emulation_result kvm_mips_emulate_load(u32 inst,
779 u32 cause,
780 struct kvm_run *run,
781 struct kvm_vcpu *vcpu);
782
783 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu);
784 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu);
785 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu);
786 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu);
787
788 /* Dynamic binary translation */
789 extern int kvm_mips_trans_cache_index(u32 inst, u32 *opc,
790 struct kvm_vcpu *vcpu);
791 extern int kvm_mips_trans_cache_va(u32 inst, u32 *opc, struct kvm_vcpu *vcpu);
792 extern int kvm_mips_trans_mfc0(u32 inst, u32 *opc, struct kvm_vcpu *vcpu);
793 extern int kvm_mips_trans_mtc0(u32 inst, u32 *opc, struct kvm_vcpu *vcpu);
794
795 /* Misc */
796 extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
797 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
798
799 static inline void kvm_arch_hardware_disable(void) {}
800 static inline void kvm_arch_hardware_unsetup(void) {}
801 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
802 static inline void kvm_arch_free_memslot(struct kvm *kvm,
803 struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {}
804 static inline void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) {}
805 static inline void kvm_arch_flush_shadow_all(struct kvm *kvm) {}
806 static inline void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
807 struct kvm_memory_slot *slot) {}
808 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
809 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
810 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {}
811 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {}
812 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
813
814 #endif /* __MIPS_KVM_HOST_H__ */
Linux kernel - Deliverables
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