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MIPS: KVM: Generalise fpu_inuse for other state
[deliverable/linux.git] / arch / mips / include / asm / kvm_host.h
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
7 * Authors: Sanjay Lal <sanjayl@kymasys.com>
8 */
9
10 #ifndef __MIPS_KVM_HOST_H__
11 #define __MIPS_KVM_HOST_H__
12
13 #include <linux/mutex.h>
14 #include <linux/hrtimer.h>
15 #include <linux/interrupt.h>
16 #include <linux/types.h>
17 #include <linux/kvm.h>
18 #include <linux/kvm_types.h>
19 #include <linux/threads.h>
20 #include <linux/spinlock.h>
21
22 #include <asm/mipsregs.h>
23
24 /* MIPS KVM register ids */
25 #define MIPS_CP0_32(_R, _S) \
26 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U32 | (8 * (_R) + (_S)))
27
28 #define MIPS_CP0_64(_R, _S) \
29 (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S)))
30
31 #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
32 #define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0)
33 #define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0)
34 #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
35 #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
36 #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
37 #define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)
38 #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
39 #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
40 #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
41 #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
42 #define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
43 #define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
44 #define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
45 #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
46 #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0)
47 #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0)
48 #define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1)
49 #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)
50 #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1)
51 #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)
52 #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3)
53 #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4)
54 #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5)
55 #define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7)
56 #define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0)
57 #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
58
59
60 #define KVM_MAX_VCPUS 1
61 #define KVM_USER_MEM_SLOTS 8
62 /* memory slots that does not exposed to userspace */
63 #define KVM_PRIVATE_MEM_SLOTS 0
64
65 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
66 #define KVM_HALT_POLL_NS_DEFAULT 500000
67
68
69
70 /* Special address that contains the comm page, used for reducing # of traps */
71 #define KVM_GUEST_COMMPAGE_ADDR 0x0
72
73 #define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
74 ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
75
76 #define KVM_GUEST_KUSEG 0x00000000UL
77 #define KVM_GUEST_KSEG0 0x40000000UL
78 #define KVM_GUEST_KSEG23 0x60000000UL
79 #define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0xe0000000)
80 #define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
81
82 #define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
83 #define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
84 #define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
85
86 /*
87 * Map an address to a certain kernel segment
88 */
89 #define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
90 #define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
91 #define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
92
93 #define KVM_INVALID_PAGE 0xdeadbeef
94 #define KVM_INVALID_INST 0xdeadbeef
95 #define KVM_INVALID_ADDR 0xdeadbeef
96
97 extern atomic_t kvm_mips_instance;
98
99 struct kvm_vm_stat {
100 u32 remote_tlb_flush;
101 };
102
103 struct kvm_vcpu_stat {
104 u32 wait_exits;
105 u32 cache_exits;
106 u32 signal_exits;
107 u32 int_exits;
108 u32 cop_unusable_exits;
109 u32 tlbmod_exits;
110 u32 tlbmiss_ld_exits;
111 u32 tlbmiss_st_exits;
112 u32 addrerr_st_exits;
113 u32 addrerr_ld_exits;
114 u32 syscall_exits;
115 u32 resvd_inst_exits;
116 u32 break_inst_exits;
117 u32 trap_inst_exits;
118 u32 msa_fpe_exits;
119 u32 fpe_exits;
120 u32 msa_disabled_exits;
121 u32 flush_dcache_exits;
122 u32 halt_successful_poll;
123 u32 halt_attempted_poll;
124 u32 halt_poll_invalid;
125 u32 halt_wakeup;
126 };
127
128 enum kvm_mips_exit_types {
129 WAIT_EXITS,
130 CACHE_EXITS,
131 SIGNAL_EXITS,
132 INT_EXITS,
133 COP_UNUSABLE_EXITS,
134 TLBMOD_EXITS,
135 TLBMISS_LD_EXITS,
136 TLBMISS_ST_EXITS,
137 ADDRERR_ST_EXITS,
138 ADDRERR_LD_EXITS,
139 SYSCALL_EXITS,
140 RESVD_INST_EXITS,
141 BREAK_INST_EXITS,
142 TRAP_INST_EXITS,
143 MSA_FPE_EXITS,
144 FPE_EXITS,
145 MSA_DISABLED_EXITS,
146 FLUSH_DCACHE_EXITS,
147 MAX_KVM_MIPS_EXIT_TYPES
148 };
149
150 struct kvm_arch_memory_slot {
151 };
152
153 struct kvm_arch {
154 /* Guest GVA->HPA page table */
155 unsigned long *guest_pmap;
156 unsigned long guest_pmap_npages;
157
158 /* Wired host TLB used for the commpage */
159 int commpage_tlb;
160 };
161
162 #define N_MIPS_COPROC_REGS 32
163 #define N_MIPS_COPROC_SEL 8
164
165 struct mips_coproc {
166 unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
167 #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
168 unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
169 #endif
170 };
171
172 /*
173 * Coprocessor 0 register names
174 */
175 #define MIPS_CP0_TLB_INDEX 0
176 #define MIPS_CP0_TLB_RANDOM 1
177 #define MIPS_CP0_TLB_LOW 2
178 #define MIPS_CP0_TLB_LO0 2
179 #define MIPS_CP0_TLB_LO1 3
180 #define MIPS_CP0_TLB_CONTEXT 4
181 #define MIPS_CP0_TLB_PG_MASK 5
182 #define MIPS_CP0_TLB_WIRED 6
183 #define MIPS_CP0_HWRENA 7
184 #define MIPS_CP0_BAD_VADDR 8
185 #define MIPS_CP0_COUNT 9
186 #define MIPS_CP0_TLB_HI 10
187 #define MIPS_CP0_COMPARE 11
188 #define MIPS_CP0_STATUS 12
189 #define MIPS_CP0_CAUSE 13
190 #define MIPS_CP0_EXC_PC 14
191 #define MIPS_CP0_PRID 15
192 #define MIPS_CP0_CONFIG 16
193 #define MIPS_CP0_LLADDR 17
194 #define MIPS_CP0_WATCH_LO 18
195 #define MIPS_CP0_WATCH_HI 19
196 #define MIPS_CP0_TLB_XCONTEXT 20
197 #define MIPS_CP0_ECC 26
198 #define MIPS_CP0_CACHE_ERR 27
199 #define MIPS_CP0_TAG_LO 28
200 #define MIPS_CP0_TAG_HI 29
201 #define MIPS_CP0_ERROR_PC 30
202 #define MIPS_CP0_DEBUG 23
203 #define MIPS_CP0_DEPC 24
204 #define MIPS_CP0_PERFCNT 25
205 #define MIPS_CP0_ERRCTL 26
206 #define MIPS_CP0_DATA_LO 28
207 #define MIPS_CP0_DATA_HI 29
208 #define MIPS_CP0_DESAVE 31
209
210 #define MIPS_CP0_CONFIG_SEL 0
211 #define MIPS_CP0_CONFIG1_SEL 1
212 #define MIPS_CP0_CONFIG2_SEL 2
213 #define MIPS_CP0_CONFIG3_SEL 3
214 #define MIPS_CP0_CONFIG4_SEL 4
215 #define MIPS_CP0_CONFIG5_SEL 5
216
217 /* Config0 register bits */
218 #define CP0C0_M 31
219 #define CP0C0_K23 28
220 #define CP0C0_KU 25
221 #define CP0C0_MDU 20
222 #define CP0C0_MM 17
223 #define CP0C0_BM 16
224 #define CP0C0_BE 15
225 #define CP0C0_AT 13
226 #define CP0C0_AR 10
227 #define CP0C0_MT 7
228 #define CP0C0_VI 3
229 #define CP0C0_K0 0
230
231 /* Config1 register bits */
232 #define CP0C1_M 31
233 #define CP0C1_MMU 25
234 #define CP0C1_IS 22
235 #define CP0C1_IL 19
236 #define CP0C1_IA 16
237 #define CP0C1_DS 13
238 #define CP0C1_DL 10
239 #define CP0C1_DA 7
240 #define CP0C1_C2 6
241 #define CP0C1_MD 5
242 #define CP0C1_PC 4
243 #define CP0C1_WR 3
244 #define CP0C1_CA 2
245 #define CP0C1_EP 1
246 #define CP0C1_FP 0
247
248 /* Config2 Register bits */
249 #define CP0C2_M 31
250 #define CP0C2_TU 28
251 #define CP0C2_TS 24
252 #define CP0C2_TL 20
253 #define CP0C2_TA 16
254 #define CP0C2_SU 12
255 #define CP0C2_SS 8
256 #define CP0C2_SL 4
257 #define CP0C2_SA 0
258
259 /* Config3 Register bits */
260 #define CP0C3_M 31
261 #define CP0C3_ISA_ON_EXC 16
262 #define CP0C3_ULRI 13
263 #define CP0C3_DSPP 10
264 #define CP0C3_LPA 7
265 #define CP0C3_VEIC 6
266 #define CP0C3_VInt 5
267 #define CP0C3_SP 4
268 #define CP0C3_MT 2
269 #define CP0C3_SM 1
270 #define CP0C3_TL 0
271
272 /* MMU types, the first four entries have the same layout as the
273 CP0C0_MT field. */
274 enum mips_mmu_types {
275 MMU_TYPE_NONE,
276 MMU_TYPE_R4000,
277 MMU_TYPE_RESERVED,
278 MMU_TYPE_FMT,
279 MMU_TYPE_R3000,
280 MMU_TYPE_R6000,
281 MMU_TYPE_R8000
282 };
283
284 /* Resume Flags */
285 #define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */
286 #define RESUME_FLAG_HOST (1<<1) /* Resume host? */
287
288 #define RESUME_GUEST 0
289 #define RESUME_GUEST_DR RESUME_FLAG_DR
290 #define RESUME_HOST RESUME_FLAG_HOST
291
292 enum emulation_result {
293 EMULATE_DONE, /* no further processing */
294 EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */
295 EMULATE_FAIL, /* can't emulate this instruction */
296 EMULATE_WAIT, /* WAIT instruction */
297 EMULATE_PRIV_FAIL,
298 };
299
300 #define mips3_paddr_to_tlbpfn(x) \
301 (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
302 #define mips3_tlbpfn_to_paddr(x) \
303 ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
304
305 #define MIPS3_PG_SHIFT 6
306 #define MIPS3_PG_FRAME 0x3fffffc0
307
308 #define VPN2_MASK 0xffffe000
309 #define KVM_ENTRYHI_ASID MIPS_ENTRYHI_ASID
310 #define TLB_IS_GLOBAL(x) ((x).tlb_lo[0] & (x).tlb_lo[1] & ENTRYLO_G)
311 #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
312 #define TLB_ASID(x) ((x).tlb_hi & KVM_ENTRYHI_ASID)
313 #define TLB_LO_IDX(x, va) (((va) >> PAGE_SHIFT) & 1)
314 #define TLB_IS_VALID(x, va) ((x).tlb_lo[TLB_LO_IDX(x, va)] & ENTRYLO_V)
315 #define TLB_HI_VPN2_HIT(x, y) ((TLB_VPN2(x) & ~(x).tlb_mask) == \
316 ((y) & VPN2_MASK & ~(x).tlb_mask))
317 #define TLB_HI_ASID_HIT(x, y) (TLB_IS_GLOBAL(x) || \
318 TLB_ASID(x) == ((y) & KVM_ENTRYHI_ASID))
319
320 struct kvm_mips_tlb {
321 long tlb_mask;
322 long tlb_hi;
323 long tlb_lo[2];
324 };
325
326 #define KVM_MIPS_AUX_FPU 0x1
327 #define KVM_MIPS_AUX_MSA 0x2
328
329 #define KVM_MIPS_GUEST_TLB_SIZE 64
330 struct kvm_vcpu_arch {
331 void *guest_ebase;
332 int (*vcpu_run)(struct kvm_run *run, struct kvm_vcpu *vcpu);
333 unsigned long host_stack;
334 unsigned long host_gp;
335
336 /* Host CP0 registers used when handling exits from guest */
337 unsigned long host_cp0_badvaddr;
338 unsigned long host_cp0_epc;
339 u32 host_cp0_cause;
340
341 /* GPRS */
342 unsigned long gprs[32];
343 unsigned long hi;
344 unsigned long lo;
345 unsigned long pc;
346
347 /* FPU State */
348 struct mips_fpu_struct fpu;
349 /* Which auxiliary state is loaded (KVM_MIPS_AUX_*) */
350 unsigned int aux_inuse;
351
352 /* COP0 State */
353 struct mips_coproc *cop0;
354
355 /* Host KSEG0 address of the EI/DI offset */
356 void *kseg0_commpage;
357
358 u32 io_gpr; /* GPR used as IO source/target */
359
360 struct hrtimer comparecount_timer;
361 /* Count timer control KVM register */
362 u32 count_ctl;
363 /* Count bias from the raw time */
364 u32 count_bias;
365 /* Frequency of timer in Hz */
366 u32 count_hz;
367 /* Dynamic nanosecond bias (multiple of count_period) to avoid overflow */
368 s64 count_dyn_bias;
369 /* Resume time */
370 ktime_t count_resume;
371 /* Period of timer tick in ns */
372 u64 count_period;
373
374 /* Bitmask of exceptions that are pending */
375 unsigned long pending_exceptions;
376
377 /* Bitmask of pending exceptions to be cleared */
378 unsigned long pending_exceptions_clr;
379
380 u32 pending_load_cause;
381
382 /* Save/Restore the entryhi register when are are preempted/scheduled back in */
383 unsigned long preempt_entryhi;
384
385 /* S/W Based TLB for guest */
386 struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
387
388 /* Cached guest kernel/user ASIDs */
389 u32 guest_user_asid[NR_CPUS];
390 u32 guest_kernel_asid[NR_CPUS];
391 struct mm_struct guest_kernel_mm, guest_user_mm;
392
393 int last_sched_cpu;
394
395 /* WAIT executed */
396 int wait;
397
398 u8 fpu_enabled;
399 u8 msa_enabled;
400 };
401
402
403 #define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0])
404 #define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
405 #define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0])
406 #define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0])
407 #define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
408 #define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
409 #define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
410 #define kvm_write_c0_guest_userlocal(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2] = (val))
411 #define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
412 #define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
413 #define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0])
414 #define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
415 #define kvm_read_c0_guest_hwrena(cop0) (cop0->reg[MIPS_CP0_HWRENA][0])
416 #define kvm_write_c0_guest_hwrena(cop0, val) (cop0->reg[MIPS_CP0_HWRENA][0] = (val))
417 #define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0])
418 #define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
419 #define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0])
420 #define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val))
421 #define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0])
422 #define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
423 #define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0])
424 #define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
425 #define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0])
426 #define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val))
427 #define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1])
428 #define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val))
429 #define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0])
430 #define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
431 #define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0])
432 #define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
433 #define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0])
434 #define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val))
435 #define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1])
436 #define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val))
437 #define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0])
438 #define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1])
439 #define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2])
440 #define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3])
441 #define kvm_read_c0_guest_config4(cop0) (cop0->reg[MIPS_CP0_CONFIG][4])
442 #define kvm_read_c0_guest_config5(cop0) (cop0->reg[MIPS_CP0_CONFIG][5])
443 #define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7])
444 #define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
445 #define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
446 #define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
447 #define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
448 #define kvm_write_c0_guest_config4(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][4] = (val))
449 #define kvm_write_c0_guest_config5(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][5] = (val))
450 #define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
451 #define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0])
452 #define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
453
454 /*
455 * Some of the guest registers may be modified asynchronously (e.g. from a
456 * hrtimer callback in hard irq context) and therefore need stronger atomicity
457 * guarantees than other registers.
458 */
459
460 static inline void _kvm_atomic_set_c0_guest_reg(unsigned long *reg,
461 unsigned long val)
462 {
463 unsigned long temp;
464 do {
465 __asm__ __volatile__(
466 " .set mips3 \n"
467 " " __LL "%0, %1 \n"
468 " or %0, %2 \n"
469 " " __SC "%0, %1 \n"
470 " .set mips0 \n"
471 : "=&r" (temp), "+m" (*reg)
472 : "r" (val));
473 } while (unlikely(!temp));
474 }
475
476 static inline void _kvm_atomic_clear_c0_guest_reg(unsigned long *reg,
477 unsigned long val)
478 {
479 unsigned long temp;
480 do {
481 __asm__ __volatile__(
482 " .set mips3 \n"
483 " " __LL "%0, %1 \n"
484 " and %0, %2 \n"
485 " " __SC "%0, %1 \n"
486 " .set mips0 \n"
487 : "=&r" (temp), "+m" (*reg)
488 : "r" (~val));
489 } while (unlikely(!temp));
490 }
491
492 static inline void _kvm_atomic_change_c0_guest_reg(unsigned long *reg,
493 unsigned long change,
494 unsigned long val)
495 {
496 unsigned long temp;
497 do {
498 __asm__ __volatile__(
499 " .set mips3 \n"
500 " " __LL "%0, %1 \n"
501 " and %0, %2 \n"
502 " or %0, %3 \n"
503 " " __SC "%0, %1 \n"
504 " .set mips0 \n"
505 : "=&r" (temp), "+m" (*reg)
506 : "r" (~change), "r" (val & change));
507 } while (unlikely(!temp));
508 }
509
510 #define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
511 #define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
512
513 /* Cause can be modified asynchronously from hardirq hrtimer callback */
514 #define kvm_set_c0_guest_cause(cop0, val) \
515 _kvm_atomic_set_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
516 #define kvm_clear_c0_guest_cause(cop0, val) \
517 _kvm_atomic_clear_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], val)
518 #define kvm_change_c0_guest_cause(cop0, change, val) \
519 _kvm_atomic_change_c0_guest_reg(&cop0->reg[MIPS_CP0_CAUSE][0], \
520 change, val)
521
522 #define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val))
523 #define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
524 #define kvm_change_c0_guest_ebase(cop0, change, val) \
525 { \
526 kvm_clear_c0_guest_ebase(cop0, change); \
527 kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \
528 }
529
530 /* Helpers */
531
532 static inline bool kvm_mips_guest_can_have_fpu(struct kvm_vcpu_arch *vcpu)
533 {
534 return (!__builtin_constant_p(cpu_has_fpu) || cpu_has_fpu) &&
535 vcpu->fpu_enabled;
536 }
537
538 static inline bool kvm_mips_guest_has_fpu(struct kvm_vcpu_arch *vcpu)
539 {
540 return kvm_mips_guest_can_have_fpu(vcpu) &&
541 kvm_read_c0_guest_config1(vcpu->cop0) & MIPS_CONF1_FP;
542 }
543
544 static inline bool kvm_mips_guest_can_have_msa(struct kvm_vcpu_arch *vcpu)
545 {
546 return (!__builtin_constant_p(cpu_has_msa) || cpu_has_msa) &&
547 vcpu->msa_enabled;
548 }
549
550 static inline bool kvm_mips_guest_has_msa(struct kvm_vcpu_arch *vcpu)
551 {
552 return kvm_mips_guest_can_have_msa(vcpu) &&
553 kvm_read_c0_guest_config3(vcpu->cop0) & MIPS_CONF3_MSA;
554 }
555
556 struct kvm_mips_callbacks {
557 int (*handle_cop_unusable)(struct kvm_vcpu *vcpu);
558 int (*handle_tlb_mod)(struct kvm_vcpu *vcpu);
559 int (*handle_tlb_ld_miss)(struct kvm_vcpu *vcpu);
560 int (*handle_tlb_st_miss)(struct kvm_vcpu *vcpu);
561 int (*handle_addr_err_st)(struct kvm_vcpu *vcpu);
562 int (*handle_addr_err_ld)(struct kvm_vcpu *vcpu);
563 int (*handle_syscall)(struct kvm_vcpu *vcpu);
564 int (*handle_res_inst)(struct kvm_vcpu *vcpu);
565 int (*handle_break)(struct kvm_vcpu *vcpu);
566 int (*handle_trap)(struct kvm_vcpu *vcpu);
567 int (*handle_msa_fpe)(struct kvm_vcpu *vcpu);
568 int (*handle_fpe)(struct kvm_vcpu *vcpu);
569 int (*handle_msa_disabled)(struct kvm_vcpu *vcpu);
570 int (*vm_init)(struct kvm *kvm);
571 int (*vcpu_init)(struct kvm_vcpu *vcpu);
572 int (*vcpu_setup)(struct kvm_vcpu *vcpu);
573 gpa_t (*gva_to_gpa)(gva_t gva);
574 void (*queue_timer_int)(struct kvm_vcpu *vcpu);
575 void (*dequeue_timer_int)(struct kvm_vcpu *vcpu);
576 void (*queue_io_int)(struct kvm_vcpu *vcpu,
577 struct kvm_mips_interrupt *irq);
578 void (*dequeue_io_int)(struct kvm_vcpu *vcpu,
579 struct kvm_mips_interrupt *irq);
580 int (*irq_deliver)(struct kvm_vcpu *vcpu, unsigned int priority,
581 u32 cause);
582 int (*irq_clear)(struct kvm_vcpu *vcpu, unsigned int priority,
583 u32 cause);
584 int (*get_one_reg)(struct kvm_vcpu *vcpu,
585 const struct kvm_one_reg *reg, s64 *v);
586 int (*set_one_reg)(struct kvm_vcpu *vcpu,
587 const struct kvm_one_reg *reg, s64 v);
588 int (*vcpu_get_regs)(struct kvm_vcpu *vcpu);
589 int (*vcpu_set_regs)(struct kvm_vcpu *vcpu);
590 };
591 extern struct kvm_mips_callbacks *kvm_mips_callbacks;
592 int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
593
594 /* Debug: dump vcpu state */
595 int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
596
597 /* Trampoline ASM routine to start running in "Guest" context */
598 extern int __kvm_mips_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu);
599
600 /* FPU/MSA context management */
601 void __kvm_save_fpu(struct kvm_vcpu_arch *vcpu);
602 void __kvm_restore_fpu(struct kvm_vcpu_arch *vcpu);
603 void __kvm_restore_fcsr(struct kvm_vcpu_arch *vcpu);
604 void __kvm_save_msa(struct kvm_vcpu_arch *vcpu);
605 void __kvm_restore_msa(struct kvm_vcpu_arch *vcpu);
606 void __kvm_restore_msa_upper(struct kvm_vcpu_arch *vcpu);
607 void __kvm_restore_msacsr(struct kvm_vcpu_arch *vcpu);
608 void kvm_own_fpu(struct kvm_vcpu *vcpu);
609 void kvm_own_msa(struct kvm_vcpu *vcpu);
610 void kvm_drop_fpu(struct kvm_vcpu *vcpu);
611 void kvm_lose_fpu(struct kvm_vcpu *vcpu);
612
613 /* TLB handling */
614 u32 kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
615
616 u32 kvm_get_user_asid(struct kvm_vcpu *vcpu);
617
618 u32 kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
619
620 extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
621 struct kvm_vcpu *vcpu);
622
623 extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
624 struct kvm_vcpu *vcpu);
625
626 extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
627 struct kvm_mips_tlb *tlb);
628
629 extern enum emulation_result kvm_mips_handle_tlbmiss(u32 cause,
630 u32 *opc,
631 struct kvm_run *run,
632 struct kvm_vcpu *vcpu);
633
634 extern enum emulation_result kvm_mips_handle_tlbmod(u32 cause,
635 u32 *opc,
636 struct kvm_run *run,
637 struct kvm_vcpu *vcpu);
638
639 extern void kvm_mips_dump_host_tlbs(void);
640 extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
641 extern int kvm_mips_host_tlb_write(struct kvm_vcpu *vcpu, unsigned long entryhi,
642 unsigned long entrylo0,
643 unsigned long entrylo1,
644 int flush_dcache_mask);
645 extern void kvm_mips_flush_host_tlb(int skip_kseg0);
646 extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
647
648 extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
649 unsigned long entryhi);
650 extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr);
651 extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu,
652 unsigned long gva);
653 extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
654 struct kvm_vcpu *vcpu);
655 extern void kvm_local_flush_tlb_all(void);
656 extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);
657 extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
658 extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
659
660 /* Emulation */
661 u32 kvm_get_inst(u32 *opc, struct kvm_vcpu *vcpu);
662 enum emulation_result update_pc(struct kvm_vcpu *vcpu, u32 cause);
663
664 extern enum emulation_result kvm_mips_emulate_inst(u32 cause,
665 u32 *opc,
666 struct kvm_run *run,
667 struct kvm_vcpu *vcpu);
668
669 extern enum emulation_result kvm_mips_emulate_syscall(u32 cause,
670 u32 *opc,
671 struct kvm_run *run,
672 struct kvm_vcpu *vcpu);
673
674 extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(u32 cause,
675 u32 *opc,
676 struct kvm_run *run,
677 struct kvm_vcpu *vcpu);
678
679 extern enum emulation_result kvm_mips_emulate_tlbinv_ld(u32 cause,
680 u32 *opc,
681 struct kvm_run *run,
682 struct kvm_vcpu *vcpu);
683
684 extern enum emulation_result kvm_mips_emulate_tlbmiss_st(u32 cause,
685 u32 *opc,
686 struct kvm_run *run,
687 struct kvm_vcpu *vcpu);
688
689 extern enum emulation_result kvm_mips_emulate_tlbinv_st(u32 cause,
690 u32 *opc,
691 struct kvm_run *run,
692 struct kvm_vcpu *vcpu);
693
694 extern enum emulation_result kvm_mips_emulate_tlbmod(u32 cause,
695 u32 *opc,
696 struct kvm_run *run,
697 struct kvm_vcpu *vcpu);
698
699 extern enum emulation_result kvm_mips_emulate_fpu_exc(u32 cause,
700 u32 *opc,
701 struct kvm_run *run,
702 struct kvm_vcpu *vcpu);
703
704 extern enum emulation_result kvm_mips_handle_ri(u32 cause,
705 u32 *opc,
706 struct kvm_run *run,
707 struct kvm_vcpu *vcpu);
708
709 extern enum emulation_result kvm_mips_emulate_ri_exc(u32 cause,
710 u32 *opc,
711 struct kvm_run *run,
712 struct kvm_vcpu *vcpu);
713
714 extern enum emulation_result kvm_mips_emulate_bp_exc(u32 cause,
715 u32 *opc,
716 struct kvm_run *run,
717 struct kvm_vcpu *vcpu);
718
719 extern enum emulation_result kvm_mips_emulate_trap_exc(u32 cause,
720 u32 *opc,
721 struct kvm_run *run,
722 struct kvm_vcpu *vcpu);
723
724 extern enum emulation_result kvm_mips_emulate_msafpe_exc(u32 cause,
725 u32 *opc,
726 struct kvm_run *run,
727 struct kvm_vcpu *vcpu);
728
729 extern enum emulation_result kvm_mips_emulate_fpe_exc(u32 cause,
730 u32 *opc,
731 struct kvm_run *run,
732 struct kvm_vcpu *vcpu);
733
734 extern enum emulation_result kvm_mips_emulate_msadis_exc(u32 cause,
735 u32 *opc,
736 struct kvm_run *run,
737 struct kvm_vcpu *vcpu);
738
739 extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
740 struct kvm_run *run);
741
742 u32 kvm_mips_read_count(struct kvm_vcpu *vcpu);
743 void kvm_mips_write_count(struct kvm_vcpu *vcpu, u32 count);
744 void kvm_mips_write_compare(struct kvm_vcpu *vcpu, u32 compare, bool ack);
745 void kvm_mips_init_count(struct kvm_vcpu *vcpu);
746 int kvm_mips_set_count_ctl(struct kvm_vcpu *vcpu, s64 count_ctl);
747 int kvm_mips_set_count_resume(struct kvm_vcpu *vcpu, s64 count_resume);
748 int kvm_mips_set_count_hz(struct kvm_vcpu *vcpu, s64 count_hz);
749 void kvm_mips_count_enable_cause(struct kvm_vcpu *vcpu);
750 void kvm_mips_count_disable_cause(struct kvm_vcpu *vcpu);
751 enum hrtimer_restart kvm_mips_count_timeout(struct kvm_vcpu *vcpu);
752
753 enum emulation_result kvm_mips_check_privilege(u32 cause,
754 u32 *opc,
755 struct kvm_run *run,
756 struct kvm_vcpu *vcpu);
757
758 enum emulation_result kvm_mips_emulate_cache(u32 inst,
759 u32 *opc,
760 u32 cause,
761 struct kvm_run *run,
762 struct kvm_vcpu *vcpu);
763 enum emulation_result kvm_mips_emulate_CP0(u32 inst,
764 u32 *opc,
765 u32 cause,
766 struct kvm_run *run,
767 struct kvm_vcpu *vcpu);
768 enum emulation_result kvm_mips_emulate_store(u32 inst,
769 u32 cause,
770 struct kvm_run *run,
771 struct kvm_vcpu *vcpu);
772 enum emulation_result kvm_mips_emulate_load(u32 inst,
773 u32 cause,
774 struct kvm_run *run,
775 struct kvm_vcpu *vcpu);
776
777 unsigned int kvm_mips_config1_wrmask(struct kvm_vcpu *vcpu);
778 unsigned int kvm_mips_config3_wrmask(struct kvm_vcpu *vcpu);
779 unsigned int kvm_mips_config4_wrmask(struct kvm_vcpu *vcpu);
780 unsigned int kvm_mips_config5_wrmask(struct kvm_vcpu *vcpu);
781
782 /* Dynamic binary translation */
783 extern int kvm_mips_trans_cache_index(u32 inst, u32 *opc,
784 struct kvm_vcpu *vcpu);
785 extern int kvm_mips_trans_cache_va(u32 inst, u32 *opc, struct kvm_vcpu *vcpu);
786 extern int kvm_mips_trans_mfc0(u32 inst, u32 *opc, struct kvm_vcpu *vcpu);
787 extern int kvm_mips_trans_mtc0(u32 inst, u32 *opc, struct kvm_vcpu *vcpu);
788
789 /* Misc */
790 extern void kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
791 extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
792
793 static inline void kvm_arch_hardware_disable(void) {}
794 static inline void kvm_arch_hardware_unsetup(void) {}
795 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
796 static inline void kvm_arch_free_memslot(struct kvm *kvm,
797 struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {}
798 static inline void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots) {}
799 static inline void kvm_arch_flush_shadow_all(struct kvm *kvm) {}
800 static inline void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
801 struct kvm_memory_slot *slot) {}
802 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
803 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
804 static inline void kvm_arch_vcpu_blocking(struct kvm_vcpu *vcpu) {}
805 static inline void kvm_arch_vcpu_unblocking(struct kvm_vcpu *vcpu) {}
806 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
807
808 #endif /* __MIPS_KVM_HOST_H__ */
Linux kernel - Deliverables
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