97b313882678084857129b811cea812a723c6a3a
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 2002 by Ralf Baechle
7 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
8 * Copyright (C) 2002 Maciej W. Rozycki
10 #ifndef _ASM_PGTABLE_BITS_H
11 #define _ASM_PGTABLE_BITS_H
15 * Note that we shift the lower 32bits of each EntryLo[01] entry
16 * 6 bits to the left. That way we can convert the PFN into the
17 * physical address by a single 'and' operation and gain 6 additional
18 * bits for storing information which isn't present in a normal
21 * Similar to the Alpha port, we need to keep track of the ref
22 * and mod bits in software. We have a software "yeah you can read
23 * from this page" bit, and a hardware one which actually lets the
24 * process read from the page. On the same token we have a software
25 * writable bit and the real hardware one which actually lets the
26 * process write to the page, this keeps a mod bit via the hardware
29 * Certain revisions of the R4000 and R5000 have a bug where if a
30 * certain sequence occurs in the last 3 instructions of an executable
31 * page, and the following page is not mapped, the cpu can do
32 * unpredictable things. The code (when it is written) to deal with
33 * this problem will be in the update_mmu_cache() code for the r4k.
35 #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32)
38 * The following bits are implemented by the TLB hardware
40 #define _PAGE_NO_EXEC_SHIFT 0
41 #define _PAGE_NO_EXEC (1 << _PAGE_NO_EXEC_SHIFT)
42 #define _PAGE_NO_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1)
43 #define _PAGE_NO_READ (1 << _PAGE_NO_READ_SHIFT)
44 #define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
45 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
46 #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
47 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
48 #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
49 #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
50 #define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1)
51 #define _CACHE_MASK (7 << _CACHE_SHIFT)
54 * The following bits are implemented in software
56 #define _PAGE_PRESENT_SHIFT (24)
57 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
58 #define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
59 #define _PAGE_READ (1 << _PAGE_READ_SHIFT)
60 #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
61 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
62 #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
63 #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
64 #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
65 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
67 #define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
70 * Bits for extended EntryLo0/EntryLo1 registers
72 #define _PFNX_MASK 0xffffff
74 #elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
77 * The following bits are implemented in software
79 #define _PAGE_PRESENT_SHIFT (0)
80 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
81 #define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
82 #define _PAGE_READ (1 << _PAGE_READ_SHIFT)
83 #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
84 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
85 #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
86 #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
87 #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
88 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
91 * The following bits are implemented by the TLB hardware
93 #define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 4)
94 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
95 #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
96 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
97 #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
98 #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
99 #define _CACHE_UNCACHED_SHIFT (_PAGE_DIRTY_SHIFT + 1)
100 #define _CACHE_UNCACHED (1 << _CACHE_UNCACHED_SHIFT)
101 #define _CACHE_MASK _CACHE_UNCACHED
103 #define _PFN_SHIFT PAGE_SHIFT
107 * Below are the "Normal" R4K cases
111 * The following bits are implemented in software
113 #define _PAGE_PRESENT_SHIFT 0
114 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT)
115 /* R2 or later cores check for RI/XI support to determine _PAGE_READ */
116 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
117 #define _PAGE_WRITE_SHIFT (_PAGE_PRESENT_SHIFT + 1)
118 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
120 #define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1)
121 #define _PAGE_READ (1 << _PAGE_READ_SHIFT)
122 #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1)
123 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT)
125 #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1)
126 #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT)
127 #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1)
128 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT)
130 #if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
132 #define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
133 #define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT)
134 #endif /* CONFIG_64BIT && CONFIG_MIPS_HUGE_TLB_SUPPORT */
136 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
137 /* XI - page cannot be executed */
138 #ifdef _PAGE_HUGE_SHIFT
139 #define _PAGE_NO_EXEC_SHIFT (_PAGE_HUGE_SHIFT + 1)
141 #define _PAGE_NO_EXEC_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
143 #define _PAGE_NO_EXEC (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0)
145 /* RI - page cannot be read */
146 #define _PAGE_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1)
147 #define _PAGE_READ (cpu_has_rixi ? 0 : (1 << _PAGE_READ_SHIFT))
148 #define _PAGE_NO_READ_SHIFT _PAGE_READ_SHIFT
149 #define _PAGE_NO_READ (cpu_has_rixi ? (1 << _PAGE_READ_SHIFT) : 0)
150 #endif /* defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) */
152 #if defined(_PAGE_NO_READ_SHIFT)
153 #define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1)
154 #elif defined(_PAGE_HUGE_SHIFT)
155 #define _PAGE_GLOBAL_SHIFT (_PAGE_HUGE_SHIFT + 1)
157 #define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 1)
159 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT)
161 #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1)
162 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT)
163 #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1)
164 #define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT)
165 #define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1)
166 #define _CACHE_MASK (7 << _CACHE_SHIFT)
168 #define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
170 #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */
172 #ifndef _PAGE_NO_EXEC
173 #define _PAGE_NO_EXEC 0
175 #ifndef _PAGE_NO_READ
176 #define _PAGE_NO_READ 0
179 #define _PAGE_SILENT_READ _PAGE_VALID
180 #define _PAGE_SILENT_WRITE _PAGE_DIRTY
182 #define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1))
185 * The final layouts of the PTE bits are:
187 * 64-bit, R1 or earlier: CCC D V G [S H] M A W R P
188 * 32-bit, R1 or earler: CCC D V G M A W R P
189 * 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P
190 * 32-bit, R2 or later: CCC D V G RI/R XI M A W P
196 * pte_to_entrylo converts a page table entry (PTE) into a Mips
199 static inline uint64_t pte_to_entrylo(unsigned long pte_val
)
201 #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
205 sa
= 31 - _PAGE_NO_READ_SHIFT
;
207 sa
= 63 - _PAGE_NO_READ_SHIFT
;
210 * C has no way to express that this is a DSRL
211 * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily
212 * in the fast path this is done in assembly
214 return (pte_val
>> _PAGE_GLOBAL_SHIFT
) |
215 ((pte_val
& (_PAGE_NO_EXEC
| _PAGE_NO_READ
)) << sa
);
219 return pte_val
>> _PAGE_GLOBAL_SHIFT
;
226 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
228 #define _CACHE_CACHABLE_NONCOHERENT 0
229 #define _CACHE_UNCACHED_ACCELERATED _CACHE_UNCACHED
231 #elif defined(CONFIG_CPU_SB1)
233 /* No penalty for being coherent on the SB1, so just
234 use it for "noncoherent" spaces, too. Shouldn't hurt. */
236 #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
238 #elif defined(CONFIG_CPU_LOONGSON3)
240 /* Using COHERENT flag for NONCOHERENT doesn't hurt. */
242 #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */
243 #define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */
245 #elif defined(CONFIG_MACH_INGENIC)
247 /* Ingenic uses the WA bit to achieve write-combine memory writes */
248 #define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)
252 #ifndef _CACHE_CACHABLE_NO_WA
253 #define _CACHE_CACHABLE_NO_WA (0<<_CACHE_SHIFT)
255 #ifndef _CACHE_CACHABLE_WA
256 #define _CACHE_CACHABLE_WA (1<<_CACHE_SHIFT)
258 #ifndef _CACHE_UNCACHED
259 #define _CACHE_UNCACHED (2<<_CACHE_SHIFT)
261 #ifndef _CACHE_CACHABLE_NONCOHERENT
262 #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)
264 #ifndef _CACHE_CACHABLE_CE
265 #define _CACHE_CACHABLE_CE (4<<_CACHE_SHIFT)
267 #ifndef _CACHE_CACHABLE_COW
268 #define _CACHE_CACHABLE_COW (5<<_CACHE_SHIFT)
270 #ifndef _CACHE_CACHABLE_CUW
271 #define _CACHE_CACHABLE_CUW (6<<_CACHE_SHIFT)
273 #ifndef _CACHE_UNCACHED_ACCELERATED
274 #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
277 #define __READABLE (_PAGE_SILENT_READ | _PAGE_READ | _PAGE_ACCESSED)
278 #define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED)
280 #define _PAGE_CHG_MASK (_PAGE_ACCESSED | _PAGE_MODIFIED | \
281 _PFN_MASK | _CACHE_MASK)
283 #endif /* _ASM_PGTABLE_BITS_H */
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