2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
23 #include <asm/cpu-features.h>
24 #include <asm/cpu-type.h>
26 #include <asm/mipsregs.h>
27 #include <asm/mipsmtregs.h>
29 #include <asm/watch.h>
31 #include <asm/pgtable-bits.h>
32 #include <asm/spram.h>
33 #include <asm/uaccess.h>
36 * Get the FPU Implementation/Revision.
38 static inline unsigned long cpu_get_fpu_id(void)
40 unsigned long tmp
, fpu_id
;
42 tmp
= read_c0_status();
43 __enable_fpu(FPU_AS_IS
);
44 fpu_id
= read_32bit_cp1_register(CP1_REVISION
);
50 * Check if the CPU has an external FPU.
52 static inline int __cpu_has_fpu(void)
54 return (cpu_get_fpu_id() & FPIR_IMP_MASK
) != FPIR_IMP_NONE
;
57 static inline unsigned long cpu_get_msa_id(void)
59 unsigned long status
, msa_id
;
61 status
= read_c0_status();
62 __enable_fpu(FPU_64BIT
);
64 msa_id
= read_msa_ir();
66 write_c0_status(status
);
71 * Determine the FCSR mask for FPU hardware.
73 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips
*c
)
75 unsigned long sr
, mask
, fcsr
, fcsr0
, fcsr1
;
78 mask
= FPU_CSR_ALL_X
| FPU_CSR_ALL_E
| FPU_CSR_ALL_S
| FPU_CSR_RM
;
80 sr
= read_c0_status();
81 __enable_fpu(FPU_AS_IS
);
84 write_32bit_cp1_register(CP1_STATUS
, fcsr0
);
85 fcsr0
= read_32bit_cp1_register(CP1_STATUS
);
88 write_32bit_cp1_register(CP1_STATUS
, fcsr1
);
89 fcsr1
= read_32bit_cp1_register(CP1_STATUS
);
91 write_32bit_cp1_register(CP1_STATUS
, fcsr
);
95 c
->fpu_msk31
= ~(fcsr0
^ fcsr1
) & ~mask
;
99 * Set the FIR feature flags for the FPU emulator.
101 static void cpu_set_nofpu_id(struct cpuinfo_mips
*c
)
106 if (c
->isa_level
& (MIPS_CPU_ISA_M32R1
| MIPS_CPU_ISA_M64R1
|
107 MIPS_CPU_ISA_M32R2
| MIPS_CPU_ISA_M64R2
|
108 MIPS_CPU_ISA_M32R6
| MIPS_CPU_ISA_M64R6
))
109 value
|= MIPS_FPIR_D
| MIPS_FPIR_S
;
110 if (c
->isa_level
& (MIPS_CPU_ISA_M32R2
| MIPS_CPU_ISA_M64R2
|
111 MIPS_CPU_ISA_M32R6
| MIPS_CPU_ISA_M64R6
))
112 value
|= MIPS_FPIR_F64
| MIPS_FPIR_L
| MIPS_FPIR_W
;
116 /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
117 static unsigned int mips_nofpu_msk31
;
120 * Set options for FPU hardware.
122 static void cpu_set_fpu_opts(struct cpuinfo_mips
*c
)
124 c
->fpu_id
= cpu_get_fpu_id();
125 mips_nofpu_msk31
= c
->fpu_msk31
;
127 if (c
->isa_level
& (MIPS_CPU_ISA_M32R1
| MIPS_CPU_ISA_M64R1
|
128 MIPS_CPU_ISA_M32R2
| MIPS_CPU_ISA_M64R2
|
129 MIPS_CPU_ISA_M32R6
| MIPS_CPU_ISA_M64R6
)) {
130 if (c
->fpu_id
& MIPS_FPIR_3D
)
131 c
->ases
|= MIPS_ASE_MIPS3D
;
132 if (c
->fpu_id
& MIPS_FPIR_FREP
)
133 c
->options
|= MIPS_CPU_FRE
;
136 cpu_set_fpu_fcsr_mask(c
);
140 * Set options for the FPU emulator.
142 static void cpu_set_nofpu_opts(struct cpuinfo_mips
*c
)
144 c
->options
&= ~MIPS_CPU_FPU
;
145 c
->fpu_msk31
= mips_nofpu_msk31
;
150 static int mips_fpu_disabled
;
152 static int __init
fpu_disable(char *s
)
154 cpu_set_nofpu_opts(&boot_cpu_data
);
155 mips_fpu_disabled
= 1;
160 __setup("nofpu", fpu_disable
);
162 int mips_dsp_disabled
;
164 static int __init
dsp_disable(char *s
)
166 cpu_data
[0].ases
&= ~(MIPS_ASE_DSP
| MIPS_ASE_DSP2P
);
167 mips_dsp_disabled
= 1;
172 __setup("nodsp", dsp_disable
);
174 static int mips_htw_disabled
;
176 static int __init
htw_disable(char *s
)
178 mips_htw_disabled
= 1;
179 cpu_data
[0].options
&= ~MIPS_CPU_HTW
;
180 write_c0_pwctl(read_c0_pwctl() &
181 ~(1 << MIPS_PWCTL_PWEN_SHIFT
));
186 __setup("nohtw", htw_disable
);
188 static int mips_ftlb_disabled
;
189 static int mips_has_ftlb_configured
;
191 static void set_ftlb_enable(struct cpuinfo_mips
*c
, int enable
);
193 static int __init
ftlb_disable(char *s
)
195 unsigned int config4
, mmuextdef
;
198 * If the core hasn't done any FTLB configuration, there is nothing
201 if (!mips_has_ftlb_configured
)
204 /* Disable it in the boot cpu */
205 set_ftlb_enable(&cpu_data
[0], 0);
207 back_to_back_c0_hazard();
209 config4
= read_c0_config4();
211 /* Check that FTLB has been disabled */
212 mmuextdef
= config4
& MIPS_CONF4_MMUEXTDEF
;
213 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
214 if (mmuextdef
== MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT
) {
215 /* This should never happen */
216 pr_warn("FTLB could not be disabled!\n");
220 mips_ftlb_disabled
= 1;
221 mips_has_ftlb_configured
= 0;
224 * noftlb is mainly used for debug purposes so print
225 * an informative message instead of using pr_debug()
227 pr_info("FTLB has been disabled\n");
230 * Some of these bits are duplicated in the decode_config4.
231 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
232 * once FTLB has been disabled so undo what decode_config4 did.
234 cpu_data
[0].tlbsize
-= cpu_data
[0].tlbsizeftlbways
*
235 cpu_data
[0].tlbsizeftlbsets
;
236 cpu_data
[0].tlbsizeftlbsets
= 0;
237 cpu_data
[0].tlbsizeftlbways
= 0;
242 __setup("noftlb", ftlb_disable
);
245 static inline void check_errata(void)
247 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
249 switch (current_cpu_type()) {
252 * Erratum "RPS May Cause Incorrect Instruction Execution"
253 * This code only handles VPE0, any SMP/RTOS code
254 * making use of VPE1 will be responsable for that VPE.
256 if ((c
->processor_id
& PRID_REV_MASK
) <= PRID_REV_34K_V1_0_2
)
257 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS
);
264 void __init
check_bugs32(void)
270 * Probe whether cpu has config register by trying to play with
271 * alternate cache bit and see whether it matters.
272 * It's used by cpu_probe to distinguish between R3000A and R3081.
274 static inline int cpu_has_confreg(void)
276 #ifdef CONFIG_CPU_R3000
277 extern unsigned long r3k_cache_size(unsigned long);
278 unsigned long size1
, size2
;
279 unsigned long cfg
= read_c0_conf();
281 size1
= r3k_cache_size(ST0_ISC
);
282 write_c0_conf(cfg
^ R30XX_CONF_AC
);
283 size2
= r3k_cache_size(ST0_ISC
);
285 return size1
!= size2
;
291 static inline void set_elf_platform(int cpu
, const char *plat
)
294 __elf_platform
= plat
;
297 static inline void cpu_probe_vmbits(struct cpuinfo_mips
*c
)
299 #ifdef __NEED_VMBITS_PROBE
300 write_c0_entryhi(0x3fffffffffffe000ULL
);
301 back_to_back_c0_hazard();
302 c
->vmbits
= fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL
);
306 static void set_isa(struct cpuinfo_mips
*c
, unsigned int isa
)
309 case MIPS_CPU_ISA_M64R2
:
310 c
->isa_level
|= MIPS_CPU_ISA_M32R2
| MIPS_CPU_ISA_M64R2
;
311 case MIPS_CPU_ISA_M64R1
:
312 c
->isa_level
|= MIPS_CPU_ISA_M32R1
| MIPS_CPU_ISA_M64R1
;
314 c
->isa_level
|= MIPS_CPU_ISA_V
;
315 case MIPS_CPU_ISA_IV
:
316 c
->isa_level
|= MIPS_CPU_ISA_IV
;
317 case MIPS_CPU_ISA_III
:
318 c
->isa_level
|= MIPS_CPU_ISA_II
| MIPS_CPU_ISA_III
;
321 /* R6 incompatible with everything else */
322 case MIPS_CPU_ISA_M64R6
:
323 c
->isa_level
|= MIPS_CPU_ISA_M32R6
| MIPS_CPU_ISA_M64R6
;
324 case MIPS_CPU_ISA_M32R6
:
325 c
->isa_level
|= MIPS_CPU_ISA_M32R6
;
326 /* Break here so we don't add incompatible ISAs */
328 case MIPS_CPU_ISA_M32R2
:
329 c
->isa_level
|= MIPS_CPU_ISA_M32R2
;
330 case MIPS_CPU_ISA_M32R1
:
331 c
->isa_level
|= MIPS_CPU_ISA_M32R1
;
332 case MIPS_CPU_ISA_II
:
333 c
->isa_level
|= MIPS_CPU_ISA_II
;
338 static char unknown_isa
[] = KERN_ERR \
339 "Unsupported ISA type, c0.config0: %d.";
341 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips
*c
)
344 unsigned int probability
= c
->tlbsize
/ c
->tlbsizevtlb
;
347 * 0 = All TLBWR instructions go to FTLB
348 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
349 * FTLB and 1 goes to the VTLB.
350 * 2 = 7:1: As above with 7:1 ratio.
351 * 3 = 3:1: As above with 3:1 ratio.
353 * Use the linear midpoint as the probability threshold.
355 if (probability
>= 12)
357 else if (probability
>= 6)
361 * So FTLB is less than 4 times bigger than VTLB.
362 * A 3:1 ratio can still be useful though.
367 static void set_ftlb_enable(struct cpuinfo_mips
*c
, int enable
)
369 unsigned int config6
;
371 /* It's implementation dependent how the FTLB can be enabled */
372 switch (c
->cputype
) {
375 /* proAptiv & related cores use Config6 to enable the FTLB */
376 config6
= read_c0_config6();
377 /* Clear the old probability value */
378 config6
&= ~(3 << MIPS_CONF6_FTLBP_SHIFT
);
381 write_c0_config6(config6
|
382 (calculate_ftlb_probability(c
)
383 << MIPS_CONF6_FTLBP_SHIFT
)
384 | MIPS_CONF6_FTLBEN
);
387 write_c0_config6(config6
& ~MIPS_CONF6_FTLBEN
);
392 static inline unsigned int decode_config0(struct cpuinfo_mips
*c
)
394 unsigned int config0
;
397 config0
= read_c0_config();
400 * Look for Standard TLB or Dual VTLB and FTLB
402 if ((((config0
& MIPS_CONF_MT
) >> 7) == 1) ||
403 (((config0
& MIPS_CONF_MT
) >> 7) == 4))
404 c
->options
|= MIPS_CPU_TLB
;
406 isa
= (config0
& MIPS_CONF_AT
) >> 13;
409 switch ((config0
& MIPS_CONF_AR
) >> 10) {
411 set_isa(c
, MIPS_CPU_ISA_M32R1
);
414 set_isa(c
, MIPS_CPU_ISA_M32R2
);
417 set_isa(c
, MIPS_CPU_ISA_M32R6
);
424 switch ((config0
& MIPS_CONF_AR
) >> 10) {
426 set_isa(c
, MIPS_CPU_ISA_M64R1
);
429 set_isa(c
, MIPS_CPU_ISA_M64R2
);
432 set_isa(c
, MIPS_CPU_ISA_M64R6
);
442 return config0
& MIPS_CONF_M
;
445 panic(unknown_isa
, config0
);
448 static inline unsigned int decode_config1(struct cpuinfo_mips
*c
)
450 unsigned int config1
;
452 config1
= read_c0_config1();
454 if (config1
& MIPS_CONF1_MD
)
455 c
->ases
|= MIPS_ASE_MDMX
;
456 if (config1
& MIPS_CONF1_WR
)
457 c
->options
|= MIPS_CPU_WATCH
;
458 if (config1
& MIPS_CONF1_CA
)
459 c
->ases
|= MIPS_ASE_MIPS16
;
460 if (config1
& MIPS_CONF1_EP
)
461 c
->options
|= MIPS_CPU_EJTAG
;
462 if (config1
& MIPS_CONF1_FP
) {
463 c
->options
|= MIPS_CPU_FPU
;
464 c
->options
|= MIPS_CPU_32FPR
;
467 c
->tlbsize
= ((config1
& MIPS_CONF1_TLBS
) >> 25) + 1;
468 c
->tlbsizevtlb
= c
->tlbsize
;
469 c
->tlbsizeftlbsets
= 0;
472 return config1
& MIPS_CONF_M
;
475 static inline unsigned int decode_config2(struct cpuinfo_mips
*c
)
477 unsigned int config2
;
479 config2
= read_c0_config2();
481 if (config2
& MIPS_CONF2_SL
)
482 c
->scache
.flags
&= ~MIPS_CACHE_NOT_PRESENT
;
484 return config2
& MIPS_CONF_M
;
487 static inline unsigned int decode_config3(struct cpuinfo_mips
*c
)
489 unsigned int config3
;
491 config3
= read_c0_config3();
493 if (config3
& MIPS_CONF3_SM
) {
494 c
->ases
|= MIPS_ASE_SMARTMIPS
;
495 c
->options
|= MIPS_CPU_RIXI
;
497 if (config3
& MIPS_CONF3_RXI
)
498 c
->options
|= MIPS_CPU_RIXI
;
499 if (config3
& MIPS_CONF3_DSP
)
500 c
->ases
|= MIPS_ASE_DSP
;
501 if (config3
& MIPS_CONF3_DSP2P
)
502 c
->ases
|= MIPS_ASE_DSP2P
;
503 if (config3
& MIPS_CONF3_VINT
)
504 c
->options
|= MIPS_CPU_VINT
;
505 if (config3
& MIPS_CONF3_VEIC
)
506 c
->options
|= MIPS_CPU_VEIC
;
507 if (config3
& MIPS_CONF3_MT
)
508 c
->ases
|= MIPS_ASE_MIPSMT
;
509 if (config3
& MIPS_CONF3_ULRI
)
510 c
->options
|= MIPS_CPU_ULRI
;
511 if (config3
& MIPS_CONF3_ISA
)
512 c
->options
|= MIPS_CPU_MICROMIPS
;
513 if (config3
& MIPS_CONF3_VZ
)
514 c
->ases
|= MIPS_ASE_VZ
;
515 if (config3
& MIPS_CONF3_SC
)
516 c
->options
|= MIPS_CPU_SEGMENTS
;
517 if (config3
& MIPS_CONF3_MSA
)
518 c
->ases
|= MIPS_ASE_MSA
;
519 /* Only tested on 32-bit cores */
520 if ((config3
& MIPS_CONF3_PW
) && config_enabled(CONFIG_32BIT
)) {
522 c
->options
|= MIPS_CPU_HTW
;
524 if (config3
& MIPS_CONF3_CDMM
)
525 c
->options
|= MIPS_CPU_CDMM
;
527 return config3
& MIPS_CONF_M
;
530 static inline unsigned int decode_config4(struct cpuinfo_mips
*c
)
532 unsigned int config4
;
534 unsigned int mmuextdef
;
535 unsigned int ftlb_page
= MIPS_CONF4_FTLBPAGESIZE
;
537 config4
= read_c0_config4();
540 if (((config4
& MIPS_CONF4_IE
) >> 29) == 2)
541 c
->options
|= MIPS_CPU_TLBINV
;
542 mmuextdef
= config4
& MIPS_CONF4_MMUEXTDEF
;
544 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
:
545 c
->tlbsize
+= (config4
& MIPS_CONF4_MMUSIZEEXT
) * 0x40;
546 c
->tlbsizevtlb
= c
->tlbsize
;
548 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT
:
550 ((config4
& MIPS_CONF4_VTLBSIZEEXT
) >>
551 MIPS_CONF4_VTLBSIZEEXT_SHIFT
) * 0x40;
552 c
->tlbsize
= c
->tlbsizevtlb
;
553 ftlb_page
= MIPS_CONF4_VFTLBPAGESIZE
;
555 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT
:
556 if (mips_ftlb_disabled
)
558 newcf4
= (config4
& ~ftlb_page
) |
559 (page_size_ftlb(mmuextdef
) <<
560 MIPS_CONF4_FTLBPAGESIZE_SHIFT
);
561 write_c0_config4(newcf4
);
562 back_to_back_c0_hazard();
563 config4
= read_c0_config4();
564 if (config4
!= newcf4
) {
565 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
567 /* Switch FTLB off */
568 set_ftlb_enable(c
, 0);
571 c
->tlbsizeftlbsets
= 1 <<
572 ((config4
& MIPS_CONF4_FTLBSETS
) >>
573 MIPS_CONF4_FTLBSETS_SHIFT
);
574 c
->tlbsizeftlbways
= ((config4
& MIPS_CONF4_FTLBWAYS
) >>
575 MIPS_CONF4_FTLBWAYS_SHIFT
) + 2;
576 c
->tlbsize
+= c
->tlbsizeftlbways
* c
->tlbsizeftlbsets
;
577 mips_has_ftlb_configured
= 1;
582 c
->kscratch_mask
= (config4
>> 16) & 0xff;
584 return config4
& MIPS_CONF_M
;
587 static inline unsigned int decode_config5(struct cpuinfo_mips
*c
)
589 unsigned int config5
;
591 config5
= read_c0_config5();
592 config5
&= ~(MIPS_CONF5_UFR
| MIPS_CONF5_UFE
);
593 write_c0_config5(config5
);
595 if (config5
& MIPS_CONF5_EVA
)
596 c
->options
|= MIPS_CPU_EVA
;
597 if (config5
& MIPS_CONF5_MRP
)
598 c
->options
|= MIPS_CPU_MAAR
;
599 if (config5
& MIPS_CONF5_LLB
)
600 c
->options
|= MIPS_CPU_RW_LLB
;
602 if (config5
& MIPS_CONF5_MVH
)
603 c
->options
|= MIPS_CPU_XPA
;
606 return config5
& MIPS_CONF_M
;
609 static void decode_configs(struct cpuinfo_mips
*c
)
613 /* MIPS32 or MIPS64 compliant CPU. */
614 c
->options
= MIPS_CPU_4KEX
| MIPS_CPU_4K_CACHE
| MIPS_CPU_COUNTER
|
615 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
| MIPS_CPU_MCHECK
;
617 c
->scache
.flags
= MIPS_CACHE_NOT_PRESENT
;
619 /* Enable FTLB if present and not disabled */
620 set_ftlb_enable(c
, !mips_ftlb_disabled
);
622 ok
= decode_config0(c
); /* Read Config registers. */
623 BUG_ON(!ok
); /* Arch spec violation! */
625 ok
= decode_config1(c
);
627 ok
= decode_config2(c
);
629 ok
= decode_config3(c
);
631 ok
= decode_config4(c
);
633 ok
= decode_config5(c
);
635 mips_probe_watch_registers(c
);
638 /* Enable the RIXI exceptions */
639 set_c0_pagegrain(PG_IEC
);
640 back_to_back_c0_hazard();
641 /* Verify the IEC bit is set */
642 if (read_c0_pagegrain() & PG_IEC
)
643 c
->options
|= MIPS_CPU_RIXIEX
;
646 #ifndef CONFIG_MIPS_CPS
647 if (cpu_has_mips_r2_r6
) {
648 c
->core
= get_ebase_cpunum();
650 c
->core
>>= fls(core_nvpes()) - 1;
655 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
658 static inline void cpu_probe_legacy(struct cpuinfo_mips
*c
, unsigned int cpu
)
660 switch (c
->processor_id
& PRID_IMP_MASK
) {
662 c
->cputype
= CPU_R2000
;
663 __cpu_name
[cpu
] = "R2000";
664 c
->fpu_msk31
|= FPU_CSR_CONDX
| FPU_CSR_FS
;
665 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_3K_CACHE
|
668 c
->options
|= MIPS_CPU_FPU
;
672 if ((c
->processor_id
& PRID_REV_MASK
) == PRID_REV_R3000A
) {
673 if (cpu_has_confreg()) {
674 c
->cputype
= CPU_R3081E
;
675 __cpu_name
[cpu
] = "R3081";
677 c
->cputype
= CPU_R3000A
;
678 __cpu_name
[cpu
] = "R3000A";
681 c
->cputype
= CPU_R3000
;
682 __cpu_name
[cpu
] = "R3000";
684 c
->fpu_msk31
|= FPU_CSR_CONDX
| FPU_CSR_FS
;
685 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_3K_CACHE
|
688 c
->options
|= MIPS_CPU_FPU
;
692 if (read_c0_config() & CONF_SC
) {
693 if ((c
->processor_id
& PRID_REV_MASK
) >=
695 c
->cputype
= CPU_R4400PC
;
696 __cpu_name
[cpu
] = "R4400PC";
698 c
->cputype
= CPU_R4000PC
;
699 __cpu_name
[cpu
] = "R4000PC";
702 int cca
= read_c0_config() & CONF_CM_CMASK
;
706 * SC and MC versions can't be reliably told apart,
707 * but only the latter support coherent caching
708 * modes so assume the firmware has set the KSEG0
709 * coherency attribute reasonably (if uncached, we
713 case CONF_CM_CACHABLE_CE
:
714 case CONF_CM_CACHABLE_COW
:
715 case CONF_CM_CACHABLE_CUW
:
722 if ((c
->processor_id
& PRID_REV_MASK
) >=
724 c
->cputype
= mc
? CPU_R4400MC
: CPU_R4400SC
;
725 __cpu_name
[cpu
] = mc
? "R4400MC" : "R4400SC";
727 c
->cputype
= mc
? CPU_R4000MC
: CPU_R4000SC
;
728 __cpu_name
[cpu
] = mc
? "R4000MC" : "R4000SC";
732 set_isa(c
, MIPS_CPU_ISA_III
);
733 c
->fpu_msk31
|= FPU_CSR_CONDX
;
734 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
735 MIPS_CPU_WATCH
| MIPS_CPU_VCE
|
739 case PRID_IMP_VR41XX
:
740 set_isa(c
, MIPS_CPU_ISA_III
);
741 c
->fpu_msk31
|= FPU_CSR_CONDX
;
742 c
->options
= R4K_OPTS
;
744 switch (c
->processor_id
& 0xf0) {
745 case PRID_REV_VR4111
:
746 c
->cputype
= CPU_VR4111
;
747 __cpu_name
[cpu
] = "NEC VR4111";
749 case PRID_REV_VR4121
:
750 c
->cputype
= CPU_VR4121
;
751 __cpu_name
[cpu
] = "NEC VR4121";
753 case PRID_REV_VR4122
:
754 if ((c
->processor_id
& 0xf) < 0x3) {
755 c
->cputype
= CPU_VR4122
;
756 __cpu_name
[cpu
] = "NEC VR4122";
758 c
->cputype
= CPU_VR4181A
;
759 __cpu_name
[cpu
] = "NEC VR4181A";
762 case PRID_REV_VR4130
:
763 if ((c
->processor_id
& 0xf) < 0x4) {
764 c
->cputype
= CPU_VR4131
;
765 __cpu_name
[cpu
] = "NEC VR4131";
767 c
->cputype
= CPU_VR4133
;
768 c
->options
|= MIPS_CPU_LLSC
;
769 __cpu_name
[cpu
] = "NEC VR4133";
773 printk(KERN_INFO
"Unexpected CPU of NEC VR4100 series\n");
774 c
->cputype
= CPU_VR41XX
;
775 __cpu_name
[cpu
] = "NEC Vr41xx";
780 c
->cputype
= CPU_R4300
;
781 __cpu_name
[cpu
] = "R4300";
782 set_isa(c
, MIPS_CPU_ISA_III
);
783 c
->fpu_msk31
|= FPU_CSR_CONDX
;
784 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
789 c
->cputype
= CPU_R4600
;
790 __cpu_name
[cpu
] = "R4600";
791 set_isa(c
, MIPS_CPU_ISA_III
);
792 c
->fpu_msk31
|= FPU_CSR_CONDX
;
793 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
800 * This processor doesn't have an MMU, so it's not
801 * "real easy" to run Linux on it. It is left purely
802 * for documentation. Commented out because it shares
803 * it's c0_prid id number with the TX3900.
805 c
->cputype
= CPU_R4650
;
806 __cpu_name
[cpu
] = "R4650";
807 set_isa(c
, MIPS_CPU_ISA_III
);
808 c
->fpu_msk31
|= FPU_CSR_CONDX
;
809 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_LLSC
;
814 c
->fpu_msk31
|= FPU_CSR_CONDX
| FPU_CSR_FS
;
815 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_TX39_CACHE
;
817 if ((c
->processor_id
& 0xf0) == (PRID_REV_TX3927
& 0xf0)) {
818 c
->cputype
= CPU_TX3927
;
819 __cpu_name
[cpu
] = "TX3927";
822 switch (c
->processor_id
& PRID_REV_MASK
) {
823 case PRID_REV_TX3912
:
824 c
->cputype
= CPU_TX3912
;
825 __cpu_name
[cpu
] = "TX3912";
828 case PRID_REV_TX3922
:
829 c
->cputype
= CPU_TX3922
;
830 __cpu_name
[cpu
] = "TX3922";
837 c
->cputype
= CPU_R4700
;
838 __cpu_name
[cpu
] = "R4700";
839 set_isa(c
, MIPS_CPU_ISA_III
);
840 c
->fpu_msk31
|= FPU_CSR_CONDX
;
841 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
846 c
->cputype
= CPU_TX49XX
;
847 __cpu_name
[cpu
] = "R49XX";
848 set_isa(c
, MIPS_CPU_ISA_III
);
849 c
->fpu_msk31
|= FPU_CSR_CONDX
;
850 c
->options
= R4K_OPTS
| MIPS_CPU_LLSC
;
851 if (!(c
->processor_id
& 0x08))
852 c
->options
|= MIPS_CPU_FPU
| MIPS_CPU_32FPR
;
856 c
->cputype
= CPU_R5000
;
857 __cpu_name
[cpu
] = "R5000";
858 set_isa(c
, MIPS_CPU_ISA_IV
);
859 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
864 c
->cputype
= CPU_R5432
;
865 __cpu_name
[cpu
] = "R5432";
866 set_isa(c
, MIPS_CPU_ISA_IV
);
867 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
868 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
872 c
->cputype
= CPU_R5500
;
873 __cpu_name
[cpu
] = "R5500";
874 set_isa(c
, MIPS_CPU_ISA_IV
);
875 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
876 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
879 case PRID_IMP_NEVADA
:
880 c
->cputype
= CPU_NEVADA
;
881 __cpu_name
[cpu
] = "Nevada";
882 set_isa(c
, MIPS_CPU_ISA_IV
);
883 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
884 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
;
888 c
->cputype
= CPU_R6000
;
889 __cpu_name
[cpu
] = "R6000";
890 set_isa(c
, MIPS_CPU_ISA_II
);
891 c
->fpu_msk31
|= FPU_CSR_CONDX
| FPU_CSR_FS
;
892 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
896 case PRID_IMP_R6000A
:
897 c
->cputype
= CPU_R6000A
;
898 __cpu_name
[cpu
] = "R6000A";
899 set_isa(c
, MIPS_CPU_ISA_II
);
900 c
->fpu_msk31
|= FPU_CSR_CONDX
| FPU_CSR_FS
;
901 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
905 case PRID_IMP_RM7000
:
906 c
->cputype
= CPU_RM7000
;
907 __cpu_name
[cpu
] = "RM7000";
908 set_isa(c
, MIPS_CPU_ISA_IV
);
909 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
912 * Undocumented RM7000: Bit 29 in the info register of
913 * the RM7000 v2.0 indicates if the TLB has 48 or 64
916 * 29 1 => 64 entry JTLB
919 c
->tlbsize
= (read_c0_info() & (1 << 29)) ? 64 : 48;
922 c
->cputype
= CPU_R8000
;
923 __cpu_name
[cpu
] = "RM8000";
924 set_isa(c
, MIPS_CPU_ISA_IV
);
925 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4KEX
|
926 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
928 c
->tlbsize
= 384; /* has weird TLB: 3-way x 128 */
930 case PRID_IMP_R10000
:
931 c
->cputype
= CPU_R10000
;
932 __cpu_name
[cpu
] = "R10000";
933 set_isa(c
, MIPS_CPU_ISA_IV
);
934 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
935 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
936 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
940 case PRID_IMP_R12000
:
941 c
->cputype
= CPU_R12000
;
942 __cpu_name
[cpu
] = "R12000";
943 set_isa(c
, MIPS_CPU_ISA_IV
);
944 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
945 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
946 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
947 MIPS_CPU_LLSC
| MIPS_CPU_BP_GHIST
;
950 case PRID_IMP_R14000
:
951 if (((c
->processor_id
>> 4) & 0x0f) > 2) {
952 c
->cputype
= CPU_R16000
;
953 __cpu_name
[cpu
] = "R16000";
955 c
->cputype
= CPU_R14000
;
956 __cpu_name
[cpu
] = "R14000";
958 set_isa(c
, MIPS_CPU_ISA_IV
);
959 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
960 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
961 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
962 MIPS_CPU_LLSC
| MIPS_CPU_BP_GHIST
;
965 case PRID_IMP_LOONGSON_64
: /* Loongson-2/3 */
966 switch (c
->processor_id
& PRID_REV_MASK
) {
967 case PRID_REV_LOONGSON2E
:
968 c
->cputype
= CPU_LOONGSON2
;
969 __cpu_name
[cpu
] = "ICT Loongson-2";
970 set_elf_platform(cpu
, "loongson2e");
971 set_isa(c
, MIPS_CPU_ISA_III
);
972 c
->fpu_msk31
|= FPU_CSR_CONDX
;
974 case PRID_REV_LOONGSON2F
:
975 c
->cputype
= CPU_LOONGSON2
;
976 __cpu_name
[cpu
] = "ICT Loongson-2";
977 set_elf_platform(cpu
, "loongson2f");
978 set_isa(c
, MIPS_CPU_ISA_III
);
979 c
->fpu_msk31
|= FPU_CSR_CONDX
;
981 case PRID_REV_LOONGSON3A
:
982 c
->cputype
= CPU_LOONGSON3
;
983 __cpu_name
[cpu
] = "ICT Loongson-3";
984 set_elf_platform(cpu
, "loongson3a");
985 set_isa(c
, MIPS_CPU_ISA_M64R1
);
987 case PRID_REV_LOONGSON3B_R1
:
988 case PRID_REV_LOONGSON3B_R2
:
989 c
->cputype
= CPU_LOONGSON3
;
990 __cpu_name
[cpu
] = "ICT Loongson-3";
991 set_elf_platform(cpu
, "loongson3b");
992 set_isa(c
, MIPS_CPU_ISA_M64R1
);
996 c
->options
= R4K_OPTS
|
997 MIPS_CPU_FPU
| MIPS_CPU_LLSC
|
1000 c
->writecombine
= _CACHE_UNCACHED_ACCELERATED
;
1002 case PRID_IMP_LOONGSON_32
: /* Loongson-1 */
1005 c
->cputype
= CPU_LOONGSON1
;
1007 switch (c
->processor_id
& PRID_REV_MASK
) {
1008 case PRID_REV_LOONGSON1B
:
1009 __cpu_name
[cpu
] = "Loongson 1B";
1017 static inline void cpu_probe_mips(struct cpuinfo_mips
*c
, unsigned int cpu
)
1019 c
->writecombine
= _CACHE_UNCACHED_ACCELERATED
;
1020 switch (c
->processor_id
& PRID_IMP_MASK
) {
1021 case PRID_IMP_QEMU_GENERIC
:
1022 c
->writecombine
= _CACHE_UNCACHED
;
1023 c
->cputype
= CPU_QEMU_GENERIC
;
1024 __cpu_name
[cpu
] = "MIPS GENERIC QEMU";
1027 c
->cputype
= CPU_4KC
;
1028 c
->writecombine
= _CACHE_UNCACHED
;
1029 __cpu_name
[cpu
] = "MIPS 4Kc";
1032 case PRID_IMP_4KECR2
:
1033 c
->cputype
= CPU_4KEC
;
1034 c
->writecombine
= _CACHE_UNCACHED
;
1035 __cpu_name
[cpu
] = "MIPS 4KEc";
1039 c
->cputype
= CPU_4KSC
;
1040 c
->writecombine
= _CACHE_UNCACHED
;
1041 __cpu_name
[cpu
] = "MIPS 4KSc";
1044 c
->cputype
= CPU_5KC
;
1045 c
->writecombine
= _CACHE_UNCACHED
;
1046 __cpu_name
[cpu
] = "MIPS 5Kc";
1049 c
->cputype
= CPU_5KE
;
1050 c
->writecombine
= _CACHE_UNCACHED
;
1051 __cpu_name
[cpu
] = "MIPS 5KE";
1054 c
->cputype
= CPU_20KC
;
1055 c
->writecombine
= _CACHE_UNCACHED
;
1056 __cpu_name
[cpu
] = "MIPS 20Kc";
1059 c
->cputype
= CPU_24K
;
1060 c
->writecombine
= _CACHE_UNCACHED
;
1061 __cpu_name
[cpu
] = "MIPS 24Kc";
1064 c
->cputype
= CPU_24K
;
1065 c
->writecombine
= _CACHE_UNCACHED
;
1066 __cpu_name
[cpu
] = "MIPS 24KEc";
1069 c
->cputype
= CPU_25KF
;
1070 c
->writecombine
= _CACHE_UNCACHED
;
1071 __cpu_name
[cpu
] = "MIPS 25Kc";
1074 c
->cputype
= CPU_34K
;
1075 c
->writecombine
= _CACHE_UNCACHED
;
1076 __cpu_name
[cpu
] = "MIPS 34Kc";
1079 c
->cputype
= CPU_74K
;
1080 c
->writecombine
= _CACHE_UNCACHED
;
1081 __cpu_name
[cpu
] = "MIPS 74Kc";
1083 case PRID_IMP_M14KC
:
1084 c
->cputype
= CPU_M14KC
;
1085 c
->writecombine
= _CACHE_UNCACHED
;
1086 __cpu_name
[cpu
] = "MIPS M14Kc";
1088 case PRID_IMP_M14KEC
:
1089 c
->cputype
= CPU_M14KEC
;
1090 c
->writecombine
= _CACHE_UNCACHED
;
1091 __cpu_name
[cpu
] = "MIPS M14KEc";
1093 case PRID_IMP_1004K
:
1094 c
->cputype
= CPU_1004K
;
1095 c
->writecombine
= _CACHE_UNCACHED
;
1096 __cpu_name
[cpu
] = "MIPS 1004Kc";
1098 case PRID_IMP_1074K
:
1099 c
->cputype
= CPU_1074K
;
1100 c
->writecombine
= _CACHE_UNCACHED
;
1101 __cpu_name
[cpu
] = "MIPS 1074Kc";
1103 case PRID_IMP_INTERAPTIV_UP
:
1104 c
->cputype
= CPU_INTERAPTIV
;
1105 __cpu_name
[cpu
] = "MIPS interAptiv";
1107 case PRID_IMP_INTERAPTIV_MP
:
1108 c
->cputype
= CPU_INTERAPTIV
;
1109 __cpu_name
[cpu
] = "MIPS interAptiv (multi)";
1111 case PRID_IMP_PROAPTIV_UP
:
1112 c
->cputype
= CPU_PROAPTIV
;
1113 __cpu_name
[cpu
] = "MIPS proAptiv";
1115 case PRID_IMP_PROAPTIV_MP
:
1116 c
->cputype
= CPU_PROAPTIV
;
1117 __cpu_name
[cpu
] = "MIPS proAptiv (multi)";
1119 case PRID_IMP_P5600
:
1120 c
->cputype
= CPU_P5600
;
1121 __cpu_name
[cpu
] = "MIPS P5600";
1123 case PRID_IMP_I6400
:
1124 c
->cputype
= CPU_I6400
;
1125 __cpu_name
[cpu
] = "MIPS I6400";
1127 case PRID_IMP_M5150
:
1128 c
->cputype
= CPU_M5150
;
1129 __cpu_name
[cpu
] = "MIPS M5150";
1138 static inline void cpu_probe_alchemy(struct cpuinfo_mips
*c
, unsigned int cpu
)
1141 switch (c
->processor_id
& PRID_IMP_MASK
) {
1142 case PRID_IMP_AU1_REV1
:
1143 case PRID_IMP_AU1_REV2
:
1144 c
->cputype
= CPU_ALCHEMY
;
1145 switch ((c
->processor_id
>> 24) & 0xff) {
1147 __cpu_name
[cpu
] = "Au1000";
1150 __cpu_name
[cpu
] = "Au1500";
1153 __cpu_name
[cpu
] = "Au1100";
1156 __cpu_name
[cpu
] = "Au1550";
1159 __cpu_name
[cpu
] = "Au1200";
1160 if ((c
->processor_id
& PRID_REV_MASK
) == 2)
1161 __cpu_name
[cpu
] = "Au1250";
1164 __cpu_name
[cpu
] = "Au1210";
1167 __cpu_name
[cpu
] = "Au1xxx";
1174 static inline void cpu_probe_sibyte(struct cpuinfo_mips
*c
, unsigned int cpu
)
1178 c
->writecombine
= _CACHE_UNCACHED_ACCELERATED
;
1179 switch (c
->processor_id
& PRID_IMP_MASK
) {
1181 c
->cputype
= CPU_SB1
;
1182 __cpu_name
[cpu
] = "SiByte SB1";
1183 /* FPU in pass1 is known to have issues. */
1184 if ((c
->processor_id
& PRID_REV_MASK
) < 0x02)
1185 c
->options
&= ~(MIPS_CPU_FPU
| MIPS_CPU_32FPR
);
1188 c
->cputype
= CPU_SB1A
;
1189 __cpu_name
[cpu
] = "SiByte SB1A";
1194 static inline void cpu_probe_sandcraft(struct cpuinfo_mips
*c
, unsigned int cpu
)
1197 switch (c
->processor_id
& PRID_IMP_MASK
) {
1198 case PRID_IMP_SR71000
:
1199 c
->cputype
= CPU_SR71000
;
1200 __cpu_name
[cpu
] = "Sandcraft SR71000";
1207 static inline void cpu_probe_nxp(struct cpuinfo_mips
*c
, unsigned int cpu
)
1210 switch (c
->processor_id
& PRID_IMP_MASK
) {
1211 case PRID_IMP_PR4450
:
1212 c
->cputype
= CPU_PR4450
;
1213 __cpu_name
[cpu
] = "Philips PR4450";
1214 set_isa(c
, MIPS_CPU_ISA_M32R1
);
1219 static inline void cpu_probe_broadcom(struct cpuinfo_mips
*c
, unsigned int cpu
)
1222 switch (c
->processor_id
& PRID_IMP_MASK
) {
1223 case PRID_IMP_BMIPS32_REV4
:
1224 case PRID_IMP_BMIPS32_REV8
:
1225 c
->cputype
= CPU_BMIPS32
;
1226 __cpu_name
[cpu
] = "Broadcom BMIPS32";
1227 set_elf_platform(cpu
, "bmips32");
1229 case PRID_IMP_BMIPS3300
:
1230 case PRID_IMP_BMIPS3300_ALT
:
1231 case PRID_IMP_BMIPS3300_BUG
:
1232 c
->cputype
= CPU_BMIPS3300
;
1233 __cpu_name
[cpu
] = "Broadcom BMIPS3300";
1234 set_elf_platform(cpu
, "bmips3300");
1236 case PRID_IMP_BMIPS43XX
: {
1237 int rev
= c
->processor_id
& PRID_REV_MASK
;
1239 if (rev
>= PRID_REV_BMIPS4380_LO
&&
1240 rev
<= PRID_REV_BMIPS4380_HI
) {
1241 c
->cputype
= CPU_BMIPS4380
;
1242 __cpu_name
[cpu
] = "Broadcom BMIPS4380";
1243 set_elf_platform(cpu
, "bmips4380");
1245 c
->cputype
= CPU_BMIPS4350
;
1246 __cpu_name
[cpu
] = "Broadcom BMIPS4350";
1247 set_elf_platform(cpu
, "bmips4350");
1251 case PRID_IMP_BMIPS5000
:
1252 case PRID_IMP_BMIPS5200
:
1253 c
->cputype
= CPU_BMIPS5000
;
1254 __cpu_name
[cpu
] = "Broadcom BMIPS5000";
1255 set_elf_platform(cpu
, "bmips5000");
1256 c
->options
|= MIPS_CPU_ULRI
;
1261 static inline void cpu_probe_cavium(struct cpuinfo_mips
*c
, unsigned int cpu
)
1264 switch (c
->processor_id
& PRID_IMP_MASK
) {
1265 case PRID_IMP_CAVIUM_CN38XX
:
1266 case PRID_IMP_CAVIUM_CN31XX
:
1267 case PRID_IMP_CAVIUM_CN30XX
:
1268 c
->cputype
= CPU_CAVIUM_OCTEON
;
1269 __cpu_name
[cpu
] = "Cavium Octeon";
1271 case PRID_IMP_CAVIUM_CN58XX
:
1272 case PRID_IMP_CAVIUM_CN56XX
:
1273 case PRID_IMP_CAVIUM_CN50XX
:
1274 case PRID_IMP_CAVIUM_CN52XX
:
1275 c
->cputype
= CPU_CAVIUM_OCTEON_PLUS
;
1276 __cpu_name
[cpu
] = "Cavium Octeon+";
1278 set_elf_platform(cpu
, "octeon");
1280 case PRID_IMP_CAVIUM_CN61XX
:
1281 case PRID_IMP_CAVIUM_CN63XX
:
1282 case PRID_IMP_CAVIUM_CN66XX
:
1283 case PRID_IMP_CAVIUM_CN68XX
:
1284 case PRID_IMP_CAVIUM_CNF71XX
:
1285 c
->cputype
= CPU_CAVIUM_OCTEON2
;
1286 __cpu_name
[cpu
] = "Cavium Octeon II";
1287 set_elf_platform(cpu
, "octeon2");
1289 case PRID_IMP_CAVIUM_CN70XX
:
1290 case PRID_IMP_CAVIUM_CN78XX
:
1291 c
->cputype
= CPU_CAVIUM_OCTEON3
;
1292 __cpu_name
[cpu
] = "Cavium Octeon III";
1293 set_elf_platform(cpu
, "octeon3");
1296 printk(KERN_INFO
"Unknown Octeon chip!\n");
1297 c
->cputype
= CPU_UNKNOWN
;
1302 static inline void cpu_probe_ingenic(struct cpuinfo_mips
*c
, unsigned int cpu
)
1305 /* JZRISC does not implement the CP0 counter. */
1306 c
->options
&= ~MIPS_CPU_COUNTER
;
1307 BUG_ON(!__builtin_constant_p(cpu_has_counter
) || cpu_has_counter
);
1308 switch (c
->processor_id
& PRID_IMP_MASK
) {
1309 case PRID_IMP_JZRISC
:
1310 c
->cputype
= CPU_JZRISC
;
1311 c
->writecombine
= _CACHE_UNCACHED_ACCELERATED
;
1312 __cpu_name
[cpu
] = "Ingenic JZRISC";
1315 panic("Unknown Ingenic Processor ID!");
1320 static inline void cpu_probe_netlogic(struct cpuinfo_mips
*c
, int cpu
)
1324 if ((c
->processor_id
& PRID_IMP_MASK
) == PRID_IMP_NETLOGIC_AU13XX
) {
1325 c
->cputype
= CPU_ALCHEMY
;
1326 __cpu_name
[cpu
] = "Au1300";
1327 /* following stuff is not for Alchemy */
1331 c
->options
= (MIPS_CPU_TLB
|
1339 switch (c
->processor_id
& PRID_IMP_MASK
) {
1340 case PRID_IMP_NETLOGIC_XLP2XX
:
1341 case PRID_IMP_NETLOGIC_XLP9XX
:
1342 case PRID_IMP_NETLOGIC_XLP5XX
:
1343 c
->cputype
= CPU_XLP
;
1344 __cpu_name
[cpu
] = "Broadcom XLPII";
1347 case PRID_IMP_NETLOGIC_XLP8XX
:
1348 case PRID_IMP_NETLOGIC_XLP3XX
:
1349 c
->cputype
= CPU_XLP
;
1350 __cpu_name
[cpu
] = "Netlogic XLP";
1353 case PRID_IMP_NETLOGIC_XLR732
:
1354 case PRID_IMP_NETLOGIC_XLR716
:
1355 case PRID_IMP_NETLOGIC_XLR532
:
1356 case PRID_IMP_NETLOGIC_XLR308
:
1357 case PRID_IMP_NETLOGIC_XLR532C
:
1358 case PRID_IMP_NETLOGIC_XLR516C
:
1359 case PRID_IMP_NETLOGIC_XLR508C
:
1360 case PRID_IMP_NETLOGIC_XLR308C
:
1361 c
->cputype
= CPU_XLR
;
1362 __cpu_name
[cpu
] = "Netlogic XLR";
1365 case PRID_IMP_NETLOGIC_XLS608
:
1366 case PRID_IMP_NETLOGIC_XLS408
:
1367 case PRID_IMP_NETLOGIC_XLS404
:
1368 case PRID_IMP_NETLOGIC_XLS208
:
1369 case PRID_IMP_NETLOGIC_XLS204
:
1370 case PRID_IMP_NETLOGIC_XLS108
:
1371 case PRID_IMP_NETLOGIC_XLS104
:
1372 case PRID_IMP_NETLOGIC_XLS616B
:
1373 case PRID_IMP_NETLOGIC_XLS608B
:
1374 case PRID_IMP_NETLOGIC_XLS416B
:
1375 case PRID_IMP_NETLOGIC_XLS412B
:
1376 case PRID_IMP_NETLOGIC_XLS408B
:
1377 case PRID_IMP_NETLOGIC_XLS404B
:
1378 c
->cputype
= CPU_XLR
;
1379 __cpu_name
[cpu
] = "Netlogic XLS";
1383 pr_info("Unknown Netlogic chip id [%02x]!\n",
1385 c
->cputype
= CPU_XLR
;
1389 if (c
->cputype
== CPU_XLP
) {
1390 set_isa(c
, MIPS_CPU_ISA_M64R2
);
1391 c
->options
|= (MIPS_CPU_FPU
| MIPS_CPU_ULRI
| MIPS_CPU_MCHECK
);
1392 /* This will be updated again after all threads are woken up */
1393 c
->tlbsize
= ((read_c0_config6() >> 16) & 0xffff) + 1;
1395 set_isa(c
, MIPS_CPU_ISA_M64R1
);
1396 c
->tlbsize
= ((read_c0_config1() >> 25) & 0x3f) + 1;
1398 c
->kscratch_mask
= 0xf;
1402 /* For use by uaccess.h */
1404 EXPORT_SYMBOL(__ua_limit
);
1407 const char *__cpu_name
[NR_CPUS
];
1408 const char *__elf_platform
;
1410 void cpu_probe(void)
1412 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1413 unsigned int cpu
= smp_processor_id();
1415 c
->processor_id
= PRID_IMP_UNKNOWN
;
1416 c
->fpu_id
= FPIR_IMP_NONE
;
1417 c
->cputype
= CPU_UNKNOWN
;
1418 c
->writecombine
= _CACHE_UNCACHED
;
1420 c
->fpu_csr31
= FPU_CSR_RN
;
1421 c
->fpu_msk31
= FPU_CSR_RSVD
| FPU_CSR_ABS2008
| FPU_CSR_NAN2008
;
1423 c
->processor_id
= read_c0_prid();
1424 switch (c
->processor_id
& PRID_COMP_MASK
) {
1425 case PRID_COMP_LEGACY
:
1426 cpu_probe_legacy(c
, cpu
);
1428 case PRID_COMP_MIPS
:
1429 cpu_probe_mips(c
, cpu
);
1431 case PRID_COMP_ALCHEMY
:
1432 cpu_probe_alchemy(c
, cpu
);
1434 case PRID_COMP_SIBYTE
:
1435 cpu_probe_sibyte(c
, cpu
);
1437 case PRID_COMP_BROADCOM
:
1438 cpu_probe_broadcom(c
, cpu
);
1440 case PRID_COMP_SANDCRAFT
:
1441 cpu_probe_sandcraft(c
, cpu
);
1444 cpu_probe_nxp(c
, cpu
);
1446 case PRID_COMP_CAVIUM
:
1447 cpu_probe_cavium(c
, cpu
);
1449 case PRID_COMP_INGENIC_D0
:
1450 case PRID_COMP_INGENIC_D1
:
1451 case PRID_COMP_INGENIC_E1
:
1452 cpu_probe_ingenic(c
, cpu
);
1454 case PRID_COMP_NETLOGIC
:
1455 cpu_probe_netlogic(c
, cpu
);
1459 BUG_ON(!__cpu_name
[cpu
]);
1460 BUG_ON(c
->cputype
== CPU_UNKNOWN
);
1463 * Platform code can force the cpu type to optimize code
1464 * generation. In that case be sure the cpu type is correctly
1465 * manually setup otherwise it could trigger some nasty bugs.
1467 BUG_ON(current_cpu_type() != c
->cputype
);
1469 if (mips_fpu_disabled
)
1470 c
->options
&= ~MIPS_CPU_FPU
;
1472 if (mips_dsp_disabled
)
1473 c
->ases
&= ~(MIPS_ASE_DSP
| MIPS_ASE_DSP2P
);
1475 if (mips_htw_disabled
) {
1476 c
->options
&= ~MIPS_CPU_HTW
;
1477 write_c0_pwctl(read_c0_pwctl() &
1478 ~(1 << MIPS_PWCTL_PWEN_SHIFT
));
1481 if (c
->options
& MIPS_CPU_FPU
)
1482 cpu_set_fpu_opts(c
);
1484 cpu_set_nofpu_opts(c
);
1486 if (cpu_has_bp_ghist
)
1487 write_c0_r10k_diag(read_c0_r10k_diag() |
1490 if (cpu_has_mips_r2_r6
) {
1491 c
->srsets
= ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1492 /* R2 has Performance Counter Interrupt indicator */
1493 c
->options
|= MIPS_CPU_PCI
;
1499 c
->msa_id
= cpu_get_msa_id();
1500 WARN(c
->msa_id
& MSA_IR_WRPF
,
1501 "Vector register partitioning unimplemented!");
1504 cpu_probe_vmbits(c
);
1508 __ua_limit
= ~((1ull << cpu_vmbits
) - 1);
1512 void cpu_report(void)
1514 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1516 pr_info("CPU%d revision is: %08x (%s)\n",
1517 smp_processor_id(), c
->processor_id
, cpu_name_string());
1518 if (c
->options
& MIPS_CPU_FPU
)
1519 printk(KERN_INFO
"FPU revision is: %08x\n", c
->fpu_id
);
1521 pr_info("MSA revision is: %08x\n", c
->msa_id
);