2 * Copyright (C) 2013 Imagination Technologies
3 * Author: Paul Burton <paul.burton@imgtec.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
11 #include <linux/delay.h>
13 #include <linux/irqchip/mips-gic.h>
14 #include <linux/sched.h>
15 #include <linux/slab.h>
16 #include <linux/smp.h>
17 #include <linux/types.h>
19 #include <asm/bcache.h>
20 #include <asm/mips-cm.h>
21 #include <asm/mips-cpc.h>
22 #include <asm/mips_mt.h>
23 #include <asm/mipsregs.h>
24 #include <asm/pm-cps.h>
25 #include <asm/r4kcache.h>
26 #include <asm/smp-cps.h>
30 static DECLARE_BITMAP(core_power
, NR_CPUS
);
32 struct core_boot_config
*mips_cps_core_bootcfg
;
34 static unsigned core_vpe_count(unsigned core
)
38 if (!config_enabled(CONFIG_MIPS_MT_SMP
) || !cpu_has_mipsmt
)
41 mips_cm_lock_other(core
, 0);
42 cfg
= read_gcr_co_config() & CM_GCR_Cx_CONFIG_PVPE_MSK
;
43 mips_cm_unlock_other();
44 return (cfg
>> CM_GCR_Cx_CONFIG_PVPE_SHF
) + 1;
47 static void __init
cps_smp_setup(void)
49 unsigned int ncores
, nvpes
, core_vpes
;
52 /* Detect & record VPE topology */
53 ncores
= mips_cm_numcores();
54 pr_info("VPE topology ");
55 for (c
= nvpes
= 0; c
< ncores
; c
++) {
56 core_vpes
= core_vpe_count(c
);
57 pr_cont("%c%u", c
? ',' : '{', core_vpes
);
59 /* Use the number of VPEs in core 0 for smp_num_siblings */
61 smp_num_siblings
= core_vpes
;
63 for (v
= 0; v
< min_t(int, core_vpes
, NR_CPUS
- nvpes
); v
++) {
64 cpu_data
[nvpes
+ v
].core
= c
;
65 #ifdef CONFIG_MIPS_MT_SMP
66 cpu_data
[nvpes
+ v
].vpe_id
= v
;
72 pr_cont("} total %u\n", nvpes
);
74 /* Indicate present CPUs (CPU being synonymous with VPE) */
75 for (v
= 0; v
< min_t(unsigned, nvpes
, NR_CPUS
); v
++) {
76 set_cpu_possible(v
, true);
77 set_cpu_present(v
, true);
78 __cpu_number_map
[v
] = v
;
79 __cpu_logical_map
[v
] = v
;
82 /* Set a coherent default CCA (CWB) */
83 change_c0_config(CONF_CM_CMASK
, 0x5);
85 /* Core 0 is powered up (we're running on it) */
86 bitmap_set(core_power
, 0, 1);
88 /* Initialise core 0 */
91 /* Make core 0 coherent with everything */
92 write_gcr_cl_coherence(0xff);
94 #ifdef CONFIG_MIPS_MT_FPAFF
95 /* If we have an FPU, enroll ourselves in the FPU-full mask */
97 cpumask_set_cpu(0, &mt_fpu_cpumask
);
98 #endif /* CONFIG_MIPS_MT_FPAFF */
101 static void __init
cps_prepare_cpus(unsigned int max_cpus
)
103 unsigned ncores
, core_vpes
, c
, cca
;
107 mips_mt_set_cpuoptions();
109 /* Detect whether the CCA is unsuited to multi-core SMP */
110 cca
= read_c0_config() & CONF_CM_CMASK
;
114 /* The CCA is coherent, multi-core is fine */
115 cca_unsuitable
= false;
119 /* CCA is not coherent, multi-core is not usable */
120 cca_unsuitable
= true;
123 /* Warn the user if the CCA prevents multi-core */
124 ncores
= mips_cm_numcores();
125 if (cca_unsuitable
&& ncores
> 1) {
126 pr_warn("Using only one core due to unsuitable CCA 0x%x\n",
129 for_each_present_cpu(c
) {
130 if (cpu_data
[c
].core
)
131 set_cpu_present(c
, false);
136 * Patch the start of mips_cps_core_entry to provide:
140 entry_code
= (u32
*)&mips_cps_core_entry
;
141 uasm_i_addiu(&entry_code
, 16, 0, cca
);
142 blast_dcache_range((unsigned long)&mips_cps_core_entry
,
143 (unsigned long)entry_code
);
144 bc_wback_inv((unsigned long)&mips_cps_core_entry
,
145 (void *)entry_code
- (void *)&mips_cps_core_entry
);
148 /* Allocate core boot configuration structs */
149 mips_cps_core_bootcfg
= kcalloc(ncores
, sizeof(*mips_cps_core_bootcfg
),
151 if (!mips_cps_core_bootcfg
) {
152 pr_err("Failed to allocate boot config for %u cores\n", ncores
);
156 /* Allocate VPE boot configuration structs */
157 for (c
= 0; c
< ncores
; c
++) {
158 core_vpes
= core_vpe_count(c
);
159 mips_cps_core_bootcfg
[c
].vpe_config
= kcalloc(core_vpes
,
160 sizeof(*mips_cps_core_bootcfg
[c
].vpe_config
),
162 if (!mips_cps_core_bootcfg
[c
].vpe_config
) {
163 pr_err("Failed to allocate %u VPE boot configs\n",
169 /* Mark this CPU as booted */
170 atomic_set(&mips_cps_core_bootcfg
[current_cpu_data
.core
].vpe_mask
,
171 1 << cpu_vpe_id(¤t_cpu_data
));
175 /* Clean up allocations */
176 if (mips_cps_core_bootcfg
) {
177 for (c
= 0; c
< ncores
; c
++)
178 kfree(mips_cps_core_bootcfg
[c
].vpe_config
);
179 kfree(mips_cps_core_bootcfg
);
180 mips_cps_core_bootcfg
= NULL
;
183 /* Effectively disable SMP by declaring CPUs not present */
184 for_each_possible_cpu(c
) {
187 set_cpu_present(c
, false);
191 static void boot_core(unsigned core
)
193 u32 access
, stat
, seq_state
;
196 /* Select the appropriate core */
197 mips_cm_lock_other(core
, 0);
199 /* Set its reset vector */
200 write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry
));
202 /* Ensure its coherency is disabled */
203 write_gcr_co_coherence(0);
205 /* Start it with the legacy memory map and exception base */
206 write_gcr_co_reset_ext_base(CM_GCR_RESET_EXT_BASE_UEB
);
208 /* Ensure the core can access the GCRs */
209 access
= read_gcr_access();
210 access
|= 1 << (CM_GCR_ACCESS_ACCESSEN_SHF
+ core
);
211 write_gcr_access(access
);
213 if (mips_cpc_present()) {
215 mips_cpc_lock_other(core
);
216 write_cpc_co_cmd(CPC_Cx_CMD_RESET
);
220 stat
= read_cpc_co_stat_conf();
221 seq_state
= stat
& CPC_Cx_STAT_CONF_SEQSTATE_MSK
;
223 /* U6 == coherent execution, ie. the core is up */
224 if (seq_state
== CPC_Cx_STAT_CONF_SEQSTATE_U6
)
227 /* Delay a little while before we start warning */
234 pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n",
239 mips_cpc_unlock_other();
241 /* Take the core out of reset */
242 write_gcr_co_reset_release(0);
245 mips_cm_unlock_other();
247 /* The core is now powered up */
248 bitmap_set(core_power
, core
, 1);
251 static void remote_vpe_boot(void *dummy
)
253 unsigned core
= current_cpu_data
.core
;
254 struct core_boot_config
*core_cfg
= &mips_cps_core_bootcfg
[core
];
256 mips_cps_boot_vpes(core_cfg
, cpu_vpe_id(¤t_cpu_data
));
259 static void cps_boot_secondary(int cpu
, struct task_struct
*idle
)
261 unsigned core
= cpu_data
[cpu
].core
;
262 unsigned vpe_id
= cpu_vpe_id(&cpu_data
[cpu
]);
263 struct core_boot_config
*core_cfg
= &mips_cps_core_bootcfg
[core
];
264 struct vpe_boot_config
*vpe_cfg
= &core_cfg
->vpe_config
[vpe_id
];
268 vpe_cfg
->pc
= (unsigned long)&smp_bootstrap
;
269 vpe_cfg
->sp
= __KSTK_TOS(idle
);
270 vpe_cfg
->gp
= (unsigned long)task_thread_info(idle
);
272 atomic_or(1 << cpu_vpe_id(&cpu_data
[cpu
]), &core_cfg
->vpe_mask
);
276 if (!test_bit(core
, core_power
)) {
277 /* Boot a VPE on a powered down core */
282 if (core
!= current_cpu_data
.core
) {
283 /* Boot a VPE on another powered up core */
284 for (remote
= 0; remote
< NR_CPUS
; remote
++) {
285 if (cpu_data
[remote
].core
!= core
)
287 if (cpu_online(remote
))
290 BUG_ON(remote
>= NR_CPUS
);
292 err
= smp_call_function_single(remote
, remote_vpe_boot
,
295 panic("Failed to call remote CPU\n");
299 BUG_ON(!cpu_has_mipsmt
);
301 /* Boot a VPE on this core */
302 mips_cps_boot_vpes(core_cfg
, vpe_id
);
307 static void cps_init_secondary(void)
309 /* Disable MT - we only want to run 1 TC per VPE */
313 if (mips_cm_revision() >= CM_REV_CM3
) {
314 unsigned ident
= gic_read_local_vp_id();
317 * Ensure that our calculation of the VP ID matches up with
318 * what the GIC reports, otherwise we'll have configured
319 * interrupts incorrectly.
321 BUG_ON(ident
!= mips_cm_vp_id(smp_processor_id()));
324 change_c0_status(ST0_IM
, STATUSF_IP2
| STATUSF_IP3
| STATUSF_IP4
|
325 STATUSF_IP5
| STATUSF_IP6
| STATUSF_IP7
);
328 static void cps_smp_finish(void)
330 write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency
/ HZ
));
332 #ifdef CONFIG_MIPS_MT_FPAFF
333 /* If we have an FPU, enroll ourselves in the FPU-full mask */
335 cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask
);
336 #endif /* CONFIG_MIPS_MT_FPAFF */
341 #ifdef CONFIG_HOTPLUG_CPU
343 static int cps_cpu_disable(void)
345 unsigned cpu
= smp_processor_id();
346 struct core_boot_config
*core_cfg
;
351 if (!cps_pm_support_state(CPS_PM_POWER_GATED
))
354 core_cfg
= &mips_cps_core_bootcfg
[current_cpu_data
.core
];
355 atomic_sub(1 << cpu_vpe_id(¤t_cpu_data
), &core_cfg
->vpe_mask
);
356 smp_mb__after_atomic();
357 set_cpu_online(cpu
, false);
358 cpumask_clear_cpu(cpu
, &cpu_callin_map
);
363 static DECLARE_COMPLETION(cpu_death_chosen
);
364 static unsigned cpu_death_sibling
;
376 cpu
= smp_processor_id();
377 cpu_death
= CPU_DEATH_POWER
;
379 if (cpu_has_mipsmt
) {
380 core
= cpu_data
[cpu
].core
;
382 /* Look for another online VPE within the core */
383 for_each_online_cpu(cpu_death_sibling
) {
384 if (cpu_data
[cpu_death_sibling
].core
!= core
)
388 * There is an online VPE within the core. Just halt
389 * this TC and leave the core alone.
391 cpu_death
= CPU_DEATH_HALT
;
396 /* This CPU has chosen its way out */
397 complete(&cpu_death_chosen
);
399 if (cpu_death
== CPU_DEATH_HALT
) {
401 write_c0_tchalt(TCHALT_H
);
402 instruction_hazard();
404 /* Power down the core */
405 cps_pm_enter_state(CPS_PM_POWER_GATED
);
408 /* This should never be reached */
409 panic("Failed to offline CPU %u", cpu
);
412 static void wait_for_sibling_halt(void *ptr_cpu
)
414 unsigned cpu
= (unsigned long)ptr_cpu
;
415 unsigned vpe_id
= cpu_vpe_id(&cpu_data
[cpu
]);
420 local_irq_save(flags
);
422 halted
= read_tc_c0_tchalt();
423 local_irq_restore(flags
);
424 } while (!(halted
& TCHALT_H
));
427 static void cps_cpu_die(unsigned int cpu
)
429 unsigned core
= cpu_data
[cpu
].core
;
433 /* Wait for the cpu to choose its way out */
434 if (!wait_for_completion_timeout(&cpu_death_chosen
,
435 msecs_to_jiffies(5000))) {
436 pr_err("CPU%u: didn't offline\n", cpu
);
441 * Now wait for the CPU to actually offline. Without doing this that
442 * offlining may race with one or more of:
444 * - Onlining the CPU again.
445 * - Powering down the core if another VPE within it is offlined.
446 * - A sibling VPE entering a non-coherent state.
448 * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing
449 * with which we could race, so do nothing.
451 if (cpu_death
== CPU_DEATH_POWER
) {
453 * Wait for the core to enter a powered down or clock gated
454 * state, the latter happening when a JTAG probe is connected
455 * in which case the CPC will refuse to power down the core.
458 mips_cpc_lock_other(core
);
459 stat
= read_cpc_co_stat_conf();
460 stat
&= CPC_Cx_STAT_CONF_SEQSTATE_MSK
;
461 mips_cpc_unlock_other();
462 } while (stat
!= CPC_Cx_STAT_CONF_SEQSTATE_D0
&&
463 stat
!= CPC_Cx_STAT_CONF_SEQSTATE_D2
&&
464 stat
!= CPC_Cx_STAT_CONF_SEQSTATE_U2
);
466 /* Indicate the core is powered off */
467 bitmap_clear(core_power
, core
, 1);
468 } else if (cpu_has_mipsmt
) {
470 * Have a CPU with access to the offlined CPUs registers wait
471 * for its TC to halt.
473 err
= smp_call_function_single(cpu_death_sibling
,
474 wait_for_sibling_halt
,
475 (void *)(unsigned long)cpu
, 1);
477 panic("Failed to call remote sibling CPU\n");
481 #endif /* CONFIG_HOTPLUG_CPU */
483 static struct plat_smp_ops cps_smp_ops
= {
484 .smp_setup
= cps_smp_setup
,
485 .prepare_cpus
= cps_prepare_cpus
,
486 .boot_secondary
= cps_boot_secondary
,
487 .init_secondary
= cps_init_secondary
,
488 .smp_finish
= cps_smp_finish
,
489 .send_ipi_single
= mips_smp_send_ipi_single
,
490 .send_ipi_mask
= mips_smp_send_ipi_mask
,
491 #ifdef CONFIG_HOTPLUG_CPU
492 .cpu_disable
= cps_cpu_disable
,
493 .cpu_die
= cps_cpu_die
,
497 bool mips_cps_smp_in_use(void)
499 extern struct plat_smp_ops
*mp_ops
;
500 return mp_ops
== &cps_smp_ops
;
503 int register_cps_smp_ops(void)
505 if (!mips_cm_present()) {
506 pr_warn("MIPS CPS SMP unable to proceed without a CM\n");
510 /* check we have a GIC - we need one for IPIs */
511 if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX_MSK
)) {
512 pr_warn("MIPS CPS SMP unable to proceed without a GIC\n");
516 register_smp_ops(&cps_smp_ops
);