arch/mips/kvm/locore.S

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Main entry point for the guest, exception handling.
   7  *
   8  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
   9  * Authors: Sanjay Lal <sanjayl@kymasys.com>
  10  */
  11
  12 #include <asm/asm.h>
  13 #include <asm/asmmacro.h>
  14 #include <asm/regdef.h>
  15 #include <asm/mipsregs.h>
  16 #include <asm/stackframe.h>
  17 #include <asm/asm-offsets.h>
  18
  19 #define _C_LABEL(x)     x
  20 #define MIPSX(name)     mips32_ ## name
  21 #define CALLFRAME_SIZ   32
  22
  23 /*
  24  * VECTOR
  25  *  exception vector entrypoint
  26  */
  27 #define VECTOR(x, regmask)      \
  28     .ent    _C_LABEL(x),0;      \
  29     EXPORT(x);
  30
  31 #define VECTOR_END(x)      \
  32     EXPORT(x);
  33
  34 /* Overload, Danger Will Robinson!! */
  35 #define PT_HOST_USERLOCAL   PT_EPC
  36
  37 #define CP0_DDATA_LO        $28,3
  38
  39 /* Resume Flags */
  40 #define RESUME_FLAG_HOST        (1<<1)  /* Resume host? */
  41
  42 #define RESUME_GUEST            0
  43 #define RESUME_HOST             RESUME_FLAG_HOST
  44
  45 /*
  46  * __kvm_mips_vcpu_run: entry point to the guest
  47  * a0: run
  48  * a1: vcpu
  49  */
  50         .set    noreorder
  51
  52 FEXPORT(__kvm_mips_vcpu_run)
  53         /* k0/k1 not being used in host kernel context */
  54         INT_ADDIU k1, sp, -PT_SIZE
  55         LONG_S  $16, PT_R16(k1)
  56         LONG_S  $17, PT_R17(k1)
  57         LONG_S  $18, PT_R18(k1)
  58         LONG_S  $19, PT_R19(k1)
  59         LONG_S  $20, PT_R20(k1)
  60         LONG_S  $21, PT_R21(k1)
  61         LONG_S  $22, PT_R22(k1)
  62         LONG_S  $23, PT_R23(k1)
  63
  64         LONG_S  $28, PT_R28(k1)
  65         LONG_S  $29, PT_R29(k1)
  66         LONG_S  $30, PT_R30(k1)
  67         LONG_S  $31, PT_R31(k1)
  68
  69         /* Save hi/lo */
  70         mflo    v0
  71         LONG_S  v0, PT_LO(k1)
  72         mfhi    v1
  73         LONG_S  v1, PT_HI(k1)
  74
  75         /* Save host status */
  76         mfc0    v0, CP0_STATUS
  77         LONG_S  v0, PT_STATUS(k1)
  78
  79         /* Save DDATA_LO, will be used to store pointer to vcpu */
  80         mfc0    v1, CP0_DDATA_LO
  81         LONG_S  v1, PT_HOST_USERLOCAL(k1)
  82
  83         /* DDATA_LO has pointer to vcpu */
  84         mtc0    a1, CP0_DDATA_LO
  85
  86         /* Offset into vcpu->arch */
  87         INT_ADDIU k1, a1, VCPU_HOST_ARCH
  88
  89         /*
  90          * Save the host stack to VCPU, used for exception processing
  91          * when we exit from the Guest
  92          */
  93         LONG_S  sp, VCPU_HOST_STACK(k1)
  94
  95         /* Save the kernel gp as well */
  96         LONG_S  gp, VCPU_HOST_GP(k1)
  97
  98         /*
  99          * Setup status register for running the guest in UM, interrupts
 100          * are disabled
 101          */
 102         li      k0, (ST0_EXL | KSU_USER | ST0_BEV)
 103         mtc0    k0, CP0_STATUS
 104         ehb
 105
 106         /* load up the new EBASE */
 107         LONG_L  k0, VCPU_GUEST_EBASE(k1)
 108         mtc0    k0, CP0_EBASE
 109
 110         /*
 111          * Now that the new EBASE has been loaded, unset BEV, set
 112          * interrupt mask as it was but make sure that timer interrupts
 113          * are enabled
 114          */
 115         li      k0, (ST0_EXL | KSU_USER | ST0_IE)
 116         andi    v0, v0, ST0_IM
 117         or      k0, k0, v0
 118         mtc0    k0, CP0_STATUS
 119         ehb
 120
 121         /* Set Guest EPC */
 122         LONG_L  t0, VCPU_PC(k1)
 123         mtc0    t0, CP0_EPC
 124
 125 FEXPORT(__kvm_mips_load_asid)
 126         /* Set the ASID for the Guest Kernel */
 127         PTR_L   t0, VCPU_COP0(k1)
 128         LONG_L  t0, COP0_STATUS(t0)
 129         andi    t0, KSU_USER | ST0_ERL | ST0_EXL
 130         xori    t0, KSU_USER
 131         bnez    t0, 1f          /* If kernel */
 132          INT_ADDIU t1, k1, VCPU_GUEST_KERNEL_ASID  /* (BD)  */
 133         INT_ADDIU t1, k1, VCPU_GUEST_USER_ASID    /* else user */
 134 1:
 135         /* t1: contains the base of the ASID array, need to get the cpu id */
 136         LONG_L  t2, TI_CPU($28)             /* smp_processor_id */
 137         INT_SLL t2, t2, 2                   /* x4 */
 138         REG_ADDU t3, t1, t2
 139         LONG_L  k0, (t3)
 140 #ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
 141         li      t3, CPUINFO_SIZE/4
 142         mul     t2, t2, t3              /* x sizeof(struct cpuinfo_mips)/4 */
 143         LONG_L  t2, (cpu_data + CPUINFO_ASID_MASK)(t2)
 144         and     k0, k0, t2
 145 #else
 146         andi    k0, k0, MIPS_ENTRYHI_ASID
 147 #endif
 148         mtc0    k0, CP0_ENTRYHI
 149         ehb
 150
 151         /* Disable RDHWR access */
 152         mtc0    zero, CP0_HWRENA
 153
 154         .set    noat
 155         /* Now load up the Guest Context from VCPU */
 156         LONG_L  $1, VCPU_R1(k1)
 157         LONG_L  $2, VCPU_R2(k1)
 158         LONG_L  $3, VCPU_R3(k1)
 159
 160         LONG_L  $4, VCPU_R4(k1)
 161         LONG_L  $5, VCPU_R5(k1)
 162         LONG_L  $6, VCPU_R6(k1)
 163         LONG_L  $7, VCPU_R7(k1)
 164
 165         LONG_L  $8, VCPU_R8(k1)
 166         LONG_L  $9, VCPU_R9(k1)
 167         LONG_L  $10, VCPU_R10(k1)
 168         LONG_L  $11, VCPU_R11(k1)
 169         LONG_L  $12, VCPU_R12(k1)
 170         LONG_L  $13, VCPU_R13(k1)
 171         LONG_L  $14, VCPU_R14(k1)
 172         LONG_L  $15, VCPU_R15(k1)
 173         LONG_L  $16, VCPU_R16(k1)
 174         LONG_L  $17, VCPU_R17(k1)
 175         LONG_L  $18, VCPU_R18(k1)
 176         LONG_L  $19, VCPU_R19(k1)
 177         LONG_L  $20, VCPU_R20(k1)
 178         LONG_L  $21, VCPU_R21(k1)
 179         LONG_L  $22, VCPU_R22(k1)
 180         LONG_L  $23, VCPU_R23(k1)
 181         LONG_L  $24, VCPU_R24(k1)
 182         LONG_L  $25, VCPU_R25(k1)
 183
 184         /* k0/k1 loaded up later */
 185
 186         LONG_L  $28, VCPU_R28(k1)
 187         LONG_L  $29, VCPU_R29(k1)
 188         LONG_L  $30, VCPU_R30(k1)
 189         LONG_L  $31, VCPU_R31(k1)
 190
 191         /* Restore hi/lo */
 192         LONG_L  k0, VCPU_LO(k1)
 193         mtlo    k0
 194
 195         LONG_L  k0, VCPU_HI(k1)
 196         mthi    k0
 197
 198 FEXPORT(__kvm_mips_load_k0k1)
 199         /* Restore the guest's k0/k1 registers */
 200         LONG_L  k0, VCPU_R26(k1)
 201         LONG_L  k1, VCPU_R27(k1)
 202
 203         /* Jump to guest */
 204         eret
 205 EXPORT(__kvm_mips_vcpu_run_end)
 206
 207 VECTOR(MIPSX(exception), unknown)
 208 /* Find out what mode we came from and jump to the proper handler. */
 209         mtc0    k0, CP0_ERROREPC        #01: Save guest k0
 210         ehb                             #02:
 211
 212         mfc0    k0, CP0_EBASE           #02: Get EBASE
 213         INT_SRL k0, k0, 10              #03: Get rid of CPUNum
 214         INT_SLL k0, k0, 10              #04
 215         LONG_S  k1, 0x3000(k0)          #05: Save k1 @ offset 0x3000
 216         INT_ADDIU k0, k0, 0x2000        #06: Exception handler is
 217                                         #    installed @ offset 0x2000
 218         j       k0                      #07: jump to the function
 219          nop                            #08: branch delay slot
 220 VECTOR_END(MIPSX(exceptionEnd))
 221 .end MIPSX(exception)
 222
 223 /*
 224  * Generic Guest exception handler. We end up here when the guest
 225  * does something that causes a trap to kernel mode.
 226  */
 227 NESTED (MIPSX(GuestException), CALLFRAME_SIZ, ra)
 228         /* Get the VCPU pointer from DDTATA_LO */
 229         mfc0    k1, CP0_DDATA_LO
 230         INT_ADDIU k1, k1, VCPU_HOST_ARCH
 231
 232         /* Start saving Guest context to VCPU */
 233         LONG_S  $0, VCPU_R0(k1)
 234         LONG_S  $1, VCPU_R1(k1)
 235         LONG_S  $2, VCPU_R2(k1)
 236         LONG_S  $3, VCPU_R3(k1)
 237         LONG_S  $4, VCPU_R4(k1)
 238         LONG_S  $5, VCPU_R5(k1)
 239         LONG_S  $6, VCPU_R6(k1)
 240         LONG_S  $7, VCPU_R7(k1)
 241         LONG_S  $8, VCPU_R8(k1)
 242         LONG_S  $9, VCPU_R9(k1)
 243         LONG_S  $10, VCPU_R10(k1)
 244         LONG_S  $11, VCPU_R11(k1)
 245         LONG_S  $12, VCPU_R12(k1)
 246         LONG_S  $13, VCPU_R13(k1)
 247         LONG_S  $14, VCPU_R14(k1)
 248         LONG_S  $15, VCPU_R15(k1)
 249         LONG_S  $16, VCPU_R16(k1)
 250         LONG_S  $17, VCPU_R17(k1)
 251         LONG_S  $18, VCPU_R18(k1)
 252         LONG_S  $19, VCPU_R19(k1)
 253         LONG_S  $20, VCPU_R20(k1)
 254         LONG_S  $21, VCPU_R21(k1)
 255         LONG_S  $22, VCPU_R22(k1)
 256         LONG_S  $23, VCPU_R23(k1)
 257         LONG_S  $24, VCPU_R24(k1)
 258         LONG_S  $25, VCPU_R25(k1)
 259
 260         /* Guest k0/k1 saved later */
 261
 262         LONG_S  $28, VCPU_R28(k1)
 263         LONG_S  $29, VCPU_R29(k1)
 264         LONG_S  $30, VCPU_R30(k1)
 265         LONG_S  $31, VCPU_R31(k1)
 266
 267         .set at
 268
 269         /* We need to save hi/lo and restore them on the way out */
 270         mfhi    t0
 271         LONG_S  t0, VCPU_HI(k1)
 272
 273         mflo    t0
 274         LONG_S  t0, VCPU_LO(k1)
 275
 276         /* Finally save guest k0/k1 to VCPU */
 277         mfc0    t0, CP0_ERROREPC
 278         LONG_S  t0, VCPU_R26(k1)
 279
 280         /* Get GUEST k1 and save it in VCPU */
 281         PTR_LI  t1, ~0x2ff
 282         mfc0    t0, CP0_EBASE
 283         and     t0, t0, t1
 284         LONG_L  t0, 0x3000(t0)
 285         LONG_S  t0, VCPU_R27(k1)
 286
 287         /* Now that context has been saved, we can use other registers */
 288
 289         /* Restore vcpu */
 290         mfc0    a1, CP0_DDATA_LO
 291         move    s1, a1
 292
 293         /* Restore run (vcpu->run) */
 294         LONG_L  a0, VCPU_RUN(a1)
 295         /* Save pointer to run in s0, will be saved by the compiler */
 296         move    s0, a0
 297
 298         /*
 299          * Save Host level EPC, BadVaddr and Cause to VCPU, useful to
 300          * process the exception
 301          */
 302         mfc0    k0,CP0_EPC
 303         LONG_S  k0, VCPU_PC(k1)
 304
 305         mfc0    k0, CP0_BADVADDR
 306         LONG_S  k0, VCPU_HOST_CP0_BADVADDR(k1)
 307
 308         mfc0    k0, CP0_CAUSE
 309         sw      k0, VCPU_HOST_CP0_CAUSE(k1)
 310
 311         /* Now restore the host state just enough to run the handlers */
 312
 313         /* Switch EBASE to the one used by Linux */
 314         /* load up the host EBASE */
 315         mfc0    v0, CP0_STATUS
 316
 317         or      k0, v0, ST0_BEV
 318
 319         mtc0    k0, CP0_STATUS
 320         ehb
 321
 322         LONG_L  k0, ebase
 323         mtc0    k0,CP0_EBASE
 324
 325         /*
 326          * If FPU is enabled, save FCR31 and clear it so that later ctc1's don't
 327          * trigger FPE for pending exceptions.
 328          */
 329         and     v1, v0, ST0_CU1
 330         beqz    v1, 1f
 331          nop
 332         .set    push
 333         SET_HARDFLOAT
 334         cfc1    t0, fcr31
 335         sw      t0, VCPU_FCR31(k1)
 336         ctc1    zero,fcr31
 337         .set    pop
 338 1:
 339
 340 #ifdef CONFIG_CPU_HAS_MSA
 341         /*
 342          * If MSA is enabled, save MSACSR and clear it so that later
 343          * instructions don't trigger MSAFPE for pending exceptions.
 344          */
 345         mfc0    t0, CP0_CONFIG3
 346         ext     t0, t0, 28, 1 /* MIPS_CONF3_MSAP */
 347         beqz    t0, 1f
 348          nop
 349         mfc0    t0, CP0_CONFIG5
 350         ext     t0, t0, 27, 1 /* MIPS_CONF5_MSAEN */
 351         beqz    t0, 1f
 352          nop
 353         _cfcmsa t0, MSA_CSR
 354         sw      t0, VCPU_MSA_CSR(k1)
 355         _ctcmsa MSA_CSR, zero
 356 1:
 357 #endif
 358
 359         /* Now that the new EBASE has been loaded, unset BEV and KSU_USER */
 360         and     v0, v0, ~(ST0_EXL | KSU_USER | ST0_IE)
 361         or      v0, v0, ST0_CU0
 362         mtc0    v0, CP0_STATUS
 363         ehb
 364
 365         /* Load up host GP */
 366         LONG_L  gp, VCPU_HOST_GP(k1)
 367
 368         /* Need a stack before we can jump to "C" */
 369         LONG_L  sp, VCPU_HOST_STACK(k1)
 370
 371         /* Saved host state */
 372         INT_ADDIU sp, sp, -PT_SIZE
 373
 374         /*
 375          * XXXKYMA do we need to load the host ASID, maybe not because the
 376          * kernel entries are marked GLOBAL, need to verify
 377          */
 378
 379         /* Restore host DDATA_LO */
 380         LONG_L  k0, PT_HOST_USERLOCAL(sp)
 381         mtc0    k0, CP0_DDATA_LO
 382
 383         /* Restore RDHWR access */
 384         PTR_LI  k0, 0x2000000F
 385         mtc0    k0, CP0_HWRENA
 386
 387         /* Jump to handler */
 388 FEXPORT(__kvm_mips_jump_to_handler)
 389         /*
 390          * XXXKYMA: not sure if this is safe, how large is the stack??
 391          * Now jump to the kvm_mips_handle_exit() to see if we can deal
 392          * with this in the kernel
 393          */
 394         PTR_LA  t9, kvm_mips_handle_exit
 395         jalr.hb t9
 396          INT_ADDIU sp, sp, -CALLFRAME_SIZ           /* BD Slot */
 397
 398         /* Return from handler Make sure interrupts are disabled */
 399         di
 400         ehb
 401
 402         /*
 403          * XXXKYMA: k0/k1 could have been blown away if we processed
 404          * an exception while we were handling the exception from the
 405          * guest, reload k1
 406          */
 407
 408         move    k1, s1
 409         INT_ADDIU k1, k1, VCPU_HOST_ARCH
 410
 411         /*
 412          * Check return value, should tell us if we are returning to the
 413          * host (handle I/O etc)or resuming the guest
 414          */
 415         andi    t0, v0, RESUME_HOST
 416         bnez    t0, __kvm_mips_return_to_host
 417          nop
 418
 419 __kvm_mips_return_to_guest:
 420         /* Put the saved pointer to vcpu (s1) back into the DDATA_LO Register */
 421         mtc0    s1, CP0_DDATA_LO
 422
 423         /* Load up the Guest EBASE to minimize the window where BEV is set */
 424         LONG_L  t0, VCPU_GUEST_EBASE(k1)
 425
 426         /* Switch EBASE back to the one used by KVM */
 427         mfc0    v1, CP0_STATUS
 428         or      k0, v1, ST0_BEV
 429         mtc0    k0, CP0_STATUS
 430         ehb
 431         mtc0    t0, CP0_EBASE
 432
 433         /* Setup status register for running guest in UM */
 434         or      v1, v1, (ST0_EXL | KSU_USER | ST0_IE)
 435         and     v1, v1, ~(ST0_CU0 | ST0_MX)
 436         mtc0    v1, CP0_STATUS
 437         ehb
 438
 439         /* Set Guest EPC */
 440         LONG_L  t0, VCPU_PC(k1)
 441         mtc0    t0, CP0_EPC
 442
 443         /* Set the ASID for the Guest Kernel */
 444         PTR_L   t0, VCPU_COP0(k1)
 445         LONG_L  t0, COP0_STATUS(t0)
 446         andi    t0, KSU_USER | ST0_ERL | ST0_EXL
 447         xori    t0, KSU_USER
 448         bnez    t0, 1f          /* If kernel */
 449          INT_ADDIU t1, k1, VCPU_GUEST_KERNEL_ASID  /* (BD)  */
 450         INT_ADDIU t1, k1, VCPU_GUEST_USER_ASID    /* else user */
 451 1:
 452         /* t1: contains the base of the ASID array, need to get the cpu id  */
 453         LONG_L  t2, TI_CPU($28)         /* smp_processor_id */
 454         INT_SLL t2, t2, 2               /* x4 */
 455         REG_ADDU t3, t1, t2
 456         LONG_L  k0, (t3)
 457 #ifdef CONFIG_MIPS_ASID_BITS_VARIABLE
 458         li      t3, CPUINFO_SIZE/4
 459         mul     t2, t2, t3              /* x sizeof(struct cpuinfo_mips)/4 */
 460         LONG_L  t2, (cpu_data + CPUINFO_ASID_MASK)(t2)
 461         and     k0, k0, t2
 462 #else
 463         andi    k0, k0, MIPS_ENTRYHI_ASID
 464 #endif
 465         mtc0    k0, CP0_ENTRYHI
 466         ehb
 467
 468         /* Disable RDHWR access */
 469         mtc0    zero, CP0_HWRENA
 470
 471         .set    noat
 472         /* load the guest context from VCPU and return */
 473         LONG_L  $0, VCPU_R0(k1)
 474         LONG_L  $1, VCPU_R1(k1)
 475         LONG_L  $2, VCPU_R2(k1)
 476         LONG_L  $3, VCPU_R3(k1)
 477         LONG_L  $4, VCPU_R4(k1)
 478         LONG_L  $5, VCPU_R5(k1)
 479         LONG_L  $6, VCPU_R6(k1)
 480         LONG_L  $7, VCPU_R7(k1)
 481         LONG_L  $8, VCPU_R8(k1)
 482         LONG_L  $9, VCPU_R9(k1)
 483         LONG_L  $10, VCPU_R10(k1)
 484         LONG_L  $11, VCPU_R11(k1)
 485         LONG_L  $12, VCPU_R12(k1)
 486         LONG_L  $13, VCPU_R13(k1)
 487         LONG_L  $14, VCPU_R14(k1)
 488         LONG_L  $15, VCPU_R15(k1)
 489         LONG_L  $16, VCPU_R16(k1)
 490         LONG_L  $17, VCPU_R17(k1)
 491         LONG_L  $18, VCPU_R18(k1)
 492         LONG_L  $19, VCPU_R19(k1)
 493         LONG_L  $20, VCPU_R20(k1)
 494         LONG_L  $21, VCPU_R21(k1)
 495         LONG_L  $22, VCPU_R22(k1)
 496         LONG_L  $23, VCPU_R23(k1)
 497         LONG_L  $24, VCPU_R24(k1)
 498         LONG_L  $25, VCPU_R25(k1)
 499
 500         /* $/k1 loaded later */
 501         LONG_L  $28, VCPU_R28(k1)
 502         LONG_L  $29, VCPU_R29(k1)
 503         LONG_L  $30, VCPU_R30(k1)
 504         LONG_L  $31, VCPU_R31(k1)
 505
 506 FEXPORT(__kvm_mips_skip_guest_restore)
 507         LONG_L  k0, VCPU_HI(k1)
 508         mthi    k0
 509
 510         LONG_L  k0, VCPU_LO(k1)
 511         mtlo    k0
 512
 513         LONG_L  k0, VCPU_R26(k1)
 514         LONG_L  k1, VCPU_R27(k1)
 515
 516         eret
 517         .set    at
 518
 519 __kvm_mips_return_to_host:
 520         /* EBASE is already pointing to Linux */
 521         LONG_L  k1, VCPU_HOST_STACK(k1)
 522         INT_ADDIU k1,k1, -PT_SIZE
 523
 524         /* Restore host DDATA_LO */
 525         LONG_L  k0, PT_HOST_USERLOCAL(k1)
 526         mtc0    k0, CP0_DDATA_LO
 527
 528         /*
 529          * r2/v0 is the return code, shift it down by 2 (arithmetic)
 530          * to recover the err code
 531          */
 532         INT_SRA k0, v0, 2
 533         move    $2, k0
 534
 535         /* Load context saved on the host stack */
 536         LONG_L  $16, PT_R16(k1)
 537         LONG_L  $17, PT_R17(k1)
 538         LONG_L  $18, PT_R18(k1)
 539         LONG_L  $19, PT_R19(k1)
 540         LONG_L  $20, PT_R20(k1)
 541         LONG_L  $21, PT_R21(k1)
 542         LONG_L  $22, PT_R22(k1)
 543         LONG_L  $23, PT_R23(k1)
 544
 545         LONG_L  $28, PT_R28(k1)
 546         LONG_L  $29, PT_R29(k1)
 547         LONG_L  $30, PT_R30(k1)
 548
 549         LONG_L  k0, PT_HI(k1)
 550         mthi    k0
 551
 552         LONG_L  k0, PT_LO(k1)
 553         mtlo    k0
 554
 555         /* Restore RDHWR access */
 556         PTR_LI  k0, 0x2000000F
 557         mtc0    k0, CP0_HWRENA
 558
 559         /* Restore RA, which is the address we will return to */
 560         LONG_L  ra, PT_R31(k1)
 561         j       ra
 562          nop
 563
 564 VECTOR_END(MIPSX(GuestExceptionEnd))
 565 .end MIPSX(GuestException)
 566
 567 MIPSX(exceptions):
 568         ####
 569         ##### The exception handlers.
 570         #####
 571         .word _C_LABEL(MIPSX(GuestException))   #  0
 572         .word _C_LABEL(MIPSX(GuestException))   #  1
 573         .word _C_LABEL(MIPSX(GuestException))   #  2
 574         .word _C_LABEL(MIPSX(GuestException))   #  3
 575         .word _C_LABEL(MIPSX(GuestException))   #  4
 576         .word _C_LABEL(MIPSX(GuestException))   #  5
 577         .word _C_LABEL(MIPSX(GuestException))   #  6
 578         .word _C_LABEL(MIPSX(GuestException))   #  7
 579         .word _C_LABEL(MIPSX(GuestException))   #  8
 580         .word _C_LABEL(MIPSX(GuestException))   #  9
 581         .word _C_LABEL(MIPSX(GuestException))   # 10
 582         .word _C_LABEL(MIPSX(GuestException))   # 11
 583         .word _C_LABEL(MIPSX(GuestException))   # 12
 584         .word _C_LABEL(MIPSX(GuestException))   # 13
 585         .word _C_LABEL(MIPSX(GuestException))   # 14
 586         .word _C_LABEL(MIPSX(GuestException))   # 15
 587         .word _C_LABEL(MIPSX(GuestException))   # 16
 588         .word _C_LABEL(MIPSX(GuestException))   # 17
 589         .word _C_LABEL(MIPSX(GuestException))   # 18
 590         .word _C_LABEL(MIPSX(GuestException))   # 19
 591         .word _C_LABEL(MIPSX(GuestException))   # 20
 592         .word _C_LABEL(MIPSX(GuestException))   # 21
 593         .word _C_LABEL(MIPSX(GuestException))   # 22
 594         .word _C_LABEL(MIPSX(GuestException))   # 23
 595         .word _C_LABEL(MIPSX(GuestException))   # 24
 596         .word _C_LABEL(MIPSX(GuestException))   # 25
 597         .word _C_LABEL(MIPSX(GuestException))   # 26
 598         .word _C_LABEL(MIPSX(GuestException))   # 27
 599         .word _C_LABEL(MIPSX(GuestException))   # 28
 600         .word _C_LABEL(MIPSX(GuestException))   # 29
 601         .word _C_LABEL(MIPSX(GuestException))   # 30
 602         .word _C_LABEL(MIPSX(GuestException))   # 31