arch/powerpc/include/asm/book3s/64/hash.h

   1 #ifndef _ASM_POWERPC_BOOK3S_64_HASH_H
   2 #define _ASM_POWERPC_BOOK3S_64_HASH_H
   3 #ifdef __KERNEL__
   4
   5 /*
   6  * Common bits between 4K and 64K pages in a linux-style PTE.
   7  * These match the bits in the (hardware-defined) PowerPC PTE as closely
   8  * as possible. Additional bits may be defined in pgtable-hash64-*.h
   9  *
  10  * Note: We only support user read/write permissions. Supervisor always
  11  * have full read/write to pages above PAGE_OFFSET (pages below that
  12  * always use the user access permissions).
  13  *
  14  * We could create separate kernel read-only if we used the 3 PP bits
  15  * combinations that newer processors provide but we currently don't.
  16  */
  17 #define _PAGE_PTE               0x00001
  18 #define _PAGE_PRESENT           0x00002 /* software: pte contains a translation */
  19 #define _PAGE_BIT_SWAP_TYPE     2
  20 #define _PAGE_USER              0x00004 /* matches one of the PP bits */
  21 #define _PAGE_EXEC              0x00008 /* No execute on POWER4 and newer (we invert) */
  22 #define _PAGE_GUARDED           0x00010
  23 /* We can derive Memory coherence from _PAGE_NO_CACHE */
  24 #define _PAGE_COHERENT          0x0
  25 #define _PAGE_NO_CACHE          0x00020 /* I: cache inhibit */
  26 #define _PAGE_WRITETHRU         0x00040 /* W: cache write-through */
  27 #define _PAGE_DIRTY             0x00080 /* C: page changed */
  28 #define _PAGE_ACCESSED          0x00100 /* R: page referenced */
  29 #define _PAGE_RW                0x00200 /* software: user write access allowed */
  30 #define _PAGE_HASHPTE           0x00400 /* software: pte has an associated HPTE */
  31 #define _PAGE_BUSY              0x00800 /* software: PTE & hash are busy */
  32 #define _PAGE_F_GIX             0x07000 /* full page: hidx bits */
  33 #define _PAGE_F_GIX_SHIFT       12
  34 #define _PAGE_F_SECOND          0x08000 /* Whether to use secondary hash or not */
  35 #define _PAGE_SPECIAL           0x10000 /* software: special page */
  36
  37 #ifdef CONFIG_MEM_SOFT_DIRTY
  38 #define _PAGE_SOFT_DIRTY        0x20000 /* software: software dirty tracking */
  39 #else
  40 #define _PAGE_SOFT_DIRTY        0x00000
  41 #endif
  42
  43 /*
  44  * THP pages can't be special. So use the _PAGE_SPECIAL
  45  */
  46 #define _PAGE_SPLITTING _PAGE_SPECIAL
  47
  48 /*
  49  * We need to differentiate between explicit huge page and THP huge
  50  * page, since THP huge page also need to track real subpage details
  51  */
  52 #define _PAGE_THP_HUGE  _PAGE_4K_PFN
  53
  54 /*
  55  * set of bits not changed in pmd_modify.
  56  */
  57 #define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS |               \
  58                          _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_SPLITTING | \
  59                          _PAGE_THP_HUGE | _PAGE_PTE | _PAGE_SOFT_DIRTY)
  60
  61 #ifdef CONFIG_PPC_64K_PAGES
  62 #include <asm/book3s/64/hash-64k.h>
  63 #else
  64 #include <asm/book3s/64/hash-4k.h>
  65 #endif
  66
  67 /*
  68  * Size of EA range mapped by our pagetables.
  69  */
  70 #define PGTABLE_EADDR_SIZE      (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
  71                                  PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
  72 #define PGTABLE_RANGE           (ASM_CONST(1) << PGTABLE_EADDR_SIZE)
  73
  74 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
  75 #define PMD_CACHE_INDEX (PMD_INDEX_SIZE + 1)
  76 #else
  77 #define PMD_CACHE_INDEX PMD_INDEX_SIZE
  78 #endif
  79 /*
  80  * Define the address range of the kernel non-linear virtual area
  81  */
  82 #define KERN_VIRT_START ASM_CONST(0xD000000000000000)
  83 #define KERN_VIRT_SIZE  ASM_CONST(0x0000100000000000)
  84
  85 /*
  86  * The vmalloc space starts at the beginning of that region, and
  87  * occupies half of it on hash CPUs and a quarter of it on Book3E
  88  * (we keep a quarter for the virtual memmap)
  89  */
  90 #define VMALLOC_START   KERN_VIRT_START
  91 #define VMALLOC_SIZE    (KERN_VIRT_SIZE >> 1)
  92 #define VMALLOC_END     (VMALLOC_START + VMALLOC_SIZE)
  93
  94 /*
  95  * Region IDs
  96  */
  97 #define REGION_SHIFT            60UL
  98 #define REGION_MASK             (0xfUL << REGION_SHIFT)
  99 #define REGION_ID(ea)           (((unsigned long)(ea)) >> REGION_SHIFT)
 100
 101 #define VMALLOC_REGION_ID       (REGION_ID(VMALLOC_START))
 102 #define KERNEL_REGION_ID        (REGION_ID(PAGE_OFFSET))
 103 #define VMEMMAP_REGION_ID       (0xfUL) /* Server only */
 104 #define USER_REGION_ID          (0UL)
 105
 106 /*
 107  * Defines the address of the vmemap area, in its own region on
 108  * hash table CPUs.
 109  */
 110 #define VMEMMAP_BASE            (VMEMMAP_REGION_ID << REGION_SHIFT)
 111
 112 #ifdef CONFIG_PPC_MM_SLICES
 113 #define HAVE_ARCH_UNMAPPED_AREA
 114 #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
 115 #endif /* CONFIG_PPC_MM_SLICES */
 116
 117 /* No separate kernel read-only */
 118 #define _PAGE_KERNEL_RW         (_PAGE_RW | _PAGE_DIRTY) /* user access blocked by key */
 119 #define _PAGE_KERNEL_RO          _PAGE_KERNEL_RW
 120 #define _PAGE_KERNEL_RWX        (_PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC)
 121
 122 /* Strong Access Ordering */
 123 #define _PAGE_SAO               (_PAGE_WRITETHRU | _PAGE_NO_CACHE | _PAGE_COHERENT)
 124
 125 /* No page size encoding in the linux PTE */
 126 #define _PAGE_PSIZE             0
 127
 128 /* PTEIDX nibble */
 129 #define _PTEIDX_SECONDARY       0x8
 130 #define _PTEIDX_GROUP_IX        0x7
 131
 132 /* Hash table based platforms need atomic updates of the linux PTE */
 133 #define PTE_ATOMIC_UPDATES      1
 134 #define _PTE_NONE_MASK  _PAGE_HPTEFLAGS
 135 /*
 136  * The mask convered by the RPN must be a ULL on 32-bit platforms with
 137  * 64-bit PTEs
 138  */
 139 #define PTE_RPN_MASK    (~((1UL << PTE_RPN_SHIFT) - 1))
 140 /*
 141  * _PAGE_CHG_MASK masks of bits that are to be preserved across
 142  * pgprot changes
 143  */
 144 #define _PAGE_CHG_MASK  (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
 145                          _PAGE_ACCESSED | _PAGE_SPECIAL | _PAGE_PTE | \
 146                          _PAGE_SOFT_DIRTY)
 147 /*
 148  * Mask of bits returned by pte_pgprot()
 149  */
 150 #define PAGE_PROT_BITS  (_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \
 151                          _PAGE_WRITETHRU | _PAGE_4K_PFN | \
 152                          _PAGE_USER | _PAGE_ACCESSED |  \
 153                          _PAGE_RW |  _PAGE_DIRTY | _PAGE_EXEC | \
 154                          _PAGE_SOFT_DIRTY)
 155 /*
 156  * We define 2 sets of base prot bits, one for basic pages (ie,
 157  * cacheable kernel and user pages) and one for non cacheable
 158  * pages. We always set _PAGE_COHERENT when SMP is enabled or
 159  * the processor might need it for DMA coherency.
 160  */
 161 #define _PAGE_BASE_NC   (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
 162 #define _PAGE_BASE      (_PAGE_BASE_NC | _PAGE_COHERENT)
 163
 164 /* Permission masks used to generate the __P and __S table,
 165  *
 166  * Note:__pgprot is defined in arch/powerpc/include/asm/page.h
 167  *
 168  * Write permissions imply read permissions for now (we could make write-only
 169  * pages on BookE but we don't bother for now). Execute permission control is
 170  * possible on platforms that define _PAGE_EXEC
 171  *
 172  * Note due to the way vm flags are laid out, the bits are XWR
 173  */
 174 #define PAGE_NONE       __pgprot(_PAGE_BASE)
 175 #define PAGE_SHARED     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
 176 #define PAGE_SHARED_X   __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | \
 177                                  _PAGE_EXEC)
 178 #define PAGE_COPY       __pgprot(_PAGE_BASE | _PAGE_USER )
 179 #define PAGE_COPY_X     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
 180 #define PAGE_READONLY   __pgprot(_PAGE_BASE | _PAGE_USER )
 181 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
 182
 183 #define __P000  PAGE_NONE
 184 #define __P001  PAGE_READONLY
 185 #define __P010  PAGE_COPY
 186 #define __P011  PAGE_COPY
 187 #define __P100  PAGE_READONLY_X
 188 #define __P101  PAGE_READONLY_X
 189 #define __P110  PAGE_COPY_X
 190 #define __P111  PAGE_COPY_X
 191
 192 #define __S000  PAGE_NONE
 193 #define __S001  PAGE_READONLY
 194 #define __S010  PAGE_SHARED
 195 #define __S011  PAGE_SHARED
 196 #define __S100  PAGE_READONLY_X
 197 #define __S101  PAGE_READONLY_X
 198 #define __S110  PAGE_SHARED_X
 199 #define __S111  PAGE_SHARED_X
 200
 201 /* Permission masks used for kernel mappings */
 202 #define PAGE_KERNEL     __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)
 203 #define PAGE_KERNEL_NC  __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
 204                                  _PAGE_NO_CACHE)
 205 #define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
 206                                  _PAGE_NO_CACHE | _PAGE_GUARDED)
 207 #define PAGE_KERNEL_X   __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
 208 #define PAGE_KERNEL_RO  __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
 209 #define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
 210
 211 /* Protection used for kernel text. We want the debuggers to be able to
 212  * set breakpoints anywhere, so don't write protect the kernel text
 213  * on platforms where such control is possible.
 214  */
 215 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH) ||\
 216         defined(CONFIG_KPROBES) || defined(CONFIG_DYNAMIC_FTRACE)
 217 #define PAGE_KERNEL_TEXT        PAGE_KERNEL_X
 218 #else
 219 #define PAGE_KERNEL_TEXT        PAGE_KERNEL_ROX
 220 #endif
 221
 222 /* Make modules code happy. We don't set RO yet */
 223 #define PAGE_KERNEL_EXEC        PAGE_KERNEL_X
 224 #define PAGE_AGP                (PAGE_KERNEL_NC)
 225
 226 #define PMD_BAD_BITS            (PTE_TABLE_SIZE-1)
 227 #define PUD_BAD_BITS            (PMD_TABLE_SIZE-1)
 228
 229 #ifndef __ASSEMBLY__
 230 #define pmd_bad(pmd)            (!is_kernel_addr(pmd_val(pmd)) \
 231                                  || (pmd_val(pmd) & PMD_BAD_BITS))
 232 #define pmd_page_vaddr(pmd)     (pmd_val(pmd) & ~PMD_MASKED_BITS)
 233
 234 #define pud_bad(pud)            (!is_kernel_addr(pud_val(pud)) \
 235                                  || (pud_val(pud) & PUD_BAD_BITS))
 236 #define pud_page_vaddr(pud)     (pud_val(pud) & ~PUD_MASKED_BITS)
 237
 238 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1))
 239 #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1))
 240 #define pte_index(address) (((address) >> (PAGE_SHIFT)) & (PTRS_PER_PTE - 1))
 241
 242 extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
 243                             pte_t *ptep, unsigned long pte, int huge);
 244 extern unsigned long htab_convert_pte_flags(unsigned long pteflags);
 245 /* Atomic PTE updates */
 246 static inline unsigned long pte_update(struct mm_struct *mm,
 247                                        unsigned long addr,
 248                                        pte_t *ptep, unsigned long clr,
 249                                        unsigned long set,
 250                                        int huge)
 251 {
 252         unsigned long old, tmp;
 253
 254         __asm__ __volatile__(
 255         "1:     ldarx   %0,0,%3         # pte_update\n\
 256         andi.   %1,%0,%6\n\
 257         bne-    1b \n\
 258         andc    %1,%0,%4 \n\
 259         or      %1,%1,%7\n\
 260         stdcx.  %1,0,%3 \n\
 261         bne-    1b"
 262         : "=&r" (old), "=&r" (tmp), "=m" (*ptep)
 263         : "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY), "r" (set)
 264         : "cc" );
 265         /* huge pages use the old page table lock */
 266         if (!huge)
 267                 assert_pte_locked(mm, addr);
 268
 269         if (old & _PAGE_HASHPTE)
 270                 hpte_need_flush(mm, addr, ptep, old, huge);
 271
 272         return old;
 273 }
 274
 275 static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
 276                                               unsigned long addr, pte_t *ptep)
 277 {
 278         unsigned long old;
 279
 280         if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
 281                 return 0;
 282         old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0, 0);
 283         return (old & _PAGE_ACCESSED) != 0;
 284 }
 285 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 286 #define ptep_test_and_clear_young(__vma, __addr, __ptep)                   \
 287 ({                                                                         \
 288         int __r;                                                           \
 289         __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
 290         __r;                                                               \
 291 })
 292
 293 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
 294 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
 295                                       pte_t *ptep)
 296 {
 297
 298         if ((pte_val(*ptep) & _PAGE_RW) == 0)
 299                 return;
 300
 301         pte_update(mm, addr, ptep, _PAGE_RW, 0, 0);
 302 }
 303
 304 static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
 305                                            unsigned long addr, pte_t *ptep)
 306 {
 307         if ((pte_val(*ptep) & _PAGE_RW) == 0)
 308                 return;
 309
 310         pte_update(mm, addr, ptep, _PAGE_RW, 0, 1);
 311 }
 312
 313 /*
 314  * We currently remove entries from the hashtable regardless of whether
 315  * the entry was young or dirty. The generic routines only flush if the
 316  * entry was young or dirty which is not good enough.
 317  *
 318  * We should be more intelligent about this but for the moment we override
 319  * these functions and force a tlb flush unconditionally
 320  */
 321 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
 322 #define ptep_clear_flush_young(__vma, __address, __ptep)                \
 323 ({                                                                      \
 324         int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \
 325                                                   __ptep);              \
 326         __young;                                                        \
 327 })
 328
 329 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 330 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
 331                                        unsigned long addr, pte_t *ptep)
 332 {
 333         unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0, 0);
 334         return __pte(old);
 335 }
 336
 337 static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
 338                              pte_t * ptep)
 339 {
 340         pte_update(mm, addr, ptep, ~0UL, 0, 0);
 341 }
 342
 343
 344 /* Set the dirty and/or accessed bits atomically in a linux PTE, this
 345  * function doesn't need to flush the hash entry
 346  */
 347 static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
 348 {
 349         unsigned long bits = pte_val(entry) &
 350                 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC |
 351                  _PAGE_SOFT_DIRTY);
 352
 353         unsigned long old, tmp;
 354
 355         __asm__ __volatile__(
 356         "1:     ldarx   %0,0,%4\n\
 357                 andi.   %1,%0,%6\n\
 358                 bne-    1b \n\
 359                 or      %0,%3,%0\n\
 360                 stdcx.  %0,0,%4\n\
 361                 bne-    1b"
 362         :"=&r" (old), "=&r" (tmp), "=m" (*ptep)
 363         :"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
 364         :"cc");
 365 }
 366
 367 #define __HAVE_ARCH_PTE_SAME
 368 #define pte_same(A,B)   (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
 369
 370 /* Generic accessors to PTE bits */
 371 static inline int pte_write(pte_t pte)          { return !!(pte_val(pte) & _PAGE_RW);}
 372 static inline int pte_dirty(pte_t pte)          { return !!(pte_val(pte) & _PAGE_DIRTY); }
 373 static inline int pte_young(pte_t pte)          { return !!(pte_val(pte) & _PAGE_ACCESSED); }
 374 static inline int pte_special(pte_t pte)        { return !!(pte_val(pte) & _PAGE_SPECIAL); }
 375 static inline int pte_none(pte_t pte)           { return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; }
 376 static inline pgprot_t pte_pgprot(pte_t pte)    { return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }
 377
 378 #ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
 379 static inline bool pte_soft_dirty(pte_t pte)
 380 {
 381         return !!(pte_val(pte) & _PAGE_SOFT_DIRTY);
 382 }
 383 static inline pte_t pte_mksoft_dirty(pte_t pte)
 384 {
 385         return __pte(pte_val(pte) | _PAGE_SOFT_DIRTY);
 386 }
 387
 388 static inline pte_t pte_clear_soft_dirty(pte_t pte)
 389 {
 390         return __pte(pte_val(pte) & ~_PAGE_SOFT_DIRTY);
 391 }
 392 #endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
 393
 394 #ifdef CONFIG_NUMA_BALANCING
 395 /*
 396  * These work without NUMA balancing but the kernel does not care. See the
 397  * comment in include/asm-generic/pgtable.h . On powerpc, this will only
 398  * work for user pages and always return true for kernel pages.
 399  */
 400 static inline int pte_protnone(pte_t pte)
 401 {
 402         return (pte_val(pte) &
 403                 (_PAGE_PRESENT | _PAGE_USER)) == _PAGE_PRESENT;
 404 }
 405 #endif /* CONFIG_NUMA_BALANCING */
 406
 407 static inline int pte_present(pte_t pte)
 408 {
 409         return pte_val(pte) & _PAGE_PRESENT;
 410 }
 411
 412 /* Conversion functions: convert a page and protection to a page entry,
 413  * and a page entry and page directory to the page they refer to.
 414  *
 415  * Even if PTEs can be unsigned long long, a PFN is always an unsigned
 416  * long for now.
 417  */
 418 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
 419 {
 420         return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) |
 421                      pgprot_val(pgprot));
 422 }
 423
 424 static inline unsigned long pte_pfn(pte_t pte)
 425 {
 426         return pte_val(pte) >> PTE_RPN_SHIFT;
 427 }
 428
 429 /* Generic modifiers for PTE bits */
 430 static inline pte_t pte_wrprotect(pte_t pte)
 431 {
 432         return __pte(pte_val(pte) & ~_PAGE_RW);
 433 }
 434
 435 static inline pte_t pte_mkclean(pte_t pte)
 436 {
 437         return __pte(pte_val(pte) & ~_PAGE_DIRTY);
 438 }
 439
 440 static inline pte_t pte_mkold(pte_t pte)
 441 {
 442         return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
 443 }
 444
 445 static inline pte_t pte_mkwrite(pte_t pte)
 446 {
 447         return __pte(pte_val(pte) | _PAGE_RW);
 448 }
 449
 450 static inline pte_t pte_mkdirty(pte_t pte)
 451 {
 452         return __pte(pte_val(pte) | _PAGE_DIRTY | _PAGE_SOFT_DIRTY);
 453 }
 454
 455 static inline pte_t pte_mkyoung(pte_t pte)
 456 {
 457         return __pte(pte_val(pte) | _PAGE_ACCESSED);
 458 }
 459
 460 static inline pte_t pte_mkspecial(pte_t pte)
 461 {
 462         return __pte(pte_val(pte) | _PAGE_SPECIAL);
 463 }
 464
 465 static inline pte_t pte_mkhuge(pte_t pte)
 466 {
 467         return pte;
 468 }
 469
 470 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 471 {
 472         return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
 473 }
 474
 475 /* This low level function performs the actual PTE insertion
 476  * Setting the PTE depends on the MMU type and other factors. It's
 477  * an horrible mess that I'm not going to try to clean up now but
 478  * I'm keeping it in one place rather than spread around
 479  */
 480 static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
 481                                 pte_t *ptep, pte_t pte, int percpu)
 482 {
 483         /*
 484          * Anything else just stores the PTE normally. That covers all 64-bit
 485          * cases, and 32-bit non-hash with 32-bit PTEs.
 486          */
 487         *ptep = pte;
 488 }
 489
 490 /*
 491  * Macro to mark a page protection value as "uncacheable".
 492  */
 493
 494 #define _PAGE_CACHE_CTL (_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \
 495                          _PAGE_WRITETHRU)
 496
 497 #define pgprot_noncached pgprot_noncached
 498 static inline pgprot_t pgprot_noncached(pgprot_t prot)
 499 {
 500         return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
 501                         _PAGE_NO_CACHE | _PAGE_GUARDED);
 502 }
 503
 504 #define pgprot_noncached_wc pgprot_noncached_wc
 505 static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)
 506 {
 507         return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
 508                         _PAGE_NO_CACHE);
 509 }
 510
 511 #define pgprot_cached pgprot_cached
 512 static inline pgprot_t pgprot_cached(pgprot_t prot)
 513 {
 514         return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
 515                         _PAGE_COHERENT);
 516 }
 517
 518 #define pgprot_cached_wthru pgprot_cached_wthru
 519 static inline pgprot_t pgprot_cached_wthru(pgprot_t prot)
 520 {
 521         return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |
 522                         _PAGE_COHERENT | _PAGE_WRITETHRU);
 523 }
 524
 525 #define pgprot_cached_noncoherent pgprot_cached_noncoherent
 526 static inline pgprot_t pgprot_cached_noncoherent(pgprot_t prot)
 527 {
 528         return __pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL);
 529 }
 530
 531 #define pgprot_writecombine pgprot_writecombine
 532 static inline pgprot_t pgprot_writecombine(pgprot_t prot)
 533 {
 534         return pgprot_noncached_wc(prot);
 535 }
 536
 537 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
 538 extern void hpte_do_hugepage_flush(struct mm_struct *mm, unsigned long addr,
 539                                    pmd_t *pmdp, unsigned long old_pmd);
 540 #else
 541 static inline void hpte_do_hugepage_flush(struct mm_struct *mm,
 542                                           unsigned long addr, pmd_t *pmdp,
 543                                           unsigned long old_pmd)
 544 {
 545         WARN(1, "%s called with THP disabled\n", __func__);
 546 }
 547 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
 548
 549 #endif /* !__ASSEMBLY__ */
 550 #endif /* __KERNEL__ */
 551 #endif /* _ASM_POWERPC_BOOK3S_64_HASH_H */