arch/powerpc/kernel/idle_book3s.S

   1 /*
   2  *  This file contains idle entry/exit functions for POWER7,
   3  *  POWER8 and POWER9 CPUs.
   4  *
   5  *  This program is free software; you can redistribute it and/or
   6  *  modify it under the terms of the GNU General Public License
   7  *  as published by the Free Software Foundation; either version
   8  *  2 of the License, or (at your option) any later version.
   9  */
  10
  11 #include <linux/threads.h>
  12 #include <asm/processor.h>
  13 #include <asm/page.h>
  14 #include <asm/cputable.h>
  15 #include <asm/thread_info.h>
  16 #include <asm/ppc_asm.h>
  17 #include <asm/asm-offsets.h>
  18 #include <asm/ppc-opcode.h>
  19 #include <asm/hw_irq.h>
  20 #include <asm/kvm_book3s_asm.h>
  21 #include <asm/opal.h>
  22 #include <asm/cpuidle.h>
  23 #include <asm/book3s/64/mmu-hash.h>
  24 #include <asm/mmu.h>
  25
  26 #undef DEBUG
  27
  28 /*
  29  * Use unused space in the interrupt stack to save and restore
  30  * registers for winkle support.
  31  */
  32 #define _SDR1   GPR3
  33 #define _RPR    GPR4
  34 #define _SPURR  GPR5
  35 #define _PURR   GPR6
  36 #define _TSCR   GPR7
  37 #define _DSCR   GPR8
  38 #define _AMOR   GPR9
  39 #define _WORT   GPR10
  40 #define _WORC   GPR11
  41 #define _PTCR   GPR12
  42
  43 #define PSSCR_HV_TEMPLATE       PSSCR_ESL | PSSCR_EC | \
  44                                 PSSCR_PSLL_MASK | PSSCR_TR_MASK | \
  45                                 PSSCR_MTL_MASK
  46
  47         .text
  48
  49 /*
  50  * Used by threads before entering deep idle states. Saves SPRs
  51  * in interrupt stack frame
  52  */
  53 save_sprs_to_stack:
  54         /*
  55          * Note all register i.e per-core, per-subcore or per-thread is saved
  56          * here since any thread in the core might wake up first
  57          */
  58 BEGIN_FTR_SECTION
  59         mfspr   r3,SPRN_PTCR
  60         std     r3,_PTCR(r1)
  61         /*
  62          * Note - SDR1 is dropped in Power ISA v3. Hence not restoring
  63          * SDR1 here
  64          */
  65 FTR_SECTION_ELSE
  66         mfspr   r3,SPRN_SDR1
  67         std     r3,_SDR1(r1)
  68 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
  69         mfspr   r3,SPRN_RPR
  70         std     r3,_RPR(r1)
  71         mfspr   r3,SPRN_SPURR
  72         std     r3,_SPURR(r1)
  73         mfspr   r3,SPRN_PURR
  74         std     r3,_PURR(r1)
  75         mfspr   r3,SPRN_TSCR
  76         std     r3,_TSCR(r1)
  77         mfspr   r3,SPRN_DSCR
  78         std     r3,_DSCR(r1)
  79         mfspr   r3,SPRN_AMOR
  80         std     r3,_AMOR(r1)
  81         mfspr   r3,SPRN_WORT
  82         std     r3,_WORT(r1)
  83         mfspr   r3,SPRN_WORC
  84         std     r3,_WORC(r1)
  85
  86         blr
  87
  88 /*
  89  * Used by threads when the lock bit of core_idle_state is set.
  90  * Threads will spin in HMT_LOW until the lock bit is cleared.
  91  * r14 - pointer to core_idle_state
  92  * r15 - used to load contents of core_idle_state
  93  */
  94
  95 core_idle_lock_held:
  96         HMT_LOW
  97 3:      lwz     r15,0(r14)
  98         andi.   r15,r15,PNV_CORE_IDLE_LOCK_BIT
  99         bne     3b
 100         HMT_MEDIUM
 101         lwarx   r15,0,r14
 102         blr
 103
 104 /*
 105  * Pass requested state in r3:
 106  *      r3 - PNV_THREAD_NAP/SLEEP/WINKLE in POWER8
 107  *         - Requested STOP state in POWER9
 108  *
 109  * To check IRQ_HAPPENED in r4
 110  *      0 - don't check
 111  *      1 - check
 112  *
 113  * Address to 'rfid' to in r5
 114  */
 115 _GLOBAL(pnv_powersave_common)
 116         /* Use r3 to pass state nap/sleep/winkle */
 117         /* NAP is a state loss, we create a regs frame on the
 118          * stack, fill it up with the state we care about and
 119          * stick a pointer to it in PACAR1. We really only
 120          * need to save PC, some CR bits and the NV GPRs,
 121          * but for now an interrupt frame will do.
 122          */
 123         mflr    r0
 124         std     r0,16(r1)
 125         stdu    r1,-INT_FRAME_SIZE(r1)
 126         std     r0,_LINK(r1)
 127         std     r0,_NIP(r1)
 128
 129         /* Hard disable interrupts */
 130         mfmsr   r9
 131         rldicl  r9,r9,48,1
 132         rotldi  r9,r9,16
 133         mtmsrd  r9,1                    /* hard-disable interrupts */
 134
 135         /* Check if something happened while soft-disabled */
 136         lbz     r0,PACAIRQHAPPENED(r13)
 137         andi.   r0,r0,~PACA_IRQ_HARD_DIS@l
 138         beq     1f
 139         cmpwi   cr0,r4,0
 140         beq     1f
 141         addi    r1,r1,INT_FRAME_SIZE
 142         ld      r0,16(r1)
 143         li      r3,0                    /* Return 0 (no nap) */
 144         mtlr    r0
 145         blr
 146
 147 1:      /* We mark irqs hard disabled as this is the state we'll
 148          * be in when returning and we need to tell arch_local_irq_restore()
 149          * about it
 150          */
 151         li      r0,PACA_IRQ_HARD_DIS
 152         stb     r0,PACAIRQHAPPENED(r13)
 153
 154         /* We haven't lost state ... yet */
 155         li      r0,0
 156         stb     r0,PACA_NAPSTATELOST(r13)
 157
 158         /* Continue saving state */
 159         SAVE_GPR(2, r1)
 160         SAVE_NVGPRS(r1)
 161         mfcr    r4
 162         std     r4,_CCR(r1)
 163         std     r9,_MSR(r1)
 164         std     r1,PACAR1(r13)
 165
 166 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
 167         /* Tell KVM we're entering idle */
 168         li      r4,KVM_HWTHREAD_IN_IDLE
 169         stb     r4,HSTATE_HWTHREAD_STATE(r13)
 170 #endif
 171
 172         /*
 173          * Go to real mode to do the nap, as required by the architecture.
 174          * Also, we need to be in real mode before setting hwthread_state,
 175          * because as soon as we do that, another thread can switch
 176          * the MMU context to the guest.
 177          */
 178         LOAD_REG_IMMEDIATE(r7, MSR_IDLE)
 179         li      r6, MSR_RI
 180         andc    r6, r9, r6
 181         mtmsrd  r6, 1           /* clear RI before setting SRR0/1 */
 182         mtspr   SPRN_SRR0, r5
 183         mtspr   SPRN_SRR1, r7
 184         rfid
 185
 186         .globl pnv_enter_arch207_idle_mode
 187 pnv_enter_arch207_idle_mode:
 188         stb     r3,PACA_THREAD_IDLE_STATE(r13)
 189         cmpwi   cr3,r3,PNV_THREAD_SLEEP
 190         bge     cr3,2f
 191         IDLE_STATE_ENTER_SEQ(PPC_NAP)
 192         /* No return */
 193 2:
 194         /* Sleep or winkle */
 195         lbz     r7,PACA_THREAD_MASK(r13)
 196         ld      r14,PACA_CORE_IDLE_STATE_PTR(r13)
 197 lwarx_loop1:
 198         lwarx   r15,0,r14
 199
 200         andi.   r9,r15,PNV_CORE_IDLE_LOCK_BIT
 201         bnel    core_idle_lock_held
 202
 203         andc    r15,r15,r7                      /* Clear thread bit */
 204
 205         andi.   r15,r15,PNV_CORE_IDLE_THREAD_BITS
 206
 207 /*
 208  * If cr0 = 0, then current thread is the last thread of the core entering
 209  * sleep. Last thread needs to execute the hardware bug workaround code if
 210  * required by the platform.
 211  * Make the workaround call unconditionally here. The below branch call is
 212  * patched out when the idle states are discovered if the platform does not
 213  * require it.
 214  */
 215 .global pnv_fastsleep_workaround_at_entry
 216 pnv_fastsleep_workaround_at_entry:
 217         beq     fastsleep_workaround_at_entry
 218
 219         stwcx.  r15,0,r14
 220         bne-    lwarx_loop1
 221         isync
 222
 223 common_enter: /* common code for all the threads entering sleep or winkle */
 224         bgt     cr3,enter_winkle
 225         IDLE_STATE_ENTER_SEQ(PPC_SLEEP)
 226
 227 fastsleep_workaround_at_entry:
 228         ori     r15,r15,PNV_CORE_IDLE_LOCK_BIT
 229         stwcx.  r15,0,r14
 230         bne-    lwarx_loop1
 231         isync
 232
 233         /* Fast sleep workaround */
 234         li      r3,1
 235         li      r4,1
 236         bl      opal_rm_config_cpu_idle_state
 237
 238         /* Clear Lock bit */
 239         li      r0,0
 240         lwsync
 241         stw     r0,0(r14)
 242         b       common_enter
 243
 244 enter_winkle:
 245         bl      save_sprs_to_stack
 246
 247         IDLE_STATE_ENTER_SEQ(PPC_WINKLE)
 248
 249 /*
 250  * r3 - requested stop state
 251  */
 252 power_enter_stop:
 253 /*
 254  * Check if the requested state is a deep idle state.
 255  */
 256         LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
 257         ld      r4,ADDROFF(pnv_first_deep_stop_state)(r5)
 258         cmpd    r3,r4
 259         bge     2f
 260         IDLE_STATE_ENTER_SEQ(PPC_STOP)
 261 2:
 262 /*
 263  * Entering deep idle state.
 264  * Clear thread bit in PACA_CORE_IDLE_STATE, save SPRs to
 265  * stack and enter stop
 266  */
 267         lbz     r7,PACA_THREAD_MASK(r13)
 268         ld      r14,PACA_CORE_IDLE_STATE_PTR(r13)
 269
 270 lwarx_loop_stop:
 271         lwarx   r15,0,r14
 272         andi.   r9,r15,PNV_CORE_IDLE_LOCK_BIT
 273         bnel    core_idle_lock_held
 274         andc    r15,r15,r7                      /* Clear thread bit */
 275
 276         stwcx.  r15,0,r14
 277         bne-    lwarx_loop_stop
 278         isync
 279
 280         bl      save_sprs_to_stack
 281
 282         IDLE_STATE_ENTER_SEQ(PPC_STOP)
 283
 284 _GLOBAL(power7_idle)
 285         /* Now check if user or arch enabled NAP mode */
 286         LOAD_REG_ADDRBASE(r3,powersave_nap)
 287         lwz     r4,ADDROFF(powersave_nap)(r3)
 288         cmpwi   0,r4,0
 289         beqlr
 290         li      r3, 1
 291         /* fall through */
 292
 293 _GLOBAL(power7_nap)
 294         mr      r4,r3
 295         li      r3,PNV_THREAD_NAP
 296         LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
 297         b       pnv_powersave_common
 298         /* No return */
 299
 300 _GLOBAL(power7_sleep)
 301         li      r3,PNV_THREAD_SLEEP
 302         li      r4,1
 303         LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
 304         b       pnv_powersave_common
 305         /* No return */
 306
 307 _GLOBAL(power7_winkle)
 308         li      r3,PNV_THREAD_WINKLE
 309         li      r4,1
 310         LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
 311         b       pnv_powersave_common
 312         /* No return */
 313
 314 #define CHECK_HMI_INTERRUPT                                             \
 315         mfspr   r0,SPRN_SRR1;                                           \
 316 BEGIN_FTR_SECTION_NESTED(66);                                           \
 317         rlwinm  r0,r0,45-31,0xf;  /* extract wake reason field (P8) */  \
 318 FTR_SECTION_ELSE_NESTED(66);                                            \
 319         rlwinm  r0,r0,45-31,0xe;  /* P7 wake reason field is 3 bits */  \
 320 ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66);                \
 321         cmpwi   r0,0xa;                 /* Hypervisor maintenance ? */  \
 322         bne     20f;                                                    \
 323         /* Invoke opal call to handle hmi */                            \
 324         ld      r2,PACATOC(r13);                                        \
 325         ld      r1,PACAR1(r13);                                         \
 326         std     r3,ORIG_GPR3(r1);       /* Save original r3 */          \
 327         li      r3,0;                   /* NULL argument */             \
 328         bl      hmi_exception_realmode;                                 \
 329         nop;                                                            \
 330         ld      r3,ORIG_GPR3(r1);       /* Restore original r3 */       \
 331 20:     nop;
 332
 333
 334 /*
 335  * r3 - requested stop state
 336  */
 337 _GLOBAL(power9_idle_stop)
 338         LOAD_REG_IMMEDIATE(r4, PSSCR_HV_TEMPLATE)
 339         or      r4,r4,r3
 340         mtspr   SPRN_PSSCR, r4
 341         li      r4, 1
 342         LOAD_REG_ADDR(r5,power_enter_stop)
 343         b       pnv_powersave_common
 344         /* No return */
 345 /*
 346  * Called from reset vector. Check whether we have woken up with
 347  * hypervisor state loss. If yes, restore hypervisor state and return
 348  * back to reset vector.
 349  *
 350  * r13 - Contents of HSPRG0
 351  * cr3 - set to gt if waking up with partial/complete hypervisor state loss
 352  */
 353 _GLOBAL(pnv_restore_hyp_resource)
 354 BEGIN_FTR_SECTION
 355         ld      r2,PACATOC(r13);
 356         /*
 357          * POWER ISA 3. Use PSSCR to determine if we
 358          * are waking up from deep idle state
 359          */
 360         LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
 361         ld      r4,ADDROFF(pnv_first_deep_stop_state)(r5)
 362
 363         mfspr   r5,SPRN_PSSCR
 364         /*
 365          * 0-3 bits correspond to Power-Saving Level Status
 366          * which indicates the idle state we are waking up from
 367          */
 368         rldicl  r5,r5,4,60
 369         cmpd    cr4,r5,r4
 370         bge     cr4,pnv_wakeup_tb_loss
 371         /*
 372          * Waking up without hypervisor state loss. Return to
 373          * reset vector
 374          */
 375         blr
 376
 377 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
 378
 379         /*
 380          * POWER ISA 2.07 or less.
 381          * Check if last bit of HSPGR0 is set. This indicates whether we are
 382          * waking up from winkle.
 383          */
 384         clrldi  r5,r13,63
 385         clrrdi  r13,r13,1
 386
 387         /* Now that we are sure r13 is corrected, load TOC */
 388         ld      r2,PACATOC(r13);
 389         cmpwi   cr4,r5,1
 390         mtspr   SPRN_HSPRG0,r13
 391
 392         lbz     r0,PACA_THREAD_IDLE_STATE(r13)
 393         cmpwi   cr2,r0,PNV_THREAD_NAP
 394         bgt     cr2,pnv_wakeup_tb_loss  /* Either sleep or Winkle */
 395
 396         /*
 397          * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking
 398          * up from nap. At this stage CR3 shouldn't contains 'gt' since that
 399          * indicates we are waking with hypervisor state loss from nap.
 400          */
 401         bgt     cr3,.
 402
 403         blr     /* Return back to System Reset vector from where
 404                    pnv_restore_hyp_resource was invoked */
 405
 406 /*
 407  * Called if waking up from idle state which can cause either partial or
 408  * complete hyp state loss.
 409  * In POWER8, called if waking up from fastsleep or winkle
 410  * In POWER9, called if waking up from stop state >= pnv_first_deep_stop_state
 411  *
 412  * r13 - PACA
 413  * cr3 - gt if waking up with partial/complete hypervisor state loss
 414  * cr4 - eq if waking up from complete hypervisor state loss.
 415  */
 416 _GLOBAL(pnv_wakeup_tb_loss)
 417         ld      r1,PACAR1(r13)
 418         /*
 419          * Before entering any idle state, the NVGPRs are saved in the stack
 420          * and they are restored before switching to the process context. Hence
 421          * until they are restored, they are free to be used.
 422          *
 423          * Save SRR1 and LR in NVGPRs as they might be clobbered in
 424          * opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required
 425          * to determine the wakeup reason if we branch to kvm_start_guest. LR
 426          * is required to return back to reset vector after hypervisor state
 427          * restore is complete.
 428          */
 429         mflr    r17
 430         mfspr   r16,SPRN_SRR1
 431 BEGIN_FTR_SECTION
 432         CHECK_HMI_INTERRUPT
 433 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
 434
 435         lbz     r7,PACA_THREAD_MASK(r13)
 436         ld      r14,PACA_CORE_IDLE_STATE_PTR(r13)
 437 lwarx_loop2:
 438         lwarx   r15,0,r14
 439         andi.   r9,r15,PNV_CORE_IDLE_LOCK_BIT
 440         /*
 441          * Lock bit is set in one of the 2 cases-
 442          * a. In the sleep/winkle enter path, the last thread is executing
 443          * fastsleep workaround code.
 444          * b. In the wake up path, another thread is executing fastsleep
 445          * workaround undo code or resyncing timebase or restoring context
 446          * In either case loop until the lock bit is cleared.
 447          */
 448         bnel    core_idle_lock_held
 449
 450         cmpwi   cr2,r15,0
 451
 452         /*
 453          * At this stage
 454          * cr2 - eq if first thread to wakeup in core
 455          * cr3-  gt if waking up with partial/complete hypervisor state loss
 456          * cr4 - eq if waking up from complete hypervisor state loss.
 457          */
 458
 459         ori     r15,r15,PNV_CORE_IDLE_LOCK_BIT
 460         stwcx.  r15,0,r14
 461         bne-    lwarx_loop2
 462         isync
 463
 464 BEGIN_FTR_SECTION
 465         lbz     r4,PACA_SUBCORE_SIBLING_MASK(r13)
 466         and     r4,r4,r15
 467         cmpwi   r4,0    /* Check if first in subcore */
 468
 469         or      r15,r15,r7              /* Set thread bit */
 470         beq     first_thread_in_subcore
 471 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
 472
 473         or      r15,r15,r7              /* Set thread bit */
 474         beq     cr2,first_thread_in_core
 475
 476         /* Not first thread in core or subcore to wake up */
 477         b       clear_lock
 478
 479 first_thread_in_subcore:
 480         /*
 481          * If waking up from sleep, subcore state is not lost. Hence
 482          * skip subcore state restore
 483          */
 484         bne     cr4,subcore_state_restored
 485
 486         /* Restore per-subcore state */
 487         ld      r4,_SDR1(r1)
 488         mtspr   SPRN_SDR1,r4
 489
 490         ld      r4,_RPR(r1)
 491         mtspr   SPRN_RPR,r4
 492         ld      r4,_AMOR(r1)
 493         mtspr   SPRN_AMOR,r4
 494
 495 subcore_state_restored:
 496         /*
 497          * Check if the thread is also the first thread in the core. If not,
 498          * skip to clear_lock.
 499          */
 500         bne     cr2,clear_lock
 501
 502 first_thread_in_core:
 503
 504         /*
 505          * First thread in the core waking up from any state which can cause
 506          * partial or complete hypervisor state loss. It needs to
 507          * call the fastsleep workaround code if the platform requires it.
 508          * Call it unconditionally here. The below branch instruction will
 509          * be patched out if the platform does not have fastsleep or does not
 510          * require the workaround. Patching will be performed during the
 511          * discovery of idle-states.
 512          */
 513 .global pnv_fastsleep_workaround_at_exit
 514 pnv_fastsleep_workaround_at_exit:
 515         b       fastsleep_workaround_at_exit
 516
 517 timebase_resync:
 518         /*
 519          * Use cr3 which indicates that we are waking up with atleast partial
 520          * hypervisor state loss to determine if TIMEBASE RESYNC is needed.
 521          */
 522         ble     cr3,clear_lock
 523         /* Time base re-sync */
 524         bl      opal_rm_resync_timebase;
 525         /*
 526          * If waking up from sleep, per core state is not lost, skip to
 527          * clear_lock.
 528          */
 529         bne     cr4,clear_lock
 530
 531         /*
 532          * First thread in the core to wake up and its waking up with
 533          * complete hypervisor state loss. Restore per core hypervisor
 534          * state.
 535          */
 536 BEGIN_FTR_SECTION
 537         ld      r4,_PTCR(r1)
 538         mtspr   SPRN_PTCR,r4
 539         ld      r4,_RPR(r1)
 540         mtspr   SPRN_RPR,r4
 541 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
 542
 543         ld      r4,_TSCR(r1)
 544         mtspr   SPRN_TSCR,r4
 545         ld      r4,_WORC(r1)
 546         mtspr   SPRN_WORC,r4
 547
 548 clear_lock:
 549         andi.   r15,r15,PNV_CORE_IDLE_THREAD_BITS
 550         lwsync
 551         stw     r15,0(r14)
 552
 553 common_exit:
 554         /*
 555          * Common to all threads.
 556          *
 557          * If waking up from sleep, hypervisor state is not lost. Hence
 558          * skip hypervisor state restore.
 559          */
 560         bne     cr4,hypervisor_state_restored
 561
 562         /* Waking up from winkle */
 563
 564 BEGIN_MMU_FTR_SECTION
 565         b       no_segments
 566 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
 567         /* Restore SLB  from PACA */
 568         ld      r8,PACA_SLBSHADOWPTR(r13)
 569
 570         .rept   SLB_NUM_BOLTED
 571         li      r3, SLBSHADOW_SAVEAREA
 572         LDX_BE  r5, r8, r3
 573         addi    r3, r3, 8
 574         LDX_BE  r6, r8, r3
 575         andis.  r7,r5,SLB_ESID_V@h
 576         beq     1f
 577         slbmte  r6,r5
 578 1:      addi    r8,r8,16
 579         .endr
 580 no_segments:
 581
 582         /* Restore per thread state */
 583
 584         ld      r4,_SPURR(r1)
 585         mtspr   SPRN_SPURR,r4
 586         ld      r4,_PURR(r1)
 587         mtspr   SPRN_PURR,r4
 588         ld      r4,_DSCR(r1)
 589         mtspr   SPRN_DSCR,r4
 590         ld      r4,_WORT(r1)
 591         mtspr   SPRN_WORT,r4
 592
 593         /* Call cur_cpu_spec->cpu_restore() */
 594         LOAD_REG_ADDR(r4, cur_cpu_spec)
 595         ld      r4,0(r4)
 596         ld      r12,CPU_SPEC_RESTORE(r4)
 597 #ifdef PPC64_ELF_ABI_v1
 598         ld      r12,0(r12)
 599 #endif
 600         mtctr   r12
 601         bctrl
 602
 603 hypervisor_state_restored:
 604
 605         mtspr   SPRN_SRR1,r16
 606         mtlr    r17
 607         blr     /* Return back to System Reset vector from where
 608                    pnv_restore_hyp_resource was invoked */
 609
 610 fastsleep_workaround_at_exit:
 611         li      r3,1
 612         li      r4,0
 613         bl      opal_rm_config_cpu_idle_state
 614         b       timebase_resync
 615
 616 /*
 617  * R3 here contains the value that will be returned to the caller
 618  * of power7_nap.
 619  */
 620 _GLOBAL(pnv_wakeup_loss)
 621         ld      r1,PACAR1(r13)
 622 BEGIN_FTR_SECTION
 623         CHECK_HMI_INTERRUPT
 624 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
 625         REST_NVGPRS(r1)
 626         REST_GPR(2, r1)
 627         ld      r6,_CCR(r1)
 628         ld      r4,_MSR(r1)
 629         ld      r5,_NIP(r1)
 630         addi    r1,r1,INT_FRAME_SIZE
 631         mtcr    r6
 632         mtspr   SPRN_SRR1,r4
 633         mtspr   SPRN_SRR0,r5
 634         rfid
 635
 636 /*
 637  * R3 here contains the value that will be returned to the caller
 638  * of power7_nap.
 639  */
 640 _GLOBAL(pnv_wakeup_noloss)
 641         lbz     r0,PACA_NAPSTATELOST(r13)
 642         cmpwi   r0,0
 643         bne     pnv_wakeup_loss
 644 BEGIN_FTR_SECTION
 645         CHECK_HMI_INTERRUPT
 646 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
 647         ld      r1,PACAR1(r13)
 648         ld      r6,_CCR(r1)
 649         ld      r4,_MSR(r1)
 650         ld      r5,_NIP(r1)
 651         addi    r1,r1,INT_FRAME_SIZE
 652         mtcr    r6
 653         mtspr   SPRN_SRR1,r4
 654         mtspr   SPRN_SRR0,r5
 655         rfid