arch/powerpc/kernel/setup_32.c

   1 /*
   2  * Common prep/pmac/chrp boot and setup code.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/string.h>
   7 #include <linux/sched.h>
   8 #include <linux/init.h>
   9 #include <linux/kernel.h>
  10 #include <linux/reboot.h>
  11 #include <linux/delay.h>
  12 #include <linux/initrd.h>
  13 #include <linux/tty.h>
  14 #include <linux/seq_file.h>
  15 #include <linux/root_dev.h>
  16 #include <linux/cpu.h>
  17 #include <linux/console.h>
  18 #include <linux/memblock.h>
  19
  20 #include <asm/io.h>
  21 #include <asm/prom.h>
  22 #include <asm/processor.h>
  23 #include <asm/pgtable.h>
  24 #include <asm/setup.h>
  25 #include <asm/smp.h>
  26 #include <asm/elf.h>
  27 #include <asm/cputable.h>
  28 #include <asm/bootx.h>
  29 #include <asm/btext.h>
  30 #include <asm/machdep.h>
  31 #include <asm/uaccess.h>
  32 #include <asm/pmac_feature.h>
  33 #include <asm/sections.h>
  34 #include <asm/nvram.h>
  35 #include <asm/xmon.h>
  36 #include <asm/time.h>
  37 #include <asm/serial.h>
  38 #include <asm/udbg.h>
  39 #include <asm/code-patching.h>
  40 #include <asm/cpu_has_feature.h>
  41
  42 #define DBG(fmt...)
  43
  44 extern void bootx_init(unsigned long r4, unsigned long phys);
  45
  46 int boot_cpuid_phys;
  47 EXPORT_SYMBOL_GPL(boot_cpuid_phys);
  48
  49 int smp_hw_index[NR_CPUS];
  50
  51 unsigned long ISA_DMA_THRESHOLD;
  52 unsigned int DMA_MODE_READ;
  53 unsigned int DMA_MODE_WRITE;
  54
  55 /*
  56  * These are used in binfmt_elf.c to put aux entries on the stack
  57  * for each elf executable being started.
  58  */
  59 int dcache_bsize;
  60 int icache_bsize;
  61 int ucache_bsize;
  62
  63 /*
  64  * We're called here very early in the boot.
  65  *
  66  * Note that the kernel may be running at an address which is different
  67  * from the address that it was linked at, so we must use RELOC/PTRRELOC
  68  * to access static data (including strings).  -- paulus
  69  */
  70 notrace unsigned long __init early_init(unsigned long dt_ptr)
  71 {
  72         unsigned long offset = reloc_offset();
  73
  74         /* First zero the BSS -- use memset_io, some platforms don't have
  75          * caches on yet */
  76         memset_io((void __iomem *)PTRRELOC(&__bss_start), 0,
  77                         __bss_stop - __bss_start);
  78
  79         /*
  80          * Identify the CPU type and fix up code sections
  81          * that depend on which cpu we have.
  82          */
  83         identify_cpu(offset, mfspr(SPRN_PVR));
  84
  85         apply_feature_fixups();
  86
  87         return KERNELBASE + offset;
  88 }
  89
  90
  91 /*
  92  * This is run before start_kernel(), the kernel has been relocated
  93  * and we are running with enough of the MMU enabled to have our
  94  * proper kernel virtual addresses
  95  *
  96  * We do the initial parsing of the flat device-tree and prepares
  97  * for the MMU to be fully initialized.
  98  */
  99 extern unsigned int memset_nocache_branch; /* Insn to be replaced by NOP */
 100
 101 notrace void __init machine_init(u64 dt_ptr)
 102 {
 103         /* Configure static keys first, now that we're relocated. */
 104         setup_feature_keys();
 105
 106         /* Enable early debugging if any specified (see udbg.h) */
 107         udbg_early_init();
 108
 109         patch_instruction((unsigned int *)&memcpy, PPC_INST_NOP);
 110         patch_instruction(&memset_nocache_branch, PPC_INST_NOP);
 111
 112         /* Do some early initialization based on the flat device tree */
 113         early_init_devtree(__va(dt_ptr));
 114
 115         early_init_mmu();
 116
 117         setup_kdump_trampoline();
 118 }
 119
 120 /* Checks "l2cr=xxxx" command-line option */
 121 int __init ppc_setup_l2cr(char *str)
 122 {
 123         if (cpu_has_feature(CPU_FTR_L2CR)) {
 124                 unsigned long val = simple_strtoul(str, NULL, 0);
 125                 printk(KERN_INFO "l2cr set to %lx\n", val);
 126                 _set_L2CR(0);           /* force invalidate by disable cache */
 127                 _set_L2CR(val);         /* and enable it */
 128         }
 129         return 1;
 130 }
 131 __setup("l2cr=", ppc_setup_l2cr);
 132
 133 /* Checks "l3cr=xxxx" command-line option */
 134 int __init ppc_setup_l3cr(char *str)
 135 {
 136         if (cpu_has_feature(CPU_FTR_L3CR)) {
 137                 unsigned long val = simple_strtoul(str, NULL, 0);
 138                 printk(KERN_INFO "l3cr set to %lx\n", val);
 139                 _set_L3CR(val);         /* and enable it */
 140         }
 141         return 1;
 142 }
 143 __setup("l3cr=", ppc_setup_l3cr);
 144
 145 #ifdef CONFIG_GENERIC_NVRAM
 146
 147 /* Generic nvram hooks used by drivers/char/gen_nvram.c */
 148 unsigned char nvram_read_byte(int addr)
 149 {
 150         if (ppc_md.nvram_read_val)
 151                 return ppc_md.nvram_read_val(addr);
 152         return 0xff;
 153 }
 154 EXPORT_SYMBOL(nvram_read_byte);
 155
 156 void nvram_write_byte(unsigned char val, int addr)
 157 {
 158         if (ppc_md.nvram_write_val)
 159                 ppc_md.nvram_write_val(addr, val);
 160 }
 161 EXPORT_SYMBOL(nvram_write_byte);
 162
 163 ssize_t nvram_get_size(void)
 164 {
 165         if (ppc_md.nvram_size)
 166                 return ppc_md.nvram_size();
 167         return -1;
 168 }
 169 EXPORT_SYMBOL(nvram_get_size);
 170
 171 void nvram_sync(void)
 172 {
 173         if (ppc_md.nvram_sync)
 174                 ppc_md.nvram_sync();
 175 }
 176 EXPORT_SYMBOL(nvram_sync);
 177
 178 #endif /* CONFIG_NVRAM */
 179
 180 int __init ppc_init(void)
 181 {
 182         /* clear the progress line */
 183         if (ppc_md.progress)
 184                 ppc_md.progress("             ", 0xffff);
 185
 186         /* call platform init */
 187         if (ppc_md.init != NULL) {
 188                 ppc_md.init();
 189         }
 190         return 0;
 191 }
 192
 193 arch_initcall(ppc_init);
 194
 195 void __init irqstack_early_init(void)
 196 {
 197         unsigned int i;
 198
 199         /* interrupt stacks must be in lowmem, we get that for free on ppc32
 200          * as the memblock is limited to lowmem by default */
 201         for_each_possible_cpu(i) {
 202                 softirq_ctx[i] = (struct thread_info *)
 203                         __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
 204                 hardirq_ctx[i] = (struct thread_info *)
 205                         __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
 206         }
 207 }
 208
 209 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
 210 void __init exc_lvl_early_init(void)
 211 {
 212         unsigned int i, hw_cpu;
 213
 214         /* interrupt stacks must be in lowmem, we get that for free on ppc32
 215          * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */
 216         for_each_possible_cpu(i) {
 217 #ifdef CONFIG_SMP
 218                 hw_cpu = get_hard_smp_processor_id(i);
 219 #else
 220                 hw_cpu = 0;
 221 #endif
 222
 223                 critirq_ctx[hw_cpu] = (struct thread_info *)
 224                         __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
 225 #ifdef CONFIG_BOOKE
 226                 dbgirq_ctx[hw_cpu] = (struct thread_info *)
 227                         __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
 228                 mcheckirq_ctx[hw_cpu] = (struct thread_info *)
 229                         __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
 230 #endif
 231         }
 232 }
 233 #endif
 234
 235 void __init setup_power_save(void)
 236 {
 237 #ifdef CONFIG_6xx
 238         if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
 239             cpu_has_feature(CPU_FTR_CAN_NAP))
 240                 ppc_md.power_save = ppc6xx_idle;
 241 #endif
 242
 243 #ifdef CONFIG_E500
 244         if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
 245             cpu_has_feature(CPU_FTR_CAN_NAP))
 246                 ppc_md.power_save = e500_idle;
 247 #endif
 248 }
 249
 250 __init void initialize_cache_info(void)
 251 {
 252         /*
 253          * Set cache line size based on type of cpu as a default.
 254          * Systems with OF can look in the properties on the cpu node(s)
 255          * for a possibly more accurate value.
 256          */
 257         dcache_bsize = cur_cpu_spec->dcache_bsize;
 258         icache_bsize = cur_cpu_spec->icache_bsize;
 259         ucache_bsize = 0;
 260         if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE))
 261                 ucache_bsize = icache_bsize = dcache_bsize;
 262 }