m68knommu: fix user a5 register being overwritten
[deliverable/linux.git] / arch / powerpc / kernel / setup_32.c
1 /*
2 * Common prep/pmac/chrp boot and setup code.
3 */
4
5 #include <linux/module.h>
6 #include <linux/string.h>
7 #include <linux/sched.h>
8 #include <linux/init.h>
9 #include <linux/kernel.h>
10 #include <linux/reboot.h>
11 #include <linux/delay.h>
12 #include <linux/initrd.h>
13 #include <linux/tty.h>
14 #include <linux/seq_file.h>
15 #include <linux/root_dev.h>
16 #include <linux/cpu.h>
17 #include <linux/console.h>
18 #include <linux/memblock.h>
19
20 #include <asm/io.h>
21 #include <asm/prom.h>
22 #include <asm/processor.h>
23 #include <asm/pgtable.h>
24 #include <asm/setup.h>
25 #include <asm/smp.h>
26 #include <asm/elf.h>
27 #include <asm/cputable.h>
28 #include <asm/bootx.h>
29 #include <asm/btext.h>
30 #include <asm/machdep.h>
31 #include <asm/uaccess.h>
32 #include <asm/pmac_feature.h>
33 #include <asm/sections.h>
34 #include <asm/nvram.h>
35 #include <asm/xmon.h>
36 #include <asm/time.h>
37 #include <asm/serial.h>
38 #include <asm/udbg.h>
39 #include <asm/code-patching.h>
40 #include <asm/cpu_has_feature.h>
41
42 #define DBG(fmt...)
43
44 extern void bootx_init(unsigned long r4, unsigned long phys);
45
46 int boot_cpuid_phys;
47 EXPORT_SYMBOL_GPL(boot_cpuid_phys);
48
49 int smp_hw_index[NR_CPUS];
50
51 unsigned long ISA_DMA_THRESHOLD;
52 unsigned int DMA_MODE_READ;
53 unsigned int DMA_MODE_WRITE;
54
55 /*
56 * These are used in binfmt_elf.c to put aux entries on the stack
57 * for each elf executable being started.
58 */
59 int dcache_bsize;
60 int icache_bsize;
61 int ucache_bsize;
62
63 /*
64 * We're called here very early in the boot.
65 *
66 * Note that the kernel may be running at an address which is different
67 * from the address that it was linked at, so we must use RELOC/PTRRELOC
68 * to access static data (including strings). -- paulus
69 */
70 notrace unsigned long __init early_init(unsigned long dt_ptr)
71 {
72 unsigned long offset = reloc_offset();
73
74 /* First zero the BSS -- use memset_io, some platforms don't have
75 * caches on yet */
76 memset_io((void __iomem *)PTRRELOC(&__bss_start), 0,
77 __bss_stop - __bss_start);
78
79 /*
80 * Identify the CPU type and fix up code sections
81 * that depend on which cpu we have.
82 */
83 identify_cpu(offset, mfspr(SPRN_PVR));
84
85 apply_feature_fixups();
86
87 return KERNELBASE + offset;
88 }
89
90
91 /*
92 * This is run before start_kernel(), the kernel has been relocated
93 * and we are running with enough of the MMU enabled to have our
94 * proper kernel virtual addresses
95 *
96 * Find out what kind of machine we're on and save any data we need
97 * from the early boot process (devtree is copied on pmac by prom_init()).
98 * This is called very early on the boot process, after a minimal
99 * MMU environment has been set up but before MMU_init is called.
100 */
101 extern unsigned int memset_nocache_branch; /* Insn to be replaced by NOP */
102
103 notrace void __init machine_init(u64 dt_ptr)
104 {
105 /* Enable early debugging if any specified (see udbg.h) */
106 udbg_early_init();
107
108 patch_instruction((unsigned int *)&memcpy, PPC_INST_NOP);
109 patch_instruction(&memset_nocache_branch, PPC_INST_NOP);
110
111 /* Do some early initialization based on the flat device tree */
112 early_init_devtree(__va(dt_ptr));
113
114 early_init_mmu();
115
116 setup_kdump_trampoline();
117 }
118
119 /* Checks "l2cr=xxxx" command-line option */
120 int __init ppc_setup_l2cr(char *str)
121 {
122 if (cpu_has_feature(CPU_FTR_L2CR)) {
123 unsigned long val = simple_strtoul(str, NULL, 0);
124 printk(KERN_INFO "l2cr set to %lx\n", val);
125 _set_L2CR(0); /* force invalidate by disable cache */
126 _set_L2CR(val); /* and enable it */
127 }
128 return 1;
129 }
130 __setup("l2cr=", ppc_setup_l2cr);
131
132 /* Checks "l3cr=xxxx" command-line option */
133 int __init ppc_setup_l3cr(char *str)
134 {
135 if (cpu_has_feature(CPU_FTR_L3CR)) {
136 unsigned long val = simple_strtoul(str, NULL, 0);
137 printk(KERN_INFO "l3cr set to %lx\n", val);
138 _set_L3CR(val); /* and enable it */
139 }
140 return 1;
141 }
142 __setup("l3cr=", ppc_setup_l3cr);
143
144 #ifdef CONFIG_GENERIC_NVRAM
145
146 /* Generic nvram hooks used by drivers/char/gen_nvram.c */
147 unsigned char nvram_read_byte(int addr)
148 {
149 if (ppc_md.nvram_read_val)
150 return ppc_md.nvram_read_val(addr);
151 return 0xff;
152 }
153 EXPORT_SYMBOL(nvram_read_byte);
154
155 void nvram_write_byte(unsigned char val, int addr)
156 {
157 if (ppc_md.nvram_write_val)
158 ppc_md.nvram_write_val(addr, val);
159 }
160 EXPORT_SYMBOL(nvram_write_byte);
161
162 ssize_t nvram_get_size(void)
163 {
164 if (ppc_md.nvram_size)
165 return ppc_md.nvram_size();
166 return -1;
167 }
168 EXPORT_SYMBOL(nvram_get_size);
169
170 void nvram_sync(void)
171 {
172 if (ppc_md.nvram_sync)
173 ppc_md.nvram_sync();
174 }
175 EXPORT_SYMBOL(nvram_sync);
176
177 #endif /* CONFIG_NVRAM */
178
179 int __init ppc_init(void)
180 {
181 /* clear the progress line */
182 if (ppc_md.progress)
183 ppc_md.progress(" ", 0xffff);
184
185 /* call platform init */
186 if (ppc_md.init != NULL) {
187 ppc_md.init();
188 }
189 return 0;
190 }
191
192 arch_initcall(ppc_init);
193
194 void __init irqstack_early_init(void)
195 {
196 unsigned int i;
197
198 /* interrupt stacks must be in lowmem, we get that for free on ppc32
199 * as the memblock is limited to lowmem by default */
200 for_each_possible_cpu(i) {
201 softirq_ctx[i] = (struct thread_info *)
202 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
203 hardirq_ctx[i] = (struct thread_info *)
204 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
205 }
206 }
207
208 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
209 void __init exc_lvl_early_init(void)
210 {
211 unsigned int i, hw_cpu;
212
213 /* interrupt stacks must be in lowmem, we get that for free on ppc32
214 * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */
215 for_each_possible_cpu(i) {
216 #ifdef CONFIG_SMP
217 hw_cpu = get_hard_smp_processor_id(i);
218 #else
219 hw_cpu = 0;
220 #endif
221
222 critirq_ctx[hw_cpu] = (struct thread_info *)
223 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
224 #ifdef CONFIG_BOOKE
225 dbgirq_ctx[hw_cpu] = (struct thread_info *)
226 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
227 mcheckirq_ctx[hw_cpu] = (struct thread_info *)
228 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
229 #endif
230 }
231 }
232 #endif
233
234 void __init setup_power_save(void)
235 {
236 #ifdef CONFIG_6xx
237 if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
238 cpu_has_feature(CPU_FTR_CAN_NAP))
239 ppc_md.power_save = ppc6xx_idle;
240 #endif
241
242 #ifdef CONFIG_E500
243 if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
244 cpu_has_feature(CPU_FTR_CAN_NAP))
245 ppc_md.power_save = e500_idle;
246 #endif
247 }
248
249 __init void initialize_cache_info(void)
250 {
251 /*
252 * Set cache line size based on type of cpu as a default.
253 * Systems with OF can look in the properties on the cpu node(s)
254 * for a possibly more accurate value.
255 */
256 dcache_bsize = cur_cpu_spec->dcache_bsize;
257 icache_bsize = cur_cpu_spec->icache_bsize;
258 ucache_bsize = 0;
259 if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE))
260 ucache_bsize = icache_bsize = dcache_bsize;
261 }
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