2 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
3 * {mikejc|engebret}@us.ibm.com
5 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 * SMP scalability work:
8 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
13 * PowerPC Hashed Page Table functions
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/sched.h>
27 #include <linux/proc_fs.h>
28 #include <linux/stat.h>
29 #include <linux/sysctl.h>
30 #include <linux/export.h>
31 #include <linux/ctype.h>
32 #include <linux/cache.h>
33 #include <linux/init.h>
34 #include <linux/signal.h>
35 #include <linux/memblock.h>
36 #include <linux/context_tracking.h>
37 #include <linux/libfdt.h>
39 #include <asm/processor.h>
40 #include <asm/pgtable.h>
42 #include <asm/mmu_context.h>
44 #include <asm/types.h>
45 #include <asm/uaccess.h>
46 #include <asm/machdep.h>
48 #include <asm/tlbflush.h>
52 #include <asm/cacheflush.h>
53 #include <asm/cputable.h>
54 #include <asm/sections.h>
55 #include <asm/copro.h>
57 #include <asm/code-patching.h>
58 #include <asm/fadump.h>
59 #include <asm/firmware.h>
61 #include <asm/trace.h>
65 #define DBG(fmt...) udbg_printf(fmt)
71 #define DBG_LOW(fmt...) udbg_printf(fmt)
73 #define DBG_LOW(fmt...)
81 * Note: pte --> Linux PTE
82 * HPTE --> PowerPC Hashed Page Table Entry
85 * htab_initialize is called with the MMU off (of course), but
86 * the kernel has been copied down to zero so it can directly
87 * reference global data. At this point it is very difficult
88 * to print debug info.
92 static unsigned long _SDR1
;
93 struct mmu_psize_def mmu_psize_defs
[MMU_PAGE_COUNT
];
94 EXPORT_SYMBOL_GPL(mmu_psize_defs
);
96 u8 hpte_page_sizes
[1 << LP_BITS
];
97 EXPORT_SYMBOL_GPL(hpte_page_sizes
);
99 struct hash_pte
*htab_address
;
100 unsigned long htab_size_bytes
;
101 unsigned long htab_hash_mask
;
102 EXPORT_SYMBOL_GPL(htab_hash_mask
);
103 int mmu_linear_psize
= MMU_PAGE_4K
;
104 EXPORT_SYMBOL_GPL(mmu_linear_psize
);
105 int mmu_virtual_psize
= MMU_PAGE_4K
;
106 int mmu_vmalloc_psize
= MMU_PAGE_4K
;
107 #ifdef CONFIG_SPARSEMEM_VMEMMAP
108 int mmu_vmemmap_psize
= MMU_PAGE_4K
;
110 int mmu_io_psize
= MMU_PAGE_4K
;
111 int mmu_kernel_ssize
= MMU_SEGSIZE_256M
;
112 EXPORT_SYMBOL_GPL(mmu_kernel_ssize
);
113 int mmu_highuser_ssize
= MMU_SEGSIZE_256M
;
114 u16 mmu_slb_size
= 64;
115 EXPORT_SYMBOL_GPL(mmu_slb_size
);
116 #ifdef CONFIG_PPC_64K_PAGES
117 int mmu_ci_restrictions
;
119 #ifdef CONFIG_DEBUG_PAGEALLOC
120 static u8
*linear_map_hash_slots
;
121 static unsigned long linear_map_hash_count
;
122 static DEFINE_SPINLOCK(linear_map_hash_lock
);
123 #endif /* CONFIG_DEBUG_PAGEALLOC */
124 struct mmu_hash_ops mmu_hash_ops
;
125 EXPORT_SYMBOL(mmu_hash_ops
);
127 /* There are definitions of page sizes arrays to be used when none
128 * is provided by the firmware.
131 /* Pre-POWER4 CPUs (4k pages only)
133 static struct mmu_psize_def mmu_psize_defaults_old
[] = {
137 .penc
= {[MMU_PAGE_4K
] = 0, [1 ... MMU_PAGE_COUNT
- 1] = -1},
143 /* POWER4, GPUL, POWER5
145 * Support for 16Mb large pages
147 static struct mmu_psize_def mmu_psize_defaults_gp
[] = {
151 .penc
= {[MMU_PAGE_4K
] = 0, [1 ... MMU_PAGE_COUNT
- 1] = -1},
158 .penc
= {[0 ... MMU_PAGE_16M
- 1] = -1, [MMU_PAGE_16M
] = 0,
159 [MMU_PAGE_16M
+ 1 ... MMU_PAGE_COUNT
- 1] = -1 },
166 * 'R' and 'C' update notes:
167 * - Under pHyp or KVM, the updatepp path will not set C, thus it *will*
168 * create writeable HPTEs without C set, because the hcall H_PROTECT
169 * that we use in that case will not update C
170 * - The above is however not a problem, because we also don't do that
171 * fancy "no flush" variant of eviction and we use H_REMOVE which will
172 * do the right thing and thus we don't have the race I described earlier
174 * - Under bare metal, we do have the race, so we need R and C set
175 * - We make sure R is always set and never lost
176 * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping
178 unsigned long htab_convert_pte_flags(unsigned long pteflags
)
180 unsigned long rflags
= 0;
182 /* _PAGE_EXEC -> NOEXEC */
183 if ((pteflags
& _PAGE_EXEC
) == 0)
187 * Linux uses slb key 0 for kernel and 1 for user.
188 * kernel RW areas are mapped with PPP=0b000
189 * User area is mapped with PPP=0b010 for read/write
190 * or PPP=0b011 for read-only (including writeable but clean pages).
192 if (pteflags
& _PAGE_PRIVILEGED
) {
194 * Kernel read only mapped with ppp bits 0b110
196 if (!(pteflags
& _PAGE_WRITE
))
197 rflags
|= (HPTE_R_PP0
| 0x2);
199 if (pteflags
& _PAGE_RWX
)
201 if (!((pteflags
& _PAGE_WRITE
) && (pteflags
& _PAGE_DIRTY
)))
205 * We can't allow hardware to update hpte bits. Hence always
206 * set 'R' bit and set 'C' if it is a write fault
210 if (pteflags
& _PAGE_DIRTY
)
216 if ((pteflags
& _PAGE_CACHE_CTL
) == _PAGE_TOLERANT
)
218 else if ((pteflags
& _PAGE_CACHE_CTL
) == _PAGE_NON_IDEMPOTENT
)
219 rflags
|= (HPTE_R_I
| HPTE_R_G
);
220 else if ((pteflags
& _PAGE_CACHE_CTL
) == _PAGE_SAO
)
221 rflags
|= (HPTE_R_W
| HPTE_R_I
| HPTE_R_M
);
224 * Add memory coherence if cache inhibited is not set
231 int htab_bolt_mapping(unsigned long vstart
, unsigned long vend
,
232 unsigned long pstart
, unsigned long prot
,
233 int psize
, int ssize
)
235 unsigned long vaddr
, paddr
;
236 unsigned int step
, shift
;
239 shift
= mmu_psize_defs
[psize
].shift
;
242 prot
= htab_convert_pte_flags(prot
);
244 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
245 vstart
, vend
, pstart
, prot
, psize
, ssize
);
247 for (vaddr
= vstart
, paddr
= pstart
; vaddr
< vend
;
248 vaddr
+= step
, paddr
+= step
) {
249 unsigned long hash
, hpteg
;
250 unsigned long vsid
= get_kernel_vsid(vaddr
, ssize
);
251 unsigned long vpn
= hpt_vpn(vaddr
, vsid
, ssize
);
252 unsigned long tprot
= prot
;
255 * If we hit a bad address return error.
259 /* Make kernel text executable */
260 if (overlaps_kernel_text(vaddr
, vaddr
+ step
))
263 /* Make kvm guest trampolines executable */
264 if (overlaps_kvm_tmp(vaddr
, vaddr
+ step
))
268 * If relocatable, check if it overlaps interrupt vectors that
269 * are copied down to real 0. For relocatable kernel
270 * (e.g. kdump case) we copy interrupt vectors down to real
271 * address 0. Mark that region as executable. This is
272 * because on p8 system with relocation on exception feature
273 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
274 * in order to execute the interrupt handlers in virtual
275 * mode the vector region need to be marked as executable.
277 if ((PHYSICAL_START
> MEMORY_START
) &&
278 overlaps_interrupt_vector_text(vaddr
, vaddr
+ step
))
281 hash
= hpt_hash(vpn
, shift
, ssize
);
282 hpteg
= ((hash
& htab_hash_mask
) * HPTES_PER_GROUP
);
284 BUG_ON(!mmu_hash_ops
.hpte_insert
);
285 ret
= mmu_hash_ops
.hpte_insert(hpteg
, vpn
, paddr
, tprot
,
286 HPTE_V_BOLTED
, psize
, psize
,
292 #ifdef CONFIG_DEBUG_PAGEALLOC
293 if (debug_pagealloc_enabled() &&
294 (paddr
>> PAGE_SHIFT
) < linear_map_hash_count
)
295 linear_map_hash_slots
[paddr
>> PAGE_SHIFT
] = ret
| 0x80;
296 #endif /* CONFIG_DEBUG_PAGEALLOC */
298 return ret
< 0 ? ret
: 0;
301 int htab_remove_mapping(unsigned long vstart
, unsigned long vend
,
302 int psize
, int ssize
)
305 unsigned int step
, shift
;
309 shift
= mmu_psize_defs
[psize
].shift
;
312 if (!mmu_hash_ops
.hpte_removebolted
)
315 for (vaddr
= vstart
; vaddr
< vend
; vaddr
+= step
) {
316 rc
= mmu_hash_ops
.hpte_removebolted(vaddr
, psize
, ssize
);
328 static bool disable_1tb_segments
= false;
330 static int __init
parse_disable_1tb_segments(char *p
)
332 disable_1tb_segments
= true;
335 early_param("disable_1tb_segments", parse_disable_1tb_segments
);
337 static int __init
htab_dt_scan_seg_sizes(unsigned long node
,
338 const char *uname
, int depth
,
341 const char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
345 /* We are scanning "cpu" nodes only */
346 if (type
== NULL
|| strcmp(type
, "cpu") != 0)
349 prop
= of_get_flat_dt_prop(node
, "ibm,processor-segment-sizes", &size
);
352 for (; size
>= 4; size
-= 4, ++prop
) {
353 if (be32_to_cpu(prop
[0]) == 40) {
354 DBG("1T segment support detected\n");
356 if (disable_1tb_segments
) {
357 DBG("1T segments disabled by command line\n");
361 cur_cpu_spec
->mmu_features
|= MMU_FTR_1T_SEGMENT
;
365 cur_cpu_spec
->mmu_features
&= ~MMU_FTR_NO_SLBIE_B
;
369 static int __init
get_idx_from_shift(unsigned int shift
)
393 static int __init
htab_dt_scan_page_sizes(unsigned long node
,
394 const char *uname
, int depth
,
397 const char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
401 /* We are scanning "cpu" nodes only */
402 if (type
== NULL
|| strcmp(type
, "cpu") != 0)
405 prop
= of_get_flat_dt_prop(node
, "ibm,segment-page-sizes", &size
);
409 pr_info("Page sizes from device-tree:\n");
411 cur_cpu_spec
->mmu_features
&= ~(MMU_FTR_16M_PAGE
);
413 unsigned int base_shift
= be32_to_cpu(prop
[0]);
414 unsigned int slbenc
= be32_to_cpu(prop
[1]);
415 unsigned int lpnum
= be32_to_cpu(prop
[2]);
416 struct mmu_psize_def
*def
;
419 size
-= 3; prop
+= 3;
420 base_idx
= get_idx_from_shift(base_shift
);
422 /* skip the pte encoding also */
423 prop
+= lpnum
* 2; size
-= lpnum
* 2;
426 def
= &mmu_psize_defs
[base_idx
];
427 if (base_idx
== MMU_PAGE_16M
)
428 cur_cpu_spec
->mmu_features
|= MMU_FTR_16M_PAGE
;
430 def
->shift
= base_shift
;
431 if (base_shift
<= 23)
434 def
->avpnm
= (1 << (base_shift
- 23)) - 1;
437 * We don't know for sure what's up with tlbiel, so
438 * for now we only set it for 4K and 64K pages
440 if (base_idx
== MMU_PAGE_4K
|| base_idx
== MMU_PAGE_64K
)
445 while (size
> 0 && lpnum
) {
446 unsigned int shift
= be32_to_cpu(prop
[0]);
447 int penc
= be32_to_cpu(prop
[1]);
449 prop
+= 2; size
-= 2;
452 idx
= get_idx_from_shift(shift
);
457 pr_err("Invalid penc for base_shift=%d "
458 "shift=%d\n", base_shift
, shift
);
460 def
->penc
[idx
] = penc
;
461 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
462 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
463 base_shift
, shift
, def
->sllp
,
464 def
->avpnm
, def
->tlbiel
, def
->penc
[idx
]);
471 #ifdef CONFIG_HUGETLB_PAGE
472 /* Scan for 16G memory blocks that have been set aside for huge pages
473 * and reserve those blocks for 16G huge pages.
475 static int __init
htab_dt_scan_hugepage_blocks(unsigned long node
,
476 const char *uname
, int depth
,
478 const char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
479 const __be64
*addr_prop
;
480 const __be32
*page_count_prop
;
481 unsigned int expected_pages
;
482 long unsigned int phys_addr
;
483 long unsigned int block_size
;
485 /* We are scanning "memory" nodes only */
486 if (type
== NULL
|| strcmp(type
, "memory") != 0)
489 /* This property is the log base 2 of the number of virtual pages that
490 * will represent this memory block. */
491 page_count_prop
= of_get_flat_dt_prop(node
, "ibm,expected#pages", NULL
);
492 if (page_count_prop
== NULL
)
494 expected_pages
= (1 << be32_to_cpu(page_count_prop
[0]));
495 addr_prop
= of_get_flat_dt_prop(node
, "reg", NULL
);
496 if (addr_prop
== NULL
)
498 phys_addr
= be64_to_cpu(addr_prop
[0]);
499 block_size
= be64_to_cpu(addr_prop
[1]);
500 if (block_size
!= (16 * GB
))
502 printk(KERN_INFO
"Huge page(16GB) memory: "
503 "addr = 0x%lX size = 0x%lX pages = %d\n",
504 phys_addr
, block_size
, expected_pages
);
505 if (phys_addr
+ (16 * GB
) <= memblock_end_of_DRAM()) {
506 memblock_reserve(phys_addr
, block_size
* expected_pages
);
507 add_gpage(phys_addr
, block_size
, expected_pages
);
511 #endif /* CONFIG_HUGETLB_PAGE */
513 static void mmu_psize_set_default_penc(void)
516 for (bpsize
= 0; bpsize
< MMU_PAGE_COUNT
; bpsize
++)
517 for (apsize
= 0; apsize
< MMU_PAGE_COUNT
; apsize
++)
518 mmu_psize_defs
[bpsize
].penc
[apsize
] = -1;
521 #ifdef CONFIG_PPC_64K_PAGES
523 static bool might_have_hea(void)
526 * The HEA ethernet adapter requires awareness of the
527 * GX bus. Without that awareness we can easily assume
528 * we will never see an HEA ethernet device.
530 #ifdef CONFIG_IBMEBUS
531 return !cpu_has_feature(CPU_FTR_ARCH_207S
) &&
532 !firmware_has_feature(FW_FEATURE_SPLPAR
);
538 #endif /* #ifdef CONFIG_PPC_64K_PAGES */
540 static void __init
htab_scan_page_sizes(void)
544 /* se the invalid penc to -1 */
545 mmu_psize_set_default_penc();
547 /* Default to 4K pages only */
548 memcpy(mmu_psize_defs
, mmu_psize_defaults_old
,
549 sizeof(mmu_psize_defaults_old
));
552 * Try to find the available page sizes in the device-tree
554 rc
= of_scan_flat_dt(htab_dt_scan_page_sizes
, NULL
);
555 if (rc
== 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE
)) {
557 * Nothing in the device-tree, but the CPU supports 16M pages,
558 * so let's fallback on a known size list for 16M capable CPUs.
560 memcpy(mmu_psize_defs
, mmu_psize_defaults_gp
,
561 sizeof(mmu_psize_defaults_gp
));
564 #ifdef CONFIG_HUGETLB_PAGE
565 /* Reserve 16G huge page memory sections for huge pages */
566 of_scan_flat_dt(htab_dt_scan_hugepage_blocks
, NULL
);
567 #endif /* CONFIG_HUGETLB_PAGE */
571 * Fill in the hpte_page_sizes[] array.
572 * We go through the mmu_psize_defs[] array looking for all the
573 * supported base/actual page size combinations. Each combination
574 * has a unique pagesize encoding (penc) value in the low bits of
575 * the LP field of the HPTE. For actual page sizes less than 1MB,
576 * some of the upper LP bits are used for RPN bits, meaning that
577 * we need to fill in several entries in hpte_page_sizes[].
579 * In diagrammatic form, with r = RPN bits and z = page size bits:
580 * PTE LP actual page size
587 * The zzzz bits are implementation-specific but are chosen so that
588 * no encoding for a larger page size uses the same value in its
589 * low-order N bits as the encoding for the 2^(12+N) byte page size
592 static void init_hpte_page_sizes(void)
595 long int shift
, penc
;
597 for (bp
= 0; bp
< MMU_PAGE_COUNT
; ++bp
) {
598 if (!mmu_psize_defs
[bp
].shift
)
599 continue; /* not a supported page size */
600 for (ap
= bp
; ap
< MMU_PAGE_COUNT
; ++ap
) {
601 penc
= mmu_psize_defs
[bp
].penc
[ap
];
604 shift
= mmu_psize_defs
[ap
].shift
- LP_SHIFT
;
606 continue; /* should never happen */
608 * For page sizes less than 1MB, this loop
609 * replicates the entry for all possible values
612 while (penc
< (1 << LP_BITS
)) {
613 hpte_page_sizes
[penc
] = (ap
<< 4) | bp
;
620 static void __init
htab_init_page_sizes(void)
622 init_hpte_page_sizes();
624 if (!debug_pagealloc_enabled()) {
626 * Pick a size for the linear mapping. Currently, we only
627 * support 16M, 1M and 4K which is the default
629 if (mmu_psize_defs
[MMU_PAGE_16M
].shift
)
630 mmu_linear_psize
= MMU_PAGE_16M
;
631 else if (mmu_psize_defs
[MMU_PAGE_1M
].shift
)
632 mmu_linear_psize
= MMU_PAGE_1M
;
635 #ifdef CONFIG_PPC_64K_PAGES
637 * Pick a size for the ordinary pages. Default is 4K, we support
638 * 64K for user mappings and vmalloc if supported by the processor.
639 * We only use 64k for ioremap if the processor
640 * (and firmware) support cache-inhibited large pages.
641 * If not, we use 4k and set mmu_ci_restrictions so that
642 * hash_page knows to switch processes that use cache-inhibited
643 * mappings to 4k pages.
645 if (mmu_psize_defs
[MMU_PAGE_64K
].shift
) {
646 mmu_virtual_psize
= MMU_PAGE_64K
;
647 mmu_vmalloc_psize
= MMU_PAGE_64K
;
648 if (mmu_linear_psize
== MMU_PAGE_4K
)
649 mmu_linear_psize
= MMU_PAGE_64K
;
650 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE
)) {
652 * When running on pSeries using 64k pages for ioremap
653 * would stop us accessing the HEA ethernet. So if we
654 * have the chance of ever seeing one, stay at 4k.
656 if (!might_have_hea())
657 mmu_io_psize
= MMU_PAGE_64K
;
659 mmu_ci_restrictions
= 1;
661 #endif /* CONFIG_PPC_64K_PAGES */
663 #ifdef CONFIG_SPARSEMEM_VMEMMAP
664 /* We try to use 16M pages for vmemmap if that is supported
665 * and we have at least 1G of RAM at boot
667 if (mmu_psize_defs
[MMU_PAGE_16M
].shift
&&
668 memblock_phys_mem_size() >= 0x40000000)
669 mmu_vmemmap_psize
= MMU_PAGE_16M
;
670 else if (mmu_psize_defs
[MMU_PAGE_64K
].shift
)
671 mmu_vmemmap_psize
= MMU_PAGE_64K
;
673 mmu_vmemmap_psize
= MMU_PAGE_4K
;
674 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
676 printk(KERN_DEBUG
"Page orders: linear mapping = %d, "
677 "virtual = %d, io = %d"
678 #ifdef CONFIG_SPARSEMEM_VMEMMAP
682 mmu_psize_defs
[mmu_linear_psize
].shift
,
683 mmu_psize_defs
[mmu_virtual_psize
].shift
,
684 mmu_psize_defs
[mmu_io_psize
].shift
685 #ifdef CONFIG_SPARSEMEM_VMEMMAP
686 ,mmu_psize_defs
[mmu_vmemmap_psize
].shift
691 static int __init
htab_dt_scan_pftsize(unsigned long node
,
692 const char *uname
, int depth
,
695 const char *type
= of_get_flat_dt_prop(node
, "device_type", NULL
);
698 /* We are scanning "cpu" nodes only */
699 if (type
== NULL
|| strcmp(type
, "cpu") != 0)
702 prop
= of_get_flat_dt_prop(node
, "ibm,pft-size", NULL
);
704 /* pft_size[0] is the NUMA CEC cookie */
705 ppc64_pft_size
= be32_to_cpu(prop
[1]);
711 unsigned htab_shift_for_mem_size(unsigned long mem_size
)
713 unsigned memshift
= __ilog2(mem_size
);
714 unsigned pshift
= mmu_psize_defs
[mmu_virtual_psize
].shift
;
717 /* round mem_size up to next power of 2 */
718 if ((1UL << memshift
) < mem_size
)
721 /* aim for 2 pages / pteg */
722 pteg_shift
= memshift
- (pshift
+ 1);
725 * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab
726 * size permitted by the architecture.
728 return max(pteg_shift
+ 7, 18U);
731 static unsigned long __init
htab_get_table_size(void)
733 /* If hash size isn't already provided by the platform, we try to
734 * retrieve it from the device-tree. If it's not there neither, we
735 * calculate it now based on the total RAM size
737 if (ppc64_pft_size
== 0)
738 of_scan_flat_dt(htab_dt_scan_pftsize
, NULL
);
740 return 1UL << ppc64_pft_size
;
742 return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size());
745 #ifdef CONFIG_MEMORY_HOTPLUG
746 int create_section_mapping(unsigned long start
, unsigned long end
)
748 int rc
= htab_bolt_mapping(start
, end
, __pa(start
),
749 pgprot_val(PAGE_KERNEL
), mmu_linear_psize
,
753 int rc2
= htab_remove_mapping(start
, end
, mmu_linear_psize
,
755 BUG_ON(rc2
&& (rc2
!= -ENOENT
));
760 int remove_section_mapping(unsigned long start
, unsigned long end
)
762 int rc
= htab_remove_mapping(start
, end
, mmu_linear_psize
,
767 #endif /* CONFIG_MEMORY_HOTPLUG */
769 static void __init
hash_init_partition_table(phys_addr_t hash_table
,
770 unsigned long htab_size
)
772 unsigned long ps_field
;
773 unsigned long patb_size
= 1UL << PATB_SIZE_SHIFT
;
776 * slb llp encoding for the page size used in VPM real mode.
777 * We can ignore that for lpid 0
780 htab_size
= __ilog2(htab_size
) - 18;
782 BUILD_BUG_ON_MSG((PATB_SIZE_SHIFT
> 24), "Partition table size too large.");
783 partition_tb
= __va(memblock_alloc_base(patb_size
, patb_size
,
784 MEMBLOCK_ALLOC_ANYWHERE
));
786 /* Initialize the Partition Table with no entries */
787 memset((void *)partition_tb
, 0, patb_size
);
788 partition_tb
->patb0
= cpu_to_be64(ps_field
| hash_table
| htab_size
);
790 * FIXME!! This should be done via update_partition table
791 * For now UPRT is 0 for us.
793 partition_tb
->patb1
= 0;
794 pr_info("Partition table %p\n", partition_tb
);
796 * update partition table control register,
799 mtspr(SPRN_PTCR
, __pa(partition_tb
) | (PATB_SIZE_SHIFT
- 12));
803 static void __init
htab_initialize(void)
806 unsigned long pteg_count
;
808 unsigned long base
= 0, size
= 0;
809 struct memblock_region
*reg
;
811 DBG(" -> htab_initialize()\n");
813 if (mmu_has_feature(MMU_FTR_1T_SEGMENT
)) {
814 mmu_kernel_ssize
= MMU_SEGSIZE_1T
;
815 mmu_highuser_ssize
= MMU_SEGSIZE_1T
;
816 printk(KERN_INFO
"Using 1TB segments\n");
820 * Calculate the required size of the htab. We want the number of
821 * PTEGs to equal one half the number of real pages.
823 htab_size_bytes
= htab_get_table_size();
824 pteg_count
= htab_size_bytes
>> 7;
826 htab_hash_mask
= pteg_count
- 1;
828 if (firmware_has_feature(FW_FEATURE_LPAR
) ||
829 firmware_has_feature(FW_FEATURE_PS3_LV1
)) {
830 /* Using a hypervisor which owns the htab */
833 #ifdef CONFIG_FA_DUMP
835 * If firmware assisted dump is active firmware preserves
836 * the contents of htab along with entire partition memory.
837 * Clear the htab if firmware assisted dump is active so
838 * that we dont end up using old mappings.
840 if (is_fadump_active() && mmu_hash_ops
.hpte_clear_all
)
841 mmu_hash_ops
.hpte_clear_all();
844 unsigned long limit
= MEMBLOCK_ALLOC_ANYWHERE
;
846 #ifdef CONFIG_PPC_CELL
848 * Cell may require the hash table down low when using the
849 * Axon IOMMU in order to fit the dynamic region over it, see
850 * comments in cell/iommu.c
852 if (fdt_subnode_offset(initial_boot_params
, 0, "axon") > 0) {
854 pr_info("Hash table forced below 2G for Axon IOMMU\n");
856 #endif /* CONFIG_PPC_CELL */
858 table
= memblock_alloc_base(htab_size_bytes
, htab_size_bytes
,
861 DBG("Hash table allocated at %lx, size: %lx\n", table
,
864 htab_address
= __va(table
);
866 /* htab absolute addr + encoded htabsize */
867 _SDR1
= table
+ __ilog2(htab_size_bytes
) - 18;
869 /* Initialize the HPT with no entries */
870 memset((void *)table
, 0, htab_size_bytes
);
872 if (!cpu_has_feature(CPU_FTR_ARCH_300
))
874 mtspr(SPRN_SDR1
, _SDR1
);
876 hash_init_partition_table(table
, htab_size_bytes
);
879 prot
= pgprot_val(PAGE_KERNEL
);
881 #ifdef CONFIG_DEBUG_PAGEALLOC
882 if (debug_pagealloc_enabled()) {
883 linear_map_hash_count
= memblock_end_of_DRAM() >> PAGE_SHIFT
;
884 linear_map_hash_slots
= __va(memblock_alloc_base(
885 linear_map_hash_count
, 1, ppc64_rma_size
));
886 memset(linear_map_hash_slots
, 0, linear_map_hash_count
);
888 #endif /* CONFIG_DEBUG_PAGEALLOC */
890 /* On U3 based machines, we need to reserve the DART area and
891 * _NOT_ map it to avoid cache paradoxes as it's remapped non
895 /* create bolted the linear mapping in the hash table */
896 for_each_memblock(memory
, reg
) {
897 base
= (unsigned long)__va(reg
->base
);
900 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
903 BUG_ON(htab_bolt_mapping(base
, base
+ size
, __pa(base
),
904 prot
, mmu_linear_psize
, mmu_kernel_ssize
));
906 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE
);
909 * If we have a memory_limit and we've allocated TCEs then we need to
910 * explicitly map the TCE area at the top of RAM. We also cope with the
911 * case that the TCEs start below memory_limit.
912 * tce_alloc_start/end are 16MB aligned so the mapping should work
913 * for either 4K or 16MB pages.
915 if (tce_alloc_start
) {
916 tce_alloc_start
= (unsigned long)__va(tce_alloc_start
);
917 tce_alloc_end
= (unsigned long)__va(tce_alloc_end
);
919 if (base
+ size
>= tce_alloc_start
)
920 tce_alloc_start
= base
+ size
+ 1;
922 BUG_ON(htab_bolt_mapping(tce_alloc_start
, tce_alloc_end
,
923 __pa(tce_alloc_start
), prot
,
924 mmu_linear_psize
, mmu_kernel_ssize
));
928 DBG(" <- htab_initialize()\n");
933 void __init
hash__early_init_devtree(void)
935 /* Initialize segment sizes */
936 of_scan_flat_dt(htab_dt_scan_seg_sizes
, NULL
);
938 /* Initialize page sizes */
939 htab_scan_page_sizes();
942 void __init
hash__early_init_mmu(void)
944 htab_init_page_sizes();
947 * initialize page table size
949 __pte_frag_nr
= H_PTE_FRAG_NR
;
950 __pte_frag_size_shift
= H_PTE_FRAG_SIZE_SHIFT
;
952 __pte_index_size
= H_PTE_INDEX_SIZE
;
953 __pmd_index_size
= H_PMD_INDEX_SIZE
;
954 __pud_index_size
= H_PUD_INDEX_SIZE
;
955 __pgd_index_size
= H_PGD_INDEX_SIZE
;
956 __pmd_cache_index
= H_PMD_CACHE_INDEX
;
957 __pte_table_size
= H_PTE_TABLE_SIZE
;
958 __pmd_table_size
= H_PMD_TABLE_SIZE
;
959 __pud_table_size
= H_PUD_TABLE_SIZE
;
960 __pgd_table_size
= H_PGD_TABLE_SIZE
;
962 * 4k use hugepd format, so for hash set then to
969 __kernel_virt_start
= H_KERN_VIRT_START
;
970 __kernel_virt_size
= H_KERN_VIRT_SIZE
;
971 __vmalloc_start
= H_VMALLOC_START
;
972 __vmalloc_end
= H_VMALLOC_END
;
973 vmemmap
= (struct page
*)H_VMEMMAP_BASE
;
974 ioremap_bot
= IOREMAP_BASE
;
977 pci_io_base
= ISA_IO_BASE
;
980 /* Select appropriate backend */
981 if (firmware_has_feature(FW_FEATURE_PS3_LV1
))
983 else if (firmware_has_feature(FW_FEATURE_LPAR
))
985 else if (IS_ENABLED(CONFIG_PPC_NATIVE
))
988 if (!mmu_hash_ops
.hpte_insert
)
989 panic("hash__early_init_mmu: No MMU hash ops defined!\n");
991 /* Initialize the MMU Hash table and create the linear mapping
992 * of memory. Has to be done before SLB initialization as this is
993 * currently where the page size encoding is obtained.
997 pr_info("Initializing hash mmu with SLB\n");
998 /* Initialize SLB management */
1003 void hash__early_init_mmu_secondary(void)
1005 /* Initialize hash table for that CPU */
1006 if (!firmware_has_feature(FW_FEATURE_LPAR
)) {
1007 if (!cpu_has_feature(CPU_FTR_ARCH_300
))
1008 mtspr(SPRN_SDR1
, _SDR1
);
1011 __pa(partition_tb
) | (PATB_SIZE_SHIFT
- 12));
1013 /* Initialize SLB */
1016 #endif /* CONFIG_SMP */
1019 * Called by asm hashtable.S for doing lazy icache flush
1021 unsigned int hash_page_do_lazy_icache(unsigned int pp
, pte_t pte
, int trap
)
1025 if (!pfn_valid(pte_pfn(pte
)))
1028 page
= pte_page(pte
);
1031 if (!test_bit(PG_arch_1
, &page
->flags
) && !PageReserved(page
)) {
1032 if (trap
== 0x400) {
1033 flush_dcache_icache_page(page
);
1034 set_bit(PG_arch_1
, &page
->flags
);
1041 #ifdef CONFIG_PPC_MM_SLICES
1042 static unsigned int get_paca_psize(unsigned long addr
)
1045 unsigned char *hpsizes
;
1046 unsigned long index
, mask_index
;
1048 if (addr
< SLICE_LOW_TOP
) {
1049 lpsizes
= get_paca()->mm_ctx_low_slices_psize
;
1050 index
= GET_LOW_SLICE_INDEX(addr
);
1051 return (lpsizes
>> (index
* 4)) & 0xF;
1053 hpsizes
= get_paca()->mm_ctx_high_slices_psize
;
1054 index
= GET_HIGH_SLICE_INDEX(addr
);
1055 mask_index
= index
& 0x1;
1056 return (hpsizes
[index
>> 1] >> (mask_index
* 4)) & 0xF;
1060 unsigned int get_paca_psize(unsigned long addr
)
1062 return get_paca()->mm_ctx_user_psize
;
1067 * Demote a segment to using 4k pages.
1068 * For now this makes the whole process use 4k pages.
1070 #ifdef CONFIG_PPC_64K_PAGES
1071 void demote_segment_4k(struct mm_struct
*mm
, unsigned long addr
)
1073 if (get_slice_psize(mm
, addr
) == MMU_PAGE_4K
)
1075 slice_set_range_psize(mm
, addr
, 1, MMU_PAGE_4K
);
1076 copro_flush_all_slbs(mm
);
1077 if ((get_paca_psize(addr
) != MMU_PAGE_4K
) && (current
->mm
== mm
)) {
1079 copy_mm_to_paca(&mm
->context
);
1080 slb_flush_and_rebolt();
1083 #endif /* CONFIG_PPC_64K_PAGES */
1085 #ifdef CONFIG_PPC_SUBPAGE_PROT
1087 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
1088 * Userspace sets the subpage permissions using the subpage_prot system call.
1090 * Result is 0: full permissions, _PAGE_RW: read-only,
1091 * _PAGE_RWX: no access.
1093 static int subpage_protection(struct mm_struct
*mm
, unsigned long ea
)
1095 struct subpage_prot_table
*spt
= &mm
->context
.spt
;
1099 if (ea
>= spt
->maxaddr
)
1101 if (ea
< 0x100000000UL
) {
1102 /* addresses below 4GB use spt->low_prot */
1103 sbpm
= spt
->low_prot
;
1105 sbpm
= spt
->protptrs
[ea
>> SBP_L3_SHIFT
];
1109 sbpp
= sbpm
[(ea
>> SBP_L2_SHIFT
) & (SBP_L2_COUNT
- 1)];
1112 spp
= sbpp
[(ea
>> PAGE_SHIFT
) & (SBP_L1_COUNT
- 1)];
1114 /* extract 2-bit bitfield for this 4k subpage */
1115 spp
>>= 30 - 2 * ((ea
>> 12) & 0xf);
1118 * 0 -> full premission
1121 * We return the flag that need to be cleared.
1123 spp
= ((spp
& 2) ? _PAGE_RWX
: 0) | ((spp
& 1) ? _PAGE_WRITE
: 0);
1127 #else /* CONFIG_PPC_SUBPAGE_PROT */
1128 static inline int subpage_protection(struct mm_struct
*mm
, unsigned long ea
)
1134 void hash_failure_debug(unsigned long ea
, unsigned long access
,
1135 unsigned long vsid
, unsigned long trap
,
1136 int ssize
, int psize
, int lpsize
, unsigned long pte
)
1138 if (!printk_ratelimit())
1140 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
1141 ea
, access
, current
->comm
);
1142 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
1143 trap
, vsid
, ssize
, psize
, lpsize
, pte
);
1146 static void check_paca_psize(unsigned long ea
, struct mm_struct
*mm
,
1147 int psize
, bool user_region
)
1150 if (psize
!= get_paca_psize(ea
)) {
1151 copy_mm_to_paca(&mm
->context
);
1152 slb_flush_and_rebolt();
1154 } else if (get_paca()->vmalloc_sllp
!=
1155 mmu_psize_defs
[mmu_vmalloc_psize
].sllp
) {
1156 get_paca()->vmalloc_sllp
=
1157 mmu_psize_defs
[mmu_vmalloc_psize
].sllp
;
1158 slb_vmalloc_update();
1164 * 1 - normal page fault
1165 * -1 - critical hash insertion error
1166 * -2 - access not permitted by subpage protection mechanism
1168 int hash_page_mm(struct mm_struct
*mm
, unsigned long ea
,
1169 unsigned long access
, unsigned long trap
,
1170 unsigned long flags
)
1173 enum ctx_state prev_state
= exception_enter();
1178 const struct cpumask
*tmp
;
1179 int rc
, user_region
= 0;
1182 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1184 trace_hash_fault(ea
, access
, trap
);
1186 /* Get region & vsid */
1187 switch (REGION_ID(ea
)) {
1188 case USER_REGION_ID
:
1191 DBG_LOW(" user region with no mm !\n");
1195 psize
= get_slice_psize(mm
, ea
);
1196 ssize
= user_segment_size(ea
);
1197 vsid
= get_vsid(mm
->context
.id
, ea
, ssize
);
1199 case VMALLOC_REGION_ID
:
1200 vsid
= get_kernel_vsid(ea
, mmu_kernel_ssize
);
1201 if (ea
< VMALLOC_END
)
1202 psize
= mmu_vmalloc_psize
;
1204 psize
= mmu_io_psize
;
1205 ssize
= mmu_kernel_ssize
;
1208 /* Not a valid range
1209 * Send the problem up to do_page_fault
1214 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm
, mm
->pgd
, vsid
);
1218 DBG_LOW("Bad address!\n");
1224 if (pgdir
== NULL
) {
1229 /* Check CPU locality */
1230 tmp
= cpumask_of(smp_processor_id());
1231 if (user_region
&& cpumask_equal(mm_cpumask(mm
), tmp
))
1232 flags
|= HPTE_LOCAL_UPDATE
;
1234 #ifndef CONFIG_PPC_64K_PAGES
1235 /* If we use 4K pages and our psize is not 4K, then we might
1236 * be hitting a special driver mapping, and need to align the
1237 * address before we fetch the PTE.
1239 * It could also be a hugepage mapping, in which case this is
1240 * not necessary, but it's not harmful, either.
1242 if (psize
!= MMU_PAGE_4K
)
1243 ea
&= ~((1ul << mmu_psize_defs
[psize
].shift
) - 1);
1244 #endif /* CONFIG_PPC_64K_PAGES */
1246 /* Get PTE and page size from page tables */
1247 ptep
= __find_linux_pte_or_hugepte(pgdir
, ea
, &is_thp
, &hugeshift
);
1248 if (ptep
== NULL
|| !pte_present(*ptep
)) {
1249 DBG_LOW(" no PTE !\n");
1254 /* Add _PAGE_PRESENT to the required access perm */
1255 access
|= _PAGE_PRESENT
;
1257 /* Pre-check access permissions (will be re-checked atomically
1258 * in __hash_page_XX but this pre-check is a fast path
1260 if (!check_pte_access(access
, pte_val(*ptep
))) {
1261 DBG_LOW(" no access !\n");
1268 rc
= __hash_page_thp(ea
, access
, vsid
, (pmd_t
*)ptep
,
1269 trap
, flags
, ssize
, psize
);
1270 #ifdef CONFIG_HUGETLB_PAGE
1272 rc
= __hash_page_huge(ea
, access
, vsid
, ptep
, trap
,
1273 flags
, ssize
, hugeshift
, psize
);
1277 * if we have hugeshift, and is not transhuge with
1278 * hugetlb disabled, something is really wrong.
1284 if (current
->mm
== mm
)
1285 check_paca_psize(ea
, mm
, psize
, user_region
);
1290 #ifndef CONFIG_PPC_64K_PAGES
1291 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep
));
1293 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep
),
1294 pte_val(*(ptep
+ PTRS_PER_PTE
)));
1296 /* Do actual hashing */
1297 #ifdef CONFIG_PPC_64K_PAGES
1298 /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */
1299 if ((pte_val(*ptep
) & H_PAGE_4K_PFN
) && psize
== MMU_PAGE_64K
) {
1300 demote_segment_4k(mm
, ea
);
1301 psize
= MMU_PAGE_4K
;
1304 /* If this PTE is non-cacheable and we have restrictions on
1305 * using non cacheable large pages, then we switch to 4k
1307 if (mmu_ci_restrictions
&& psize
== MMU_PAGE_64K
&& pte_ci(*ptep
)) {
1309 demote_segment_4k(mm
, ea
);
1310 psize
= MMU_PAGE_4K
;
1311 } else if (ea
< VMALLOC_END
) {
1313 * some driver did a non-cacheable mapping
1314 * in vmalloc space, so switch vmalloc
1317 printk(KERN_ALERT
"Reducing vmalloc segment "
1318 "to 4kB pages because of "
1319 "non-cacheable mapping\n");
1320 psize
= mmu_vmalloc_psize
= MMU_PAGE_4K
;
1321 copro_flush_all_slbs(mm
);
1325 #endif /* CONFIG_PPC_64K_PAGES */
1327 if (current
->mm
== mm
)
1328 check_paca_psize(ea
, mm
, psize
, user_region
);
1330 #ifdef CONFIG_PPC_64K_PAGES
1331 if (psize
== MMU_PAGE_64K
)
1332 rc
= __hash_page_64K(ea
, access
, vsid
, ptep
, trap
,
1335 #endif /* CONFIG_PPC_64K_PAGES */
1337 int spp
= subpage_protection(mm
, ea
);
1341 rc
= __hash_page_4K(ea
, access
, vsid
, ptep
, trap
,
1345 /* Dump some info in case of hash insertion failure, they should
1346 * never happen so it is really useful to know if/when they do
1349 hash_failure_debug(ea
, access
, vsid
, trap
, ssize
, psize
,
1350 psize
, pte_val(*ptep
));
1351 #ifndef CONFIG_PPC_64K_PAGES
1352 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep
));
1354 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep
),
1355 pte_val(*(ptep
+ PTRS_PER_PTE
)));
1357 DBG_LOW(" -> rc=%d\n", rc
);
1360 exception_exit(prev_state
);
1363 EXPORT_SYMBOL_GPL(hash_page_mm
);
1365 int hash_page(unsigned long ea
, unsigned long access
, unsigned long trap
,
1366 unsigned long dsisr
)
1368 unsigned long flags
= 0;
1369 struct mm_struct
*mm
= current
->mm
;
1371 if (REGION_ID(ea
) == VMALLOC_REGION_ID
)
1374 if (dsisr
& DSISR_NOHPTE
)
1375 flags
|= HPTE_NOHPTE_UPDATE
;
1377 return hash_page_mm(mm
, ea
, access
, trap
, flags
);
1379 EXPORT_SYMBOL_GPL(hash_page
);
1381 int __hash_page(unsigned long ea
, unsigned long msr
, unsigned long trap
,
1382 unsigned long dsisr
)
1384 unsigned long access
= _PAGE_PRESENT
| _PAGE_READ
;
1385 unsigned long flags
= 0;
1386 struct mm_struct
*mm
= current
->mm
;
1388 if (REGION_ID(ea
) == VMALLOC_REGION_ID
)
1391 if (dsisr
& DSISR_NOHPTE
)
1392 flags
|= HPTE_NOHPTE_UPDATE
;
1394 if (dsisr
& DSISR_ISSTORE
)
1395 access
|= _PAGE_WRITE
;
1397 * We set _PAGE_PRIVILEGED only when
1398 * kernel mode access kernel space.
1400 * _PAGE_PRIVILEGED is NOT set
1401 * 1) when kernel mode access user space
1402 * 2) user space access kernel space.
1404 access
|= _PAGE_PRIVILEGED
;
1405 if ((msr
& MSR_PR
) || (REGION_ID(ea
) == USER_REGION_ID
))
1406 access
&= ~_PAGE_PRIVILEGED
;
1409 access
|= _PAGE_EXEC
;
1411 return hash_page_mm(mm
, ea
, access
, trap
, flags
);
1414 #ifdef CONFIG_PPC_MM_SLICES
1415 static bool should_hash_preload(struct mm_struct
*mm
, unsigned long ea
)
1417 int psize
= get_slice_psize(mm
, ea
);
1419 /* We only prefault standard pages for now */
1420 if (unlikely(psize
!= mm
->context
.user_psize
))
1424 * Don't prefault if subpage protection is enabled for the EA.
1426 if (unlikely((psize
== MMU_PAGE_4K
) && subpage_protection(mm
, ea
)))
1432 static bool should_hash_preload(struct mm_struct
*mm
, unsigned long ea
)
1438 void hash_preload(struct mm_struct
*mm
, unsigned long ea
,
1439 unsigned long access
, unsigned long trap
)
1445 unsigned long flags
;
1446 int rc
, ssize
, update_flags
= 0;
1448 BUG_ON(REGION_ID(ea
) != USER_REGION_ID
);
1450 if (!should_hash_preload(mm
, ea
))
1453 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1454 " trap=%lx\n", mm
, mm
->pgd
, ea
, access
, trap
);
1456 /* Get Linux PTE if available */
1462 ssize
= user_segment_size(ea
);
1463 vsid
= get_vsid(mm
->context
.id
, ea
, ssize
);
1467 * Hash doesn't like irqs. Walking linux page table with irq disabled
1468 * saves us from holding multiple locks.
1470 local_irq_save(flags
);
1473 * THP pages use update_mmu_cache_pmd. We don't do
1474 * hash preload there. Hence can ignore THP here
1476 ptep
= find_linux_pte_or_hugepte(pgdir
, ea
, NULL
, &hugepage_shift
);
1480 WARN_ON(hugepage_shift
);
1481 #ifdef CONFIG_PPC_64K_PAGES
1482 /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on
1483 * a 64K kernel), then we don't preload, hash_page() will take
1484 * care of it once we actually try to access the page.
1485 * That way we don't have to duplicate all of the logic for segment
1486 * page size demotion here
1488 if ((pte_val(*ptep
) & H_PAGE_4K_PFN
) || pte_ci(*ptep
))
1490 #endif /* CONFIG_PPC_64K_PAGES */
1492 /* Is that local to this CPU ? */
1493 if (cpumask_equal(mm_cpumask(mm
), cpumask_of(smp_processor_id())))
1494 update_flags
|= HPTE_LOCAL_UPDATE
;
1497 #ifdef CONFIG_PPC_64K_PAGES
1498 if (mm
->context
.user_psize
== MMU_PAGE_64K
)
1499 rc
= __hash_page_64K(ea
, access
, vsid
, ptep
, trap
,
1500 update_flags
, ssize
);
1502 #endif /* CONFIG_PPC_64K_PAGES */
1503 rc
= __hash_page_4K(ea
, access
, vsid
, ptep
, trap
, update_flags
,
1504 ssize
, subpage_protection(mm
, ea
));
1506 /* Dump some info in case of hash insertion failure, they should
1507 * never happen so it is really useful to know if/when they do
1510 hash_failure_debug(ea
, access
, vsid
, trap
, ssize
,
1511 mm
->context
.user_psize
,
1512 mm
->context
.user_psize
,
1515 local_irq_restore(flags
);
1518 /* WARNING: This is called from hash_low_64.S, if you change this prototype,
1519 * do not forget to update the assembly call site !
1521 void flush_hash_page(unsigned long vpn
, real_pte_t pte
, int psize
, int ssize
,
1522 unsigned long flags
)
1524 unsigned long hash
, index
, shift
, hidx
, slot
;
1525 int local
= flags
& HPTE_LOCAL_UPDATE
;
1527 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn
);
1528 pte_iterate_hashed_subpages(pte
, psize
, vpn
, index
, shift
) {
1529 hash
= hpt_hash(vpn
, shift
, ssize
);
1530 hidx
= __rpte_to_hidx(pte
, index
);
1531 if (hidx
& _PTEIDX_SECONDARY
)
1533 slot
= (hash
& htab_hash_mask
) * HPTES_PER_GROUP
;
1534 slot
+= hidx
& _PTEIDX_GROUP_IX
;
1535 DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index
, slot
, hidx
);
1537 * We use same base page size and actual psize, because we don't
1538 * use these functions for hugepage
1540 mmu_hash_ops
.hpte_invalidate(slot
, vpn
, psize
, psize
,
1542 } pte_iterate_hashed_end();
1544 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1545 /* Transactions are not aborted by tlbiel, only tlbie.
1546 * Without, syncing a page back to a block device w/ PIO could pick up
1547 * transactional data (bad!) so we force an abort here. Before the
1548 * sync the page will be made read-only, which will flush_hash_page.
1549 * BIG ISSUE here: if the kernel uses a page from userspace without
1550 * unmapping it first, it may see the speculated version.
1552 if (local
&& cpu_has_feature(CPU_FTR_TM
) &&
1553 current
->thread
.regs
&&
1554 MSR_TM_ACTIVE(current
->thread
.regs
->msr
)) {
1556 tm_abort(TM_CAUSE_TLBI
);
1561 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1562 void flush_hash_hugepage(unsigned long vsid
, unsigned long addr
,
1563 pmd_t
*pmdp
, unsigned int psize
, int ssize
,
1564 unsigned long flags
)
1566 int i
, max_hpte_count
, valid
;
1567 unsigned long s_addr
;
1568 unsigned char *hpte_slot_array
;
1569 unsigned long hidx
, shift
, vpn
, hash
, slot
;
1570 int local
= flags
& HPTE_LOCAL_UPDATE
;
1572 s_addr
= addr
& HPAGE_PMD_MASK
;
1573 hpte_slot_array
= get_hpte_slot_array(pmdp
);
1575 * IF we try to do a HUGE PTE update after a withdraw is done.
1576 * we will find the below NULL. This happens when we do
1577 * split_huge_page_pmd
1579 if (!hpte_slot_array
)
1582 if (mmu_hash_ops
.hugepage_invalidate
) {
1583 mmu_hash_ops
.hugepage_invalidate(vsid
, s_addr
, hpte_slot_array
,
1584 psize
, ssize
, local
);
1588 * No bluk hpte removal support, invalidate each entry
1590 shift
= mmu_psize_defs
[psize
].shift
;
1591 max_hpte_count
= HPAGE_PMD_SIZE
>> shift
;
1592 for (i
= 0; i
< max_hpte_count
; i
++) {
1594 * 8 bits per each hpte entries
1595 * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
1597 valid
= hpte_valid(hpte_slot_array
, i
);
1600 hidx
= hpte_hash_index(hpte_slot_array
, i
);
1603 addr
= s_addr
+ (i
* (1ul << shift
));
1604 vpn
= hpt_vpn(addr
, vsid
, ssize
);
1605 hash
= hpt_hash(vpn
, shift
, ssize
);
1606 if (hidx
& _PTEIDX_SECONDARY
)
1609 slot
= (hash
& htab_hash_mask
) * HPTES_PER_GROUP
;
1610 slot
+= hidx
& _PTEIDX_GROUP_IX
;
1611 mmu_hash_ops
.hpte_invalidate(slot
, vpn
, psize
,
1612 MMU_PAGE_16M
, ssize
, local
);
1615 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1616 /* Transactions are not aborted by tlbiel, only tlbie.
1617 * Without, syncing a page back to a block device w/ PIO could pick up
1618 * transactional data (bad!) so we force an abort here. Before the
1619 * sync the page will be made read-only, which will flush_hash_page.
1620 * BIG ISSUE here: if the kernel uses a page from userspace without
1621 * unmapping it first, it may see the speculated version.
1623 if (local
&& cpu_has_feature(CPU_FTR_TM
) &&
1624 current
->thread
.regs
&&
1625 MSR_TM_ACTIVE(current
->thread
.regs
->msr
)) {
1627 tm_abort(TM_CAUSE_TLBI
);
1632 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1634 void flush_hash_range(unsigned long number
, int local
)
1636 if (mmu_hash_ops
.flush_hash_range
)
1637 mmu_hash_ops
.flush_hash_range(number
, local
);
1640 struct ppc64_tlb_batch
*batch
=
1641 this_cpu_ptr(&ppc64_tlb_batch
);
1643 for (i
= 0; i
< number
; i
++)
1644 flush_hash_page(batch
->vpn
[i
], batch
->pte
[i
],
1645 batch
->psize
, batch
->ssize
, local
);
1650 * low_hash_fault is called when we the low level hash code failed
1651 * to instert a PTE due to an hypervisor error
1653 void low_hash_fault(struct pt_regs
*regs
, unsigned long address
, int rc
)
1655 enum ctx_state prev_state
= exception_enter();
1657 if (user_mode(regs
)) {
1658 #ifdef CONFIG_PPC_SUBPAGE_PROT
1660 _exception(SIGSEGV
, regs
, SEGV_ACCERR
, address
);
1663 _exception(SIGBUS
, regs
, BUS_ADRERR
, address
);
1665 bad_page_fault(regs
, address
, SIGBUS
);
1667 exception_exit(prev_state
);
1670 long hpte_insert_repeating(unsigned long hash
, unsigned long vpn
,
1671 unsigned long pa
, unsigned long rflags
,
1672 unsigned long vflags
, int psize
, int ssize
)
1674 unsigned long hpte_group
;
1678 hpte_group
= ((hash
& htab_hash_mask
) *
1679 HPTES_PER_GROUP
) & ~0x7UL
;
1681 /* Insert into the hash table, primary slot */
1682 slot
= mmu_hash_ops
.hpte_insert(hpte_group
, vpn
, pa
, rflags
, vflags
,
1683 psize
, psize
, ssize
);
1685 /* Primary is full, try the secondary */
1686 if (unlikely(slot
== -1)) {
1687 hpte_group
= ((~hash
& htab_hash_mask
) *
1688 HPTES_PER_GROUP
) & ~0x7UL
;
1689 slot
= mmu_hash_ops
.hpte_insert(hpte_group
, vpn
, pa
, rflags
,
1690 vflags
| HPTE_V_SECONDARY
,
1691 psize
, psize
, ssize
);
1694 hpte_group
= ((hash
& htab_hash_mask
) *
1695 HPTES_PER_GROUP
)&~0x7UL
;
1697 mmu_hash_ops
.hpte_remove(hpte_group
);
1705 #ifdef CONFIG_DEBUG_PAGEALLOC
1706 static void kernel_map_linear_page(unsigned long vaddr
, unsigned long lmi
)
1709 unsigned long vsid
= get_kernel_vsid(vaddr
, mmu_kernel_ssize
);
1710 unsigned long vpn
= hpt_vpn(vaddr
, vsid
, mmu_kernel_ssize
);
1711 unsigned long mode
= htab_convert_pte_flags(pgprot_val(PAGE_KERNEL
));
1714 hash
= hpt_hash(vpn
, PAGE_SHIFT
, mmu_kernel_ssize
);
1716 /* Don't create HPTE entries for bad address */
1720 ret
= hpte_insert_repeating(hash
, vpn
, __pa(vaddr
), mode
,
1722 mmu_linear_psize
, mmu_kernel_ssize
);
1725 spin_lock(&linear_map_hash_lock
);
1726 BUG_ON(linear_map_hash_slots
[lmi
] & 0x80);
1727 linear_map_hash_slots
[lmi
] = ret
| 0x80;
1728 spin_unlock(&linear_map_hash_lock
);
1731 static void kernel_unmap_linear_page(unsigned long vaddr
, unsigned long lmi
)
1733 unsigned long hash
, hidx
, slot
;
1734 unsigned long vsid
= get_kernel_vsid(vaddr
, mmu_kernel_ssize
);
1735 unsigned long vpn
= hpt_vpn(vaddr
, vsid
, mmu_kernel_ssize
);
1737 hash
= hpt_hash(vpn
, PAGE_SHIFT
, mmu_kernel_ssize
);
1738 spin_lock(&linear_map_hash_lock
);
1739 BUG_ON(!(linear_map_hash_slots
[lmi
] & 0x80));
1740 hidx
= linear_map_hash_slots
[lmi
] & 0x7f;
1741 linear_map_hash_slots
[lmi
] = 0;
1742 spin_unlock(&linear_map_hash_lock
);
1743 if (hidx
& _PTEIDX_SECONDARY
)
1745 slot
= (hash
& htab_hash_mask
) * HPTES_PER_GROUP
;
1746 slot
+= hidx
& _PTEIDX_GROUP_IX
;
1747 mmu_hash_ops
.hpte_invalidate(slot
, vpn
, mmu_linear_psize
,
1749 mmu_kernel_ssize
, 0);
1752 void __kernel_map_pages(struct page
*page
, int numpages
, int enable
)
1754 unsigned long flags
, vaddr
, lmi
;
1757 local_irq_save(flags
);
1758 for (i
= 0; i
< numpages
; i
++, page
++) {
1759 vaddr
= (unsigned long)page_address(page
);
1760 lmi
= __pa(vaddr
) >> PAGE_SHIFT
;
1761 if (lmi
>= linear_map_hash_count
)
1764 kernel_map_linear_page(vaddr
, lmi
);
1766 kernel_unmap_linear_page(vaddr
, lmi
);
1768 local_irq_restore(flags
);
1770 #endif /* CONFIG_DEBUG_PAGEALLOC */
1772 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base
,
1773 phys_addr_t first_memblock_size
)
1775 /* We don't currently support the first MEMBLOCK not mapping 0
1776 * physical on those processors
1778 BUG_ON(first_memblock_base
!= 0);
1780 /* On LPAR systems, the first entry is our RMA region,
1781 * non-LPAR 64-bit hash MMU systems don't have a limitation
1782 * on real mode access, but using the first entry works well
1783 * enough. We also clamp it to 1G to avoid some funky things
1784 * such as RTAS bugs etc...
1786 ppc64_rma_size
= min_t(u64
, first_memblock_size
, 0x40000000);
1788 /* Finally limit subsequent allocations */
1789 memblock_set_current_limit(ppc64_rma_size
);