arch/sh/kernel/cpu/sh2a/setup-sh7201.c

   1 /*
   2  *  SH7201 setup
   3  *
   4  *  Copyright (C) 2008  Peter Griffin pgriffin@mpc-data.co.uk
   5  *  Copyright (C) 2009  Paul Mundt
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11 #include <linux/platform_device.h>
  12 #include <linux/init.h>
  13 #include <linux/serial.h>
  14 #include <linux/serial_sci.h>
  15 #include <linux/sh_timer.h>
  16 #include <linux/io.h>
  17
  18 enum {
  19         UNUSED = 0,
  20
  21         /* interrupt sources */
  22         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
  23         PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
  24
  25         ADC_ADI,
  26
  27         MTU20_ABCD, MTU20_VEF, MTU21_AB, MTU21_VU, MTU22_AB, MTU22_VU,
  28         MTU23_ABCD, MTU24_ABCD, MTU25_UVW, MTU2_TCI3V, MTU2_TCI4V,
  29
  30         RTC, WDT,
  31
  32         IIC30, IIC31, IIC32,
  33
  34         DMAC0_DMINT0, DMAC1_DMINT1,
  35         DMAC2_DMINT2, DMAC3_DMINT3,
  36
  37         SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
  38
  39         DMAC0_DMINTA, DMAC4_DMINT4, DMAC5_DMINT5, DMAC6_DMINT6,
  40         DMAC7_DMINT7,
  41
  42         RCAN0, RCAN1,
  43
  44         SSI0_SSII, SSI1_SSII,
  45
  46         TMR0, TMR1,
  47
  48         /* interrupt groups */
  49         PINT,
  50 };
  51
  52 static struct intc_vect vectors[] __initdata = {
  53         INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
  54         INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
  55         INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
  56         INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
  57
  58         INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
  59         INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
  60         INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
  61         INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
  62
  63         INTC_IRQ(ADC_ADI, 92),
  64
  65         INTC_IRQ(MTU20_ABCD, 108), INTC_IRQ(MTU20_ABCD, 109),
  66         INTC_IRQ(MTU20_ABCD, 110), INTC_IRQ(MTU20_ABCD, 111),
  67
  68         INTC_IRQ(MTU20_VEF, 112), INTC_IRQ(MTU20_VEF, 113),
  69         INTC_IRQ(MTU20_VEF, 114),
  70
  71         INTC_IRQ(MTU21_AB, 116), INTC_IRQ(MTU21_AB, 117),
  72         INTC_IRQ(MTU21_VU, 120), INTC_IRQ(MTU21_VU, 121),
  73
  74         INTC_IRQ(MTU22_AB, 124), INTC_IRQ(MTU22_AB, 125),
  75         INTC_IRQ(MTU22_VU, 128), INTC_IRQ(MTU22_VU, 129),
  76
  77         INTC_IRQ(MTU23_ABCD, 132), INTC_IRQ(MTU23_ABCD, 133),
  78         INTC_IRQ(MTU23_ABCD, 134), INTC_IRQ(MTU23_ABCD, 135),
  79
  80         INTC_IRQ(MTU2_TCI3V, 136),
  81
  82         INTC_IRQ(MTU24_ABCD, 140), INTC_IRQ(MTU24_ABCD, 141),
  83         INTC_IRQ(MTU24_ABCD, 142), INTC_IRQ(MTU24_ABCD, 143),
  84
  85         INTC_IRQ(MTU2_TCI4V, 144),
  86
  87         INTC_IRQ(MTU25_UVW, 148), INTC_IRQ(MTU25_UVW, 149),
  88         INTC_IRQ(MTU25_UVW, 150),
  89
  90         INTC_IRQ(RTC, 152), INTC_IRQ(RTC, 153),
  91         INTC_IRQ(RTC, 154),
  92
  93         INTC_IRQ(WDT, 156),
  94
  95         INTC_IRQ(IIC30, 157), INTC_IRQ(IIC30, 158),
  96         INTC_IRQ(IIC30, 159), INTC_IRQ(IIC30, 160),
  97         INTC_IRQ(IIC30, 161),
  98
  99         INTC_IRQ(IIC31, 164), INTC_IRQ(IIC31, 165),
 100         INTC_IRQ(IIC31, 166), INTC_IRQ(IIC31, 167),
 101         INTC_IRQ(IIC31, 168),
 102
 103         INTC_IRQ(IIC32, 170), INTC_IRQ(IIC32, 171),
 104         INTC_IRQ(IIC32, 172), INTC_IRQ(IIC32, 173),
 105         INTC_IRQ(IIC32, 174),
 106
 107         INTC_IRQ(DMAC0_DMINT0, 176), INTC_IRQ(DMAC1_DMINT1, 177),
 108         INTC_IRQ(DMAC2_DMINT2, 178), INTC_IRQ(DMAC3_DMINT3, 179),
 109
 110         INTC_IRQ(SCIF0, 180), INTC_IRQ(SCIF0, 181),
 111         INTC_IRQ(SCIF0, 182), INTC_IRQ(SCIF0, 183),
 112         INTC_IRQ(SCIF1, 184), INTC_IRQ(SCIF1, 185),
 113         INTC_IRQ(SCIF1, 186), INTC_IRQ(SCIF1, 187),
 114         INTC_IRQ(SCIF2, 188), INTC_IRQ(SCIF2, 189),
 115         INTC_IRQ(SCIF2, 190), INTC_IRQ(SCIF2, 191),
 116         INTC_IRQ(SCIF3, 192), INTC_IRQ(SCIF3, 193),
 117         INTC_IRQ(SCIF3, 194), INTC_IRQ(SCIF3, 195),
 118         INTC_IRQ(SCIF4, 196), INTC_IRQ(SCIF4, 197),
 119         INTC_IRQ(SCIF4, 198), INTC_IRQ(SCIF4, 199),
 120         INTC_IRQ(SCIF5, 200), INTC_IRQ(SCIF5, 201),
 121         INTC_IRQ(SCIF5, 202), INTC_IRQ(SCIF5, 203),
 122         INTC_IRQ(SCIF6, 204), INTC_IRQ(SCIF6, 205),
 123         INTC_IRQ(SCIF6, 206), INTC_IRQ(SCIF6, 207),
 124         INTC_IRQ(SCIF7, 208), INTC_IRQ(SCIF7, 209),
 125         INTC_IRQ(SCIF7, 210), INTC_IRQ(SCIF7, 211),
 126
 127         INTC_IRQ(DMAC0_DMINTA, 212), INTC_IRQ(DMAC4_DMINT4, 216),
 128         INTC_IRQ(DMAC5_DMINT5, 217), INTC_IRQ(DMAC6_DMINT6, 218),
 129         INTC_IRQ(DMAC7_DMINT7, 219),
 130
 131         INTC_IRQ(RCAN0, 228), INTC_IRQ(RCAN0, 229),
 132         INTC_IRQ(RCAN0, 230),
 133         INTC_IRQ(RCAN0, 231), INTC_IRQ(RCAN0, 232),
 134
 135         INTC_IRQ(RCAN1, 234), INTC_IRQ(RCAN1, 235),
 136         INTC_IRQ(RCAN1, 236),
 137         INTC_IRQ(RCAN1, 237), INTC_IRQ(RCAN1, 238),
 138
 139         INTC_IRQ(SSI0_SSII, 244), INTC_IRQ(SSI1_SSII, 245),
 140
 141         INTC_IRQ(TMR0, 246), INTC_IRQ(TMR0, 247),
 142         INTC_IRQ(TMR0, 248),
 143
 144         INTC_IRQ(TMR1, 252), INTC_IRQ(TMR1, 253),
 145         INTC_IRQ(TMR1, 254),
 146 };
 147
 148 static struct intc_group groups[] __initdata = {
 149         INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
 150                    PINT4, PINT5, PINT6, PINT7),
 151 };
 152
 153 static struct intc_prio_reg prio_registers[] __initdata = {
 154         { 0xfffe9418, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
 155         { 0xfffe941a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
 156         { 0xfffe9420, 0, 16, 4, /* IPR05 */ { PINT, 0, ADC_ADI, 0 } },
 157         { 0xfffe9800, 0, 16, 4, /* IPR06 */ { 0, MTU20_ABCD, MTU20_VEF, MTU21_AB } },
 158         { 0xfffe9802, 0, 16, 4, /* IPR07 */ { MTU21_VU, MTU22_AB, MTU22_VU,  MTU23_ABCD } },
 159         { 0xfffe9804, 0, 16, 4, /* IPR08 */ { MTU2_TCI3V, MTU24_ABCD, MTU2_TCI4V, MTU25_UVW } },
 160
 161         { 0xfffe9806, 0, 16, 4, /* IPR09 */ { RTC, WDT, IIC30, 0 } },
 162         { 0xfffe9808, 0, 16, 4, /* IPR10 */ { IIC31, IIC32, DMAC0_DMINT0, DMAC1_DMINT1 } },
 163         { 0xfffe980a, 0, 16, 4, /* IPR11 */ { DMAC2_DMINT2, DMAC3_DMINT3, SCIF0, SCIF1 } },
 164         { 0xfffe980c, 0, 16, 4, /* IPR12 */ { SCIF2, SCIF3, SCIF4, SCIF5 } },
 165         { 0xfffe980e, 0, 16, 4, /* IPR13 */ { SCIF6, SCIF7, DMAC0_DMINTA, DMAC4_DMINT4  } },
 166         { 0xfffe9810, 0, 16, 4, /* IPR14 */ { DMAC5_DMINT5, DMAC6_DMINT6, DMAC7_DMINT7, 0 } },
 167         { 0xfffe9812, 0, 16, 4, /* IPR15 */ { 0, RCAN0, RCAN1, 0 } },
 168         { 0xfffe9814, 0, 16, 4, /* IPR16 */ { SSI0_SSII, SSI1_SSII, TMR0, TMR1 } },
 169 };
 170
 171 static struct intc_mask_reg mask_registers[] __initdata = {
 172         { 0xfffe9408, 0, 16, /* PINTER */
 173           { 0, 0, 0, 0, 0, 0, 0, 0,
 174             PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
 175 };
 176
 177 static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups,
 178                          mask_registers, prio_registers, NULL);
 179
 180 static struct plat_sci_port scif0_platform_data = {
 181         .mapbase        = 0xfffe8000,
 182         .flags          = UPF_BOOT_AUTOCONF,
 183         .type           = PORT_SCIF,
 184         .irqs           = { 180, 180, 180, 180 }
 185 };
 186
 187 static struct platform_device scif0_device = {
 188         .name           = "sh-sci",
 189         .id             = 0,
 190         .dev            = {
 191                 .platform_data  = &scif0_platform_data,
 192         },
 193 };
 194
 195 static struct plat_sci_port scif1_platform_data = {
 196         .mapbase        = 0xfffe8800,
 197         .flags          = UPF_BOOT_AUTOCONF,
 198         .type           = PORT_SCIF,
 199         .irqs           = { 184, 184, 184, 184 }
 200 };
 201
 202 static struct platform_device scif1_device = {
 203         .name           = "sh-sci",
 204         .id             = 1,
 205         .dev            = {
 206                 .platform_data  = &scif1_platform_data,
 207         },
 208 };
 209
 210 static struct plat_sci_port scif2_platform_data = {
 211         .mapbase        = 0xfffe9000,
 212         .flags          = UPF_BOOT_AUTOCONF,
 213         .type           = PORT_SCIF,
 214         .irqs           = { 188, 188, 188, 188 }
 215 };
 216
 217 static struct platform_device scif2_device = {
 218         .name           = "sh-sci",
 219         .id             = 2,
 220         .dev            = {
 221                 .platform_data  = &scif2_platform_data,
 222         },
 223 };
 224
 225 static struct plat_sci_port scif3_platform_data = {
 226         .mapbase        = 0xfffe9800,
 227         .flags          = UPF_BOOT_AUTOCONF,
 228         .type           = PORT_SCIF,
 229         .irqs           = { 192, 192, 192, 192 }
 230 };
 231
 232 static struct platform_device scif3_device = {
 233         .name           = "sh-sci",
 234         .id             = 3,
 235         .dev            = {
 236                 .platform_data  = &scif3_platform_data,
 237         },
 238 };
 239
 240 static struct plat_sci_port scif4_platform_data = {
 241         .mapbase        = 0xfffea000,
 242         .flags          = UPF_BOOT_AUTOCONF,
 243         .type           = PORT_SCIF,
 244         .irqs           = { 196, 196, 196, 196 }
 245 };
 246
 247 static struct platform_device scif4_device = {
 248         .name           = "sh-sci",
 249         .id             = 4,
 250         .dev            = {
 251                 .platform_data  = &scif4_platform_data,
 252         },
 253 };
 254
 255 static struct plat_sci_port scif5_platform_data = {
 256         .mapbase        = 0xfffea800,
 257         .flags          = UPF_BOOT_AUTOCONF,
 258         .type           = PORT_SCIF,
 259         .irqs           = { 200, 200, 200, 200 }
 260 };
 261
 262 static struct platform_device scif5_device = {
 263         .name           = "sh-sci",
 264         .id             = 5,
 265         .dev            = {
 266                 .platform_data  = &scif5_platform_data,
 267         },
 268 };
 269
 270 static struct plat_sci_port scif6_platform_data = {
 271         .mapbase        = 0xfffeb000,
 272         .flags          = UPF_BOOT_AUTOCONF,
 273         .type           = PORT_SCIF,
 274         .irqs           = { 204, 204, 204, 204 }
 275 };
 276
 277 static struct platform_device scif6_device = {
 278         .name           = "sh-sci",
 279         .id             = 6,
 280         .dev            = {
 281                 .platform_data  = &scif6_platform_data,
 282         },
 283 };
 284
 285 static struct plat_sci_port scif7_platform_data = {
 286         .mapbase        = 0xfffeb800,
 287         .flags          = UPF_BOOT_AUTOCONF,
 288         .type           = PORT_SCIF,
 289         .irqs           = { 208, 208, 208, 208 }
 290 };
 291
 292 static struct platform_device scif7_device = {
 293         .name           = "sh-sci",
 294         .id             = 7,
 295         .dev            = {
 296                 .platform_data  = &scif7_platform_data,
 297         },
 298 };
 299
 300 static struct resource rtc_resources[] = {
 301         [0] = {
 302                 .start  = 0xffff0800,
 303                 .end    = 0xffff2000 + 0x58 - 1,
 304                 .flags  = IORESOURCE_IO,
 305         },
 306         [1] = {
 307                 /* Shared Period/Carry/Alarm IRQ */
 308                 .start  = 152,
 309                 .flags  = IORESOURCE_IRQ,
 310         },
 311 };
 312
 313 static struct platform_device rtc_device = {
 314         .name           = "sh-rtc",
 315         .id             = -1,
 316         .num_resources  = ARRAY_SIZE(rtc_resources),
 317         .resource       = rtc_resources,
 318 };
 319
 320 static struct sh_timer_config mtu2_0_platform_data = {
 321         .channel_offset = -0x80,
 322         .timer_bit = 0,
 323         .clockevent_rating = 200,
 324 };
 325
 326 static struct resource mtu2_0_resources[] = {
 327         [0] = {
 328                 .start  = 0xfffe4300,
 329                 .end    = 0xfffe4326,
 330                 .flags  = IORESOURCE_MEM,
 331         },
 332         [1] = {
 333                 .start  = 108,
 334                 .flags  = IORESOURCE_IRQ,
 335         },
 336 };
 337
 338 static struct platform_device mtu2_0_device = {
 339         .name           = "sh_mtu2",
 340         .id             = 0,
 341         .dev = {
 342                 .platform_data  = &mtu2_0_platform_data,
 343         },
 344         .resource       = mtu2_0_resources,
 345         .num_resources  = ARRAY_SIZE(mtu2_0_resources),
 346 };
 347
 348 static struct sh_timer_config mtu2_1_platform_data = {
 349         .channel_offset = -0x100,
 350         .timer_bit = 1,
 351         .clockevent_rating = 200,
 352 };
 353
 354 static struct resource mtu2_1_resources[] = {
 355         [0] = {
 356                 .start  = 0xfffe4380,
 357                 .end    = 0xfffe4390,
 358                 .flags  = IORESOURCE_MEM,
 359         },
 360         [1] = {
 361                 .start  = 116,
 362                 .flags  = IORESOURCE_IRQ,
 363         },
 364 };
 365
 366 static struct platform_device mtu2_1_device = {
 367         .name           = "sh_mtu2",
 368         .id             = 1,
 369         .dev = {
 370                 .platform_data  = &mtu2_1_platform_data,
 371         },
 372         .resource       = mtu2_1_resources,
 373         .num_resources  = ARRAY_SIZE(mtu2_1_resources),
 374 };
 375
 376 static struct sh_timer_config mtu2_2_platform_data = {
 377         .channel_offset = 0x80,
 378         .timer_bit = 2,
 379         .clockevent_rating = 200,
 380 };
 381
 382 static struct resource mtu2_2_resources[] = {
 383         [0] = {
 384                 .start  = 0xfffe4000,
 385                 .end    = 0xfffe400a,
 386                 .flags  = IORESOURCE_MEM,
 387         },
 388         [1] = {
 389                 .start  = 124,
 390                 .flags  = IORESOURCE_IRQ,
 391         },
 392 };
 393
 394 static struct platform_device mtu2_2_device = {
 395         .name           = "sh_mtu2",
 396         .id             = 2,
 397         .dev = {
 398                 .platform_data  = &mtu2_2_platform_data,
 399         },
 400         .resource       = mtu2_2_resources,
 401         .num_resources  = ARRAY_SIZE(mtu2_2_resources),
 402 };
 403
 404 static struct platform_device *sh7201_devices[] __initdata = {
 405         &scif0_device,
 406         &scif1_device,
 407         &scif2_device,
 408         &scif3_device,
 409         &scif4_device,
 410         &scif5_device,
 411         &scif6_device,
 412         &scif7_device,
 413         &rtc_device,
 414         &mtu2_0_device,
 415         &mtu2_1_device,
 416         &mtu2_2_device,
 417 };
 418
 419 static int __init sh7201_devices_setup(void)
 420 {
 421         return platform_add_devices(sh7201_devices,
 422                                     ARRAY_SIZE(sh7201_devices));
 423 }
 424 arch_initcall(sh7201_devices_setup);
 425
 426 void __init plat_irq_setup(void)
 427 {
 428         register_intc_controller(&intc_desc);
 429 }
 430
 431 static struct platform_device *sh7201_early_devices[] __initdata = {
 432         &scif0_device,
 433         &scif1_device,
 434         &scif2_device,
 435         &scif3_device,
 436         &scif4_device,
 437         &scif5_device,
 438         &scif6_device,
 439         &scif7_device,
 440         &mtu2_0_device,
 441         &mtu2_1_device,
 442         &mtu2_2_device,
 443 };
 444
 445 #define STBCR3 0xfffe0408
 446
 447 void __init plat_early_device_setup(void)
 448 {
 449         /* enable MTU2 clock */
 450         __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
 451
 452         early_platform_add_devices(sh7201_early_devices,
 453                                    ARRAY_SIZE(sh7201_early_devices));
 454 }