arch/sh/kernel/cpu/sh4a/setup-sh7763.c

   1 /*
   2  * SH7763 Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *  Copyright (C) 2007  Yoshihiro Shimoda
   6  *  Copyright (C) 2008, 2009  Nobuhiro Iwamatsu
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/platform_device.h>
  13 #include <linux/init.h>
  14 #include <linux/serial.h>
  15 #include <linux/sh_timer.h>
  16 #include <linux/io.h>
  17 #include <linux/serial_sci.h>
  18
  19 static struct resource rtc_resources[] = {
  20         [0] = {
  21                 .start  = 0xffe80000,
  22                 .end    = 0xffe80000 + 0x58 - 1,
  23                 .flags  = IORESOURCE_IO,
  24         },
  25         [1] = {
  26                 /* Shared Period/Carry/Alarm IRQ */
  27                 .start  = 20,
  28                 .flags  = IORESOURCE_IRQ,
  29         },
  30 };
  31
  32 static struct platform_device rtc_device = {
  33         .name           = "sh-rtc",
  34         .id             = -1,
  35         .num_resources  = ARRAY_SIZE(rtc_resources),
  36         .resource       = rtc_resources,
  37 };
  38
  39 static struct plat_sci_port sci_platform_data[] = {
  40         {
  41                 .mapbase        = 0xffe00000,
  42                 .flags          = UPF_BOOT_AUTOCONF,
  43                 .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  44                 .scbrr_algo_id  = SCBRR_ALGO_2,
  45                 .type           = PORT_SCIF,
  46                 .irqs           = { 40, 40, 40, 40 },
  47         }, {
  48                 .mapbase        = 0xffe08000,
  49                 .flags          = UPF_BOOT_AUTOCONF,
  50                 .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  51                 .scbrr_algo_id  = SCBRR_ALGO_2,
  52                 .type           = PORT_SCIF,
  53                 .irqs           = { 76, 76, 76, 76 },
  54         }, {
  55                 .mapbase        = 0xffe10000,
  56                 .flags          = UPF_BOOT_AUTOCONF,
  57                 .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
  58                 .scbrr_algo_id  = SCBRR_ALGO_2,
  59                 .type           = PORT_SCIF,
  60                 .irqs           = { 104, 104, 104, 104 },
  61         }, {
  62                 .flags = 0,
  63         }
  64 };
  65
  66 static struct platform_device sci_device = {
  67         .name           = "sh-sci",
  68         .id             = -1,
  69         .dev            = {
  70                 .platform_data  = sci_platform_data,
  71         },
  72 };
  73
  74 static struct resource usb_ohci_resources[] = {
  75         [0] = {
  76                 .start  = 0xffec8000,
  77                 .end    = 0xffec80ff,
  78                 .flags  = IORESOURCE_MEM,
  79         },
  80         [1] = {
  81                 .start  = 83,
  82                 .end    = 83,
  83                 .flags  = IORESOURCE_IRQ,
  84         },
  85 };
  86
  87 static u64 usb_ohci_dma_mask = 0xffffffffUL;
  88 static struct platform_device usb_ohci_device = {
  89         .name           = "sh_ohci",
  90         .id             = -1,
  91         .dev = {
  92                 .dma_mask               = &usb_ohci_dma_mask,
  93                 .coherent_dma_mask      = 0xffffffff,
  94         },
  95         .num_resources  = ARRAY_SIZE(usb_ohci_resources),
  96         .resource       = usb_ohci_resources,
  97 };
  98
  99 static struct resource usbf_resources[] = {
 100         [0] = {
 101                 .start  = 0xffec0000,
 102                 .end    = 0xffec00ff,
 103                 .flags  = IORESOURCE_MEM,
 104         },
 105         [1] = {
 106                 .start  = 84,
 107                 .end    = 84,
 108                 .flags  = IORESOURCE_IRQ,
 109         },
 110 };
 111
 112 static struct platform_device usbf_device = {
 113         .name           = "sh_udc",
 114         .id             = -1,
 115         .dev = {
 116                 .dma_mask               = NULL,
 117                 .coherent_dma_mask      = 0xffffffff,
 118         },
 119         .num_resources  = ARRAY_SIZE(usbf_resources),
 120         .resource       = usbf_resources,
 121 };
 122
 123 static struct sh_timer_config tmu0_platform_data = {
 124         .name = "TMU0",
 125         .channel_offset = 0x04,
 126         .timer_bit = 0,
 127         .clk = "peripheral_clk",
 128         .clockevent_rating = 200,
 129 };
 130
 131 static struct resource tmu0_resources[] = {
 132         [0] = {
 133                 .name   = "TMU0",
 134                 .start  = 0xffd80008,
 135                 .end    = 0xffd80013,
 136                 .flags  = IORESOURCE_MEM,
 137         },
 138         [1] = {
 139                 .start  = 28,
 140                 .flags  = IORESOURCE_IRQ,
 141         },
 142 };
 143
 144 static struct platform_device tmu0_device = {
 145         .name           = "sh_tmu",
 146         .id             = 0,
 147         .dev = {
 148                 .platform_data  = &tmu0_platform_data,
 149         },
 150         .resource       = tmu0_resources,
 151         .num_resources  = ARRAY_SIZE(tmu0_resources),
 152 };
 153
 154 static struct sh_timer_config tmu1_platform_data = {
 155         .name = "TMU1",
 156         .channel_offset = 0x10,
 157         .timer_bit = 1,
 158         .clk = "peripheral_clk",
 159         .clocksource_rating = 200,
 160 };
 161
 162 static struct resource tmu1_resources[] = {
 163         [0] = {
 164                 .name   = "TMU1",
 165                 .start  = 0xffd80014,
 166                 .end    = 0xffd8001f,
 167                 .flags  = IORESOURCE_MEM,
 168         },
 169         [1] = {
 170                 .start  = 29,
 171                 .flags  = IORESOURCE_IRQ,
 172         },
 173 };
 174
 175 static struct platform_device tmu1_device = {
 176         .name           = "sh_tmu",
 177         .id             = 1,
 178         .dev = {
 179                 .platform_data  = &tmu1_platform_data,
 180         },
 181         .resource       = tmu1_resources,
 182         .num_resources  = ARRAY_SIZE(tmu1_resources),
 183 };
 184
 185 static struct sh_timer_config tmu2_platform_data = {
 186         .name = "TMU2",
 187         .channel_offset = 0x1c,
 188         .timer_bit = 2,
 189         .clk = "peripheral_clk",
 190 };
 191
 192 static struct resource tmu2_resources[] = {
 193         [0] = {
 194                 .name   = "TMU2",
 195                 .start  = 0xffd80020,
 196                 .end    = 0xffd8002f,
 197                 .flags  = IORESOURCE_MEM,
 198         },
 199         [1] = {
 200                 .start  = 30,
 201                 .flags  = IORESOURCE_IRQ,
 202         },
 203 };
 204
 205 static struct platform_device tmu2_device = {
 206         .name           = "sh_tmu",
 207         .id             = 2,
 208         .dev = {
 209                 .platform_data  = &tmu2_platform_data,
 210         },
 211         .resource       = tmu2_resources,
 212         .num_resources  = ARRAY_SIZE(tmu2_resources),
 213 };
 214
 215 static struct sh_timer_config tmu3_platform_data = {
 216         .name = "TMU3",
 217         .channel_offset = 0x04,
 218         .timer_bit = 0,
 219         .clk = "peripheral_clk",
 220 };
 221
 222 static struct resource tmu3_resources[] = {
 223         [0] = {
 224                 .name   = "TMU3",
 225                 .start  = 0xffd88008,
 226                 .end    = 0xffd88013,
 227                 .flags  = IORESOURCE_MEM,
 228         },
 229         [1] = {
 230                 .start  = 96,
 231                 .flags  = IORESOURCE_IRQ,
 232         },
 233 };
 234
 235 static struct platform_device tmu3_device = {
 236         .name           = "sh_tmu",
 237         .id             = 3,
 238         .dev = {
 239                 .platform_data  = &tmu3_platform_data,
 240         },
 241         .resource       = tmu3_resources,
 242         .num_resources  = ARRAY_SIZE(tmu3_resources),
 243 };
 244
 245 static struct sh_timer_config tmu4_platform_data = {
 246         .name = "TMU4",
 247         .channel_offset = 0x10,
 248         .timer_bit = 1,
 249         .clk = "peripheral_clk",
 250 };
 251
 252 static struct resource tmu4_resources[] = {
 253         [0] = {
 254                 .name   = "TMU4",
 255                 .start  = 0xffd88014,
 256                 .end    = 0xffd8801f,
 257                 .flags  = IORESOURCE_MEM,
 258         },
 259         [1] = {
 260                 .start  = 97,
 261                 .flags  = IORESOURCE_IRQ,
 262         },
 263 };
 264
 265 static struct platform_device tmu4_device = {
 266         .name           = "sh_tmu",
 267         .id             = 4,
 268         .dev = {
 269                 .platform_data  = &tmu4_platform_data,
 270         },
 271         .resource       = tmu4_resources,
 272         .num_resources  = ARRAY_SIZE(tmu4_resources),
 273 };
 274
 275 static struct sh_timer_config tmu5_platform_data = {
 276         .name = "TMU5",
 277         .channel_offset = 0x1c,
 278         .timer_bit = 2,
 279         .clk = "peripheral_clk",
 280 };
 281
 282 static struct resource tmu5_resources[] = {
 283         [0] = {
 284                 .name   = "TMU5",
 285                 .start  = 0xffd88020,
 286                 .end    = 0xffd8802b,
 287                 .flags  = IORESOURCE_MEM,
 288         },
 289         [1] = {
 290                 .start  = 98,
 291                 .flags  = IORESOURCE_IRQ,
 292         },
 293 };
 294
 295 static struct platform_device tmu5_device = {
 296         .name           = "sh_tmu",
 297         .id             = 5,
 298         .dev = {
 299                 .platform_data  = &tmu5_platform_data,
 300         },
 301         .resource       = tmu5_resources,
 302         .num_resources  = ARRAY_SIZE(tmu5_resources),
 303 };
 304
 305 static struct platform_device *sh7763_devices[] __initdata = {
 306         &tmu0_device,
 307         &tmu1_device,
 308         &tmu2_device,
 309         &tmu3_device,
 310         &tmu4_device,
 311         &tmu5_device,
 312         &rtc_device,
 313         &sci_device,
 314         &usb_ohci_device,
 315         &usbf_device,
 316 };
 317
 318 static int __init sh7763_devices_setup(void)
 319 {
 320         return platform_add_devices(sh7763_devices,
 321                                     ARRAY_SIZE(sh7763_devices));
 322 }
 323 __initcall(sh7763_devices_setup);
 324
 325 static struct platform_device *sh7763_early_devices[] __initdata = {
 326         &tmu0_device,
 327         &tmu1_device,
 328         &tmu2_device,
 329         &tmu3_device,
 330         &tmu4_device,
 331         &tmu5_device,
 332 };
 333
 334 void __init plat_early_device_setup(void)
 335 {
 336         early_platform_add_devices(sh7763_early_devices,
 337                                    ARRAY_SIZE(sh7763_early_devices));
 338 }
 339
 340 enum {
 341         UNUSED = 0,
 342
 343         /* interrupt sources */
 344
 345         IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 346         IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 347         IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 348         IRL_HHLL, IRL_HHLH, IRL_HHHL,
 349
 350         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 351         RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
 352         HUDI, LCDC, DMAC, SCIF0, IIC0, IIC1, CMT, GETHER, HAC,
 353         PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
 354         STIF0, STIF1, SCIF1, SIOF0, SIOF1, SIOF2,
 355         USBH, USBF, TPU, PCC, MMCIF, SIM,
 356         TMU3, TMU4, TMU5, ADC, SSI0, SSI1, SSI2, SSI3,
 357         SCIF2, GPIO,
 358
 359         /* interrupt groups */
 360
 361         TMU012, TMU345,
 362 };
 363
 364 static struct intc_vect vectors[] __initdata = {
 365         INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
 366         INTC_VECT(RTC, 0x4c0),
 367         INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580),
 368         INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0),
 369         INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600),
 370         INTC_VECT(LCDC, 0x620),
 371         INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
 372         INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
 373         INTC_VECT(DMAC, 0x6c0),
 374         INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
 375         INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
 376         INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
 377         INTC_VECT(IIC0, 0x8A0), INTC_VECT(IIC1, 0x8C0),
 378         INTC_VECT(CMT, 0x900), INTC_VECT(GETHER, 0x920),
 379         INTC_VECT(GETHER, 0x940), INTC_VECT(GETHER, 0x960),
 380         INTC_VECT(HAC, 0x980),
 381         INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
 382         INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
 383         INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
 384         INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
 385         INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
 386         INTC_VECT(STIF0, 0xb40), INTC_VECT(STIF1, 0xb60),
 387         INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
 388         INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
 389         INTC_VECT(SIOF0, 0xc00), INTC_VECT(SIOF1, 0xc20),
 390         INTC_VECT(USBH, 0xc60), INTC_VECT(USBF, 0xc80),
 391         INTC_VECT(USBF, 0xca0),
 392         INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0),
 393         INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
 394         INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
 395         INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
 396         INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
 397         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 398         INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60),
 399         INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
 400         INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0),
 401         INTC_VECT(SCIF2, 0xf00), INTC_VECT(SCIF2, 0xf20),
 402         INTC_VECT(SCIF2, 0xf40), INTC_VECT(SCIF2, 0xf60),
 403         INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
 404         INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
 405 };
 406
 407 static struct intc_group groups[] __initdata = {
 408         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 409         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 410 };
 411
 412 static struct intc_mask_reg mask_registers[] __initdata = {
 413         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 414           { 0, 0, 0, 0, 0, 0, GPIO, 0,
 415             SSI0, MMCIF, 0, SIOF0, PCIC5, PCIINTD, PCIINTC, PCIINTB,
 416             PCIINTA, PCISERR, HAC, CMT, 0, 0, 0, DMAC,
 417             HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
 418         { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
 419           { 0, 0, 0, 0, 0, 0, SCIF2, USBF,
 420             0, 0, STIF1, STIF0, 0, 0, USBH, GETHER,
 421             PCC, 0, 0, ADC, TPU, SIM, SIOF2, SIOF1,
 422             LCDC, 0, IIC1, IIC0, SSI3, SSI2, SSI1, 0 } },
 423 };
 424
 425 static struct intc_prio_reg prio_registers[] __initdata = {
 426         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
 427                                                  TMU2, TMU2_TICPI } },
 428         { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
 429         { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
 430         { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC, ADC } },
 431         { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
 432                                                  PCISERR, PCIINTA } },
 433         { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
 434                                                  PCIINTD, PCIC5 } },
 435         { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF0, USBF, MMCIF, SSI0 } },
 436         { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SCIF2, GPIO } },
 437         { 0xffd400a0, 0, 32, 8, /* INT2PRI8 */ { SSI3, SSI2, SSI1, 0 } },
 438         { 0xffd400a4, 0, 32, 8, /* INT2PRI9 */ { LCDC, 0, IIC1, IIC0 } },
 439         { 0xffd400a8, 0, 32, 8, /* INT2PRI10 */ { TPU, SIM, SIOF2, SIOF1 } },
 440         { 0xffd400ac, 0, 32, 8, /* INT2PRI11 */ { PCC } },
 441         { 0xffd400b0, 0, 32, 8, /* INT2PRI12 */ { 0, 0, USBH, GETHER } },
 442         { 0xffd400b4, 0, 32, 8, /* INT2PRI13 */ { 0, 0, STIF1, STIF0 } },
 443 };
 444
 445 static DECLARE_INTC_DESC(intc_desc, "sh7763", vectors, groups,
 446                          mask_registers, prio_registers, NULL);
 447
 448 /* Support for external interrupt pins in IRQ mode */
 449 static struct intc_vect irq_vectors[] __initdata = {
 450         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 451         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 452         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 453         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 454 };
 455
 456 static struct intc_mask_reg irq_mask_registers[] __initdata = {
 457         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 458           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 459 };
 460
 461 static struct intc_prio_reg irq_prio_registers[] __initdata = {
 462         { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
 463                                                IRQ4, IRQ5, IRQ6, IRQ7 } },
 464 };
 465
 466 static struct intc_sense_reg irq_sense_registers[] __initdata = {
 467         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 468                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 469 };
 470
 471 static struct intc_mask_reg irq_ack_registers[] __initdata = {
 472         { 0xffd00024, 0, 32, /* INTREQ */
 473           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 474 };
 475
 476 static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7763-irq", irq_vectors,
 477                              NULL, irq_mask_registers, irq_prio_registers,
 478                              irq_sense_registers, irq_ack_registers);
 479
 480
 481 /* External interrupt pins in IRL mode */
 482 static struct intc_vect irl_vectors[] __initdata = {
 483         INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
 484         INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
 485         INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
 486         INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
 487         INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
 488         INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
 489         INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
 490         INTC_VECT(IRL_HHHL, 0x3c0),
 491 };
 492
 493 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
 494         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 495           { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 496             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 497             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 498             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 499 };
 500
 501 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
 502         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 503           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 504             IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 505             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 506             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 507             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 508 };
 509
 510 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7763-irl7654", irl_vectors,
 511                         NULL, irl7654_mask_registers, NULL, NULL);
 512
 513 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7763-irl3210", irl_vectors,
 514                         NULL, irl3210_mask_registers, NULL, NULL);
 515
 516 #define INTC_ICR0       0xffd00000
 517 #define INTC_INTMSK0    0xffd00044
 518 #define INTC_INTMSK1    0xffd00048
 519 #define INTC_INTMSK2    0xffd40080
 520 #define INTC_INTMSKCLR1 0xffd00068
 521 #define INTC_INTMSKCLR2 0xffd40084
 522
 523 void __init plat_irq_setup(void)
 524 {
 525         /* disable IRQ7-0 */
 526         ctrl_outl(0xff000000, INTC_INTMSK0);
 527
 528         /* disable IRL3-0 + IRL7-4 */
 529         ctrl_outl(0xc0000000, INTC_INTMSK1);
 530         ctrl_outl(0xfffefffe, INTC_INTMSK2);
 531
 532         register_intc_controller(&intc_desc);
 533 }
 534
 535 void __init plat_irq_setup_pins(int mode)
 536 {
 537         switch (mode) {
 538         case IRQ_MODE_IRQ:
 539                 /* select IRQ mode for IRL3-0 + IRL7-4 */
 540                 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
 541                 register_intc_controller(&intc_irq_desc);
 542                 break;
 543         case IRQ_MODE_IRL7654:
 544                 /* enable IRL7-4 but don't provide any masking */
 545                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
 546                 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
 547                 break;
 548         case IRQ_MODE_IRL3210:
 549                 /* enable IRL0-3 but don't provide any masking */
 550                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
 551                 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
 552                 break;
 553         case IRQ_MODE_IRL7654_MASK:
 554                 /* enable IRL7-4 and mask using cpu intc controller */
 555                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
 556                 register_intc_controller(&intc_irl7654_desc);
 557                 break;
 558         case IRQ_MODE_IRL3210_MASK:
 559                 /* enable IRL0-3 and mask using cpu intc controller */
 560                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
 561                 register_intc_controller(&intc_irl3210_desc);
 562                 break;
 563         default:
 564                 BUG();
 565         }
 566 }